Patent application number | Description | Published |
20080263485 | Verification support method and apparatus, and computer product - A verification support apparatus that verifies operation of a circuit includes a receiving unit, a detecting unit, and a determining unit. The receiving unit receives implementation description data of the circuit. Based on the implementation description data, the detecting unit detects a functional block that is in the circuit and includes an external input terminal that receives an external input signal. Based on a detection result of the detecting unit, the determining unit determines the functional block to verify an abnormal-event operation. The abnormal-event operation is an operation that differs from an operation implementing a function of the circuit. | 10-23-2008 |
20090259610 | VERIFICATION SUPPORT APPARATUS, VERIFICATION SUPPORT METHOD, AND COMPUTER PRODUCT - A verification support apparatus includes an identifying unit that, by using a pre-change specification and a post-change specification given before and after a specification change in a subject to be verified, identifies an area that has changed from among a plurality of specification items included in the post-change specification and a selecting unit that selects a specification item from among the areas identified by the identifying unit. The verification support apparatus further includes a searching unit that, by referring a transition graph concerning the specification items included in the post-change specification and by tracing specification items as origins of transitions from a starting point that is the specification item selected by the selecting unit, searches for a route made up of specification items affected by the specification change; and an output unit that outputs a search result of the searching unit. | 10-15-2009 |
20090276740 | VERIFICATION SUPPORTING APPARATUS, VERIFICATION SUPPORTING METHOD, AND COMPUTER PRODUCT - In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output. | 11-05-2009 |
20090287965 | VERIFICATION SUPPORTING SYSTEM - A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard. | 11-19-2009 |
20090326906 | VERIFICATION SUPPORT APPARATUS, VERIFICATION SUPPORT METHOD, AND COMPUTER PRODUCT - A computer-readable recording medium stores therein a verification support program that causes a computer to execute selecting arbitrarily a use case from a use case diagram for a verification target; extracting a precondition and a postcondition of the use case selected at the selecting; and converting, to a Kripke model, a finite state machine model corresponding to the use case selected at the selecting. The verification support program further causes the computer to execute specifying, based on the precondition and the postcondition extracted at the extracting, a Kripke initial state, a Kripke precondition, and a Kripke postcondition of the Kripke model obtained at the converting; and generating, based on the Kripke precondition and the Kripke postcondition specified at the specifying, a Kripke property of the use case selected at the selecting. | 12-31-2009 |
20100058262 | VERIFICATION ASSISTING PROGRAM, VERIFICATION ASSISTING APPARATUS, AND VERIFICATION ASSISTING METHOD - A verification assisting apparatus for assisting a matching check between a specification and implementation of an object includes: an obtaining unit that obtains a specification description including elements executed to realize functions of the object and restricting conditions of the elements to realize the functions, and an implementation description concerning the functions; a creating unit that creates a graph structure including, as nodes, the elements and the restricting conditions, based on the implementation description; a first correlating unit that correlates nodes in the graph structure with the implementation description; a second correlating unit that correlates a node in the graph structure with the specification description, by detecting the node in the structure using a description concerning the element or the restricting condition in the specification description; and an outputting unit that outputs the correlation results. | 03-04-2010 |
20100064266 | VERIFICATION SUPPORT APPARATUS, VERIFICATION SUPPORT METHOD, AND COMPUTER PRODUCT - A computer-readable recording medium stores therein a verification support program that causes a computer to execute receiving a hardware description of a combinational circuit to be verified; extracting, from the hardware description, a conditional branch description expressing conditional branch processing; identifying, from among conditional branch descriptions extracted at the extracting of a conditional branch description and based on a description sequence in the hardware description, a combination of conditional branch descriptions having a hierarchical relation; extracting, from among combinations of conditional branch descriptions identified at the identifying, a combination having a potential to satisfy a specified condition; creating a simulation program that causes the specified condition for the conditional branch descriptions included in the combination extracted at the extracting of the combination to be satisfied; and outputting, as assertion information of the combinational circuit, the simulation program created for each combination at the creating. | 03-11-2010 |
20100083204 | VERIFICATION SUPPORT APPARATUS, VERIFICATION SUPPORT METHOD, AND COMPUTER PRODUCT - A computer-readable recording medium stores therein a verification support program that causes a computer to execute receiving a hardware description of a sequential circuit to be verified and a timing specification that indicates a timing constraint in the hardware description; converting the hardware description into a control flow graph that expresses a flow of control in the sequential circuit; indentifying, from the control flow graph and as a combination of conditional branch descriptions having a hierarchical relation, conditional branch descriptions that are connected in parallel; extracting, from among identified combinations of conditional branch descriptions, a combination having a potential to satisfy specified conditions; creating a simulation program that, at a timing satisfying the timing specification, causes the conditional branch descriptions included in the extracted combination to satisfy the specified conditions; and outputting, as assertion information of the sequential circuit, the simulation program created at the creating. | 04-01-2010 |
20110119655 | COMPUTER PRODUCT, VERIFICATION SUPPORT APPARATUS, AND VERIFICATION SUPPORT METHOD - A non-transitory, recording medium stores therein a program that causes a computer to execute extracting from hardware description of a circuit, a conditional branch statement representing a conditional branch process; determining whether the extracted conditional branch statement includes at least three condition expressions, where a given combination thereof has exclusive satisfying conditions; extracting from the conditional branch statement determined at the determining, a combination of condition expressions for which satisfying conditions are exclusive; extracting each condition expression from the extracted combination and creating, for each extracted condition expression and according to an order of appearance in the hardware description, a conditional branch statement in which the extracted condition expression has a hierarchical relationship with a condition expression not included in the combination; generating an assertion for checking whether a specified condition is satisfied in each created conditional branch statement; and outputting, as assertion data of the circuit, the generated assertion. | 05-19-2011 |
20110239172 | VERIFICATION SUPPORTING SYSTEM - A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard. | 09-29-2011 |
20120240120 | INFORMATION PROCESSING APPARATUS, POWER CONTROL METHOD, AND COMPUTER PRODUCT - An information processing apparatus includes a first detector that detects a scheduled starting time of an event to be corrected and executed at the current time or thereafter; a second detector that detects in processing contents differing from that of the event detected by the first detector, a scheduled starting time of each event to be executed at the current time or thereafter; a calculator that calculates the difference between the scheduled starting time detected by the first detector and each scheduled starting time detected by the second detector; a determiner that determines a target event for the event to be corrected, based on the calculated differences; and a corrector that corrects the scheduled starting time of the event to be corrected such that an interval becomes short between the scheduled starting time of the event to be corrected and the scheduled starting time of the target event. | 09-20-2012 |
20130117720 | COMPUTER PRODUCT FOR SUPPORTING DESIGN AND VERIFICATION OF INTEGRATED CIRCUIT - Design and verification support related to integrated circuits that includes acquiring a first use case diagram representing a function of an object subject to design and verification and an activity diagram representing a processing procedure of the object; analyzing a structure of the activity diagram acquired at the acquiring step; converting the activity diagram to a second use case diagram representing a function of the object, based on the structure analyzed at the analyzing; verifying uniformity of the first use case diagram and the second use case diagram; and outputting a verification result obtained at the verifying uniformity. | 05-09-2013 |