Patent application number | Description | Published |
20090161287 | ELECTRONIC DEVICE OPERABLE TO PROTECT A POWER TRANSISTOR WHEN USED IN CONJUNCTION WITH A TRANSFORMER - An electronic device can be used with a system, such as an ignition system, that operates a relatively high voltage. The device can include a signal clamping control module that can include a signal reference module and a feedback control module. The signal reference module is operable to provide a reference signal to the feedback control module. The feedback control can be configured to receive a scaled signal from a signal scaling module, wherein the scaled signal is representative of a signal at a current carrying electrode of a power transistor. Based on the comparison of the reference signal to the scaled signal, the measurement module provides one or more signals to a control signal drive module. The feedback control module provides a control electrode signal to a control electrode of the power transistor. | 06-25-2009 |
20110115527 | METHOD AND DETECTOR FOR DETERMINING A STATE OF A SWITCH - In an integrated circuit, a state of a switch coupled to the integrated circuit is determined by comparing a switch voltage at a first terminal of the switch to a reference voltage at a first time. If the switch voltage is higher than the reference voltage, the switch is determined to be in a first state. If the switch voltage is lower than the reference voltage, the switch voltage is stored in a storage element to produce a stored voltage. The stored voltage is compared to the switch voltage at a second time after the first time. A determination is made that the switch is in the first state if the switch voltage is higher than the stored voltage at the second time. A determination is made that the switch is in a second state if the switch voltage is not higher than the stored voltage at the second time. | 05-19-2011 |
20130328554 | VRS INTERFACE WITH 1/T ARMING FUNCTION - A variable reluctance sensor system for processing a variable reluctance sensor signal including an arming comparator and an arming circuit. The arming comparator compares the variable reluctance sensor signal with an arming threshold which decreases proportional to 1/t from a predetermined maximum level and asserts an armed signal when the variable reluctance sensor signal reaches the arming threshold. The arming threshold may be decreased based on a scaling factor multiplied by 1/t to ensure detection of each pulse of the variable reluctance sensor signal. The arming threshold may decrease to a predetermined minimum level sufficiently low to intersect the variable reluctance sensor signal and sufficiently high relative to an expected noise level. The arming threshold is reset in response to a timing event, such as zero crossing of the variable reluctance sensor signal. | 12-12-2013 |
20140035561 | VARIABLE RELUCTANCE SENSOR INTERFACE WITH INTEGRATION BASED ARMING THRESHOLD - An interface for processing a variable reluctance sensor signal provided by a variable reluctance sensor including an integrator, an arming comparator and a detect circuit. The integrator includes an input for receiving the variable reluctance sensor signal and an output providing an integrated signal indicative of total flux change of the variable reluctance sensor. The arming comparator compares the integrated signal with a predetermined arming threshold and provides an armed signal indicative thereof. The detect circuit provides a reset signal after the armed signal is provided to reset the integrator. A corresponding method of processing the variable reluctance sensor signal is also described. | 02-06-2014 |
20150067429 | WAFER-LEVEL GATE STRESS TESTING - A method of testing a semiconductor device includes forming a test circuit over a semiconductor substrate. The test circuit includes a plurality of interconnects electrically connected to a set of device structures supported by the semiconductor substrate. A test, such as a gate stress or leakage current test, of each device structure is conducted with the test circuit. The plurality of interconnects are removed after conducting the test. | 03-05-2015 |
20150075401 | SQUIB DRIVER DIAGNOSTIC CIRCUIT AND METHOD - A diagnostic circuit is provided that includes a FET having a source connected to a first node, a drain, and a gate; a first switch connecting a current-supply node to one of the gate and a second node; a second switch connecting the first node and the second node; a variable current source providing one of a drive current and a test current to the current-supply node; a fire current source configured to provide a fire current to the drain; an error-detecting circuit connected to the second node, a reference terminal, and an error node, the error-detecting circuit generating an error signal to the error node indicating whether an error-detecting parameter at the second node exceeds a reference parameter at the reference terminal; and a control circuit generating control signals to control the variable current source, and the first and second switches. | 03-19-2015 |
Patent application number | Description | Published |
20080232253 | PORT RATE SMOOTHING IN AN AVIONICS NETWORK - A communication network is provided. The network includes a least one switch and a plurality of ports. Each port is in communication with the at least one switch. At least one of the ports is configured to introduce a time delay after each transmission of a frame based at least in part on a maximum transmission rate of the at least one port and its allocated transmission rate. | 09-25-2008 |
20100195491 | BOUNDED MINIMAL LATENCY FOR NETWORK RESOURCES WITHOUT SYNCHRONIZATION - Systems and methods for bounded minimal latency for network resources without synchronization are provided. In one embodiment, a method for managing data traffic between nodes in an asynchronous network comprises: receiving a data request message at a first port of network switch; storing information about the data request message in a memory at the network switch; forwarding the data request message to a producer node; receiving a data message at a second port of the network switch; determining whether the data message is responsive to the data request message; when the data message is responsive, forwarding the data message from the network switch; and when the data message is not responsive, blocking the data message from being forwarded from the network. | 08-05-2010 |
20110087847 | MULTIPLE-PORT MEMORY SYSTEMS AND METHODS - Systems and methods for improved multiple-port memory are provided. In one embodiment, a processing system comprises: at least one processing core; a peripheral bus; and a memory for storing digital data, the memory divided into a first and a second partition of memory segments. The memory includes a first port coupled to the peripheral bus providing read access and write access only to the first partition, wherein the first partition stores peripheral data associated with one or more peripheral components coupled to the peripheral bus; a second port coupled to the at least one processor providing read-only access to only the second partition, wherein the second partition stores executable code for the at least one processing core; and a third port coupled to the at least one processor providing read access and write access to the entire first partition and the second partition. | 04-14-2011 |
20110107022 | REDUCING POWER CONSUMPTION FOR DYNAMIC MEMORIES USING DISTRIBUTED REFRESH CONTROL - A method for refreshing memory is provided. The method comprises determining when a first memory of a plurality of memories is not being accessed and sending a refresh opportunity command from a master refresh controller to one of a plurality of local refresh controllers when the first memory is not being accessed, wherein the one of a plurality of local refresh controllers controls only the first memory. The method further comprises determining when the first memory needs refreshing and refreshing the first memory. | 05-05-2011 |
20110131377 | MULTI-CORE PROCESSING CACHE IMAGE MANAGEMENT - A multi-core processor chip comprises at least one shared cache having a plurality of ports and a plurality of address spaces and a plurality of processor cores. Each processor core is coupled to one of the plurality of ports such that each processor core is able to access the at least one shared cache simultaneously with another of the plurality of processor cores. Each processor core is assigned one of a unique application or a unique application task and the multi-core processor is operable to execute a partitioning operating system that temporally and spatially isolates each unique application and each unique application task such that each of the plurality of processor cores does not attempt to write to the same address space of the at least one shared cache at the same time as another of the plurality of processor cores. | 06-02-2011 |
20110214043 | HIGH INTEGRITY DATA BUS FAULT DETECTION USING MULTIPLE SIGNAL COMPONENTS - Methods and apparatus are provided for verifying the integrity of a signal transmitted across a multiple rail data bus. The method and apparatus provide for independently processing a signal by a first processor and a second processor, the first and second processors being connected in parallel thereby generating a first processed signal and a second processed signal. Each of the processed signals is split into a first component sequence and a second component sequence, the first component sequences being different from the second component sequences. It is then determined that the first component sequences are not identical and that the second component sequences are not identical. If either of the first component sequences is not identical, or if either of the second component sequences is not identical, then an error signal is transmitted to a receiving device via a first or second rail of the bus. | 09-01-2011 |
20120030519 | INTEGRATED DISSIMILAR HIGH INTEGRITY PROCESSING - A self-checking network is provided, comprising a first command processor configured to execute a performance function and a second command processor configured to execute the performance function, coupled to the first command processor. The self-checking network also comprises a first monitor processor configured to execute a monitor function that is coupled to the first command processor and a second monitor processor configured to execute the monitor function that is coupled to the second command processor. The first and second command processors compare outputs, the first and second monitor processors compare outputs, and the first monitor processor determines whether an output of the first command processor exceeds a first selected limit. | 02-02-2012 |
20130191584 | DETERMINISTIC HIGH INTEGRITY MULTI-PROCESSOR SYSTEM ON A CHIP - Systems integrated into a single electronic chip are provided for. The systems include a primary shared bus, a secondary shared bus and an embedded dynamic random access memory (eDRAM) including a first port and a second port. The systems also include a primary processor in operable communication with the eDRAM via the first port; and a secondary processor in operable communication with the eDRAM via the secondary bus and the second port, wherein the primary and secondary processors are operating in synchronization. | 07-25-2013 |
20140376570 | SYSTEMS AND METHODS FOR SELF-CHECKING PAIR - Systems and methods for a self-checking pair are provided. In certain embodiments a system on chip in a self-checking pair includes a system architecture; a plurality of communication channels configured for communicating data with an external system; and an integrated system on chip logic configured to collect the data communicated through the plurality of communication channels and transmit the data to a second system on chip and handle received data from the second system on chip, wherein the integrated system on chip logic determines whether the data communicated through the plurality of communication channels matches the received data from the second system on chip. | 12-25-2014 |
20140380020 | SYSTEM AND METHODS FOR SYNCHRONIZATION OF REDUNDANT PROCESSING ELEMENTS - System and methods for synchronizing redundant processing elements are provided. In certain embodiments, a self-checking pair of system on chips (SoCs) includes a first SoC configured to execute a first plurality of instructions; and a second SoC configured to execute a second plurality of instructions that are approximately identical; wherein the first SoC exchanges a first instruction count with the second SoC, the first instruction count identifying a number of instructions executed by the first SoC; wherein the second SoC exchanges a second instruction count with the first SoC, the second instruction count identifying a number of instructions executed by the second SoC; and wherein the first SoC executes a first single step execution utility to synchronize the first instruction count with the second instruction count and the second SoC executes a second single step execution utility to synchronize the first instruction count with the second instruction count. | 12-25-2014 |
Patent application number | Description | Published |
20090157555 | BILL PAYMENT SYSTEM AND METHOD - Automated authorization and processing of an interim payment is disclosed. When a merchant requests payment prior to a recurring payment process being enabled, the system handles the payment request without customer intervention. The system requests and receives a transaction coordination code for an interim payment from a financial processor. The system passes the interim payment transaction coordination code to the merchant so the merchant may obtain an authorized payment. | 06-18-2009 |
20090327131 | DYNAMIC ACCOUNT AUTHENTICATION USING A MOBILE DEVICE - Providing dynamic authentication of a user requesting access to a system via a mobile device is disclosed. An account holder tailors a set of customized security challenges and responses. When a request for account authentication is received from a mobile device, the system conducts a multi-step user authentication process that includes dynamically selecting and prompting the user with the custom security challenges. | 12-31-2009 |
20100120408 | SERVICING ATTRIBUTES ON A MOBILE DEVICE - Enabling remote customer service and maintenance using a visual identifier is disclosed. In response to a user enrolling in a service capability associated with a mobile device, the process utilizes a visual identifier to associate the service capability with the customer account, the service and the mobile device. The system allocates a visual identifier for each service capability and enables customer service agents to identify the service capability and mobile device, verify the user and retrieve information for the service interaction. | 05-13-2010 |
20100161493 | METHODS, APPARATUS AND COMPUTER PROGRAM PRODUCTS FOR SECURELY ACCESSING ACCOUNT DATA - Customer data is securely downloaded to a browser toolbar by performing a check to determine whether a request for customer data includes a request for personal identifiable information requiring encryption by a public encryption key generated by the browser toolbar. The customer is authenticated based on a set of a user credential and an account specific access credential. The account specific access credential is associated with the account of the customer. Requested personal identifiable information is encrypted using the public encryption key generated by the browser toolbar. Encrypted personal identifiable information is transmitted to the browser toolbar. | 06-24-2010 |
20110060687 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ISSUING AND USING DEBIT CARDS - A system, method, and computer program product are used to issue and track debit cards. A system comprises an enrolling system that verifies an enrollee, associates an enrollee's main and overdraft account, and issues a debit card, an authentication system that receives information regarding a requested transaction of a debit card and that receives information regarding the main and overdraft account associated with the debit card and accepts or rejects the requested transaction based thereon, and a settlement system that generates a periodic report of at least one of the transactions, the main account, and the overdraft account. The overdraft account can be a charge or credit account. | 03-10-2011 |
20150161607 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ISSUING AND USING DEBIT CARDS - A system, method, and computer program product are used to issue and track debit cards. A system comprises an enrolling system that verifies an enrollee, associates an enrollee's main and overdraft account, and issues a debit card, an authentication system that receives information regarding a requested transaction of a debit card and that receives information regarding the main and overdraft account associated with the debit card and accepts or rejects the requested transaction based thereon, and a settlement system that generates a periodic report of at least one of the transactions, the main account, and the overdraft account. The overdraft account can be a charge or credit account. | 06-11-2015 |