Patent application number | Description | Published |
20080232185 | Structure and Method of Implementing Power Savings During Addressing of DRAM Architectures - A random access memory device includes an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Address decoder logic in signal communication with the array is configured to receive a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated. | 09-25-2008 |
20090006706 | Structure for Hub for Supporting High Capacity Memory Subsystem - A design structure is provided for a hub for use in a high-capacity memory subsystem in which memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving | 01-01-2009 |
20090006760 | Structure for Dual-Mode Memory Chip for High Capacity Memory Subsystem - A design structure is provided for a dual-mode memory chip supporting a first operation mode in which received data access commands contain chip select data to identify the chip addressed by the command, and control logic in the memory chip determines whether the command is addressed to the chip, and a second operation mode in which the received data access command addresses a set of multiple chips. Preferably, the first mode supports a daisy-chained configuration of memory chips. Preferably the second mode supports a hierarchical interleaved memory subsystem, in which each addressable set of chips is configured as a tree, command and write data being propagated down the tree, the number of chips increasing at each succeeding level of the tree. | 01-01-2009 |
20090006781 | Structure for Memory Chip for High Capacity Memory Subsystem Supporting Multiple Speed Bus - A design structure is provided for a memory module containing an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Preferably, the memory module contains a second interface for re-transmitting memory access data, also operating at dual frequency. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports dual-speed buses for receiving and re-transmitting different parts of data access commands, and another of which supports conventional daisy-chaining. | 01-01-2009 |
20090006798 | Structure for Memory Chip for High Capacity Memory Subsystem Supporting Replication of Command Data - A design structure is provided for a memory module containing a first interface for receiving data access commands and a second interface for re-transmitting data access commands to other memory modules, the second interface propagating multiple copies of received data access commands to multiple other memory modules. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports multiple replication of commands and another of which supports conventional daisy-chaining | 01-01-2009 |
20090031067 | Spider Web Interconnect Topology Utilizing Multiple Port Connection - A data communications apparatus includes a central device and a plurality of communication devices. The central device includes a plurality of central port pairs, in which each central port pair includes an input port and an output port. The plurality of communication devices is arranged in a spoke and ring configuration, in which each communication device is part of a communication spoke. Each communication spoke is in communication with a different central port pair. Each communication device is also a part of a communication ring, so that each communication device in a selected communication ring belongs to a different communication spoke. | 01-29-2009 |
20090196118 | Design Structure Of Implementing Power Savings During Addressing Of DRAM Architectures - A design structure embodied in a machine readable medium used in a design process includes random access memory device having an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Logic in signal communication with the array receives a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated. | 08-06-2009 |
20090217281 | Adaptable Redundant Bit Steering for DRAM Memory Failures - A method, computer program product and computer system for assigning computing resources in a computer system to solve multiple problems where tolerances to the problems are countable and have pre-set thresholds, and solutions to the problems share resources exclusively. The method, computer program product and system include counting the tolerances using at least one counter, assigning resources to solve a problem if the tolerance to the problem is higher than a first pre-set threshold, and reassigning resources to solve a second problem if the tolerance to the second problem is higher than a second pre-set threshold. The method, computer program product and system can also adopt an alternative solution that does not share resources exclusively with a current solution to solve the problems. | 08-27-2009 |
20090249093 | Design Structure for Selecting Processors for Job Scheduling Using Measured Power Consumption - In a design structure for allocating a plurality of parts of a computational system to a computational job, a set of requirements necessary to execute the job is determined. A set of parts of the plurality of parts is assembled so that the set of parts is capable of meeting the set of requirements and so that a part is added to the set of parts based on a determination that the addition of the part will minimize power consumption by the set of parts. The set of parts are caused to execute the job. | 10-01-2009 |
20110238879 | SORTING MOVABLE MEMORY HIERARCHIES IN A COMPUTER SYSTEM - Method and apparatus for optimally placing memory devices within a computer system. A memory controller may include circuitry configured to retrieve or one or more performance metrics a plurality of memory devices connected thereto. Based on the performance metrics and one or more predefined rules for placing memory devices, the circuitry may determine an optimal placement of the memory devices in the system. | 09-29-2011 |
20120124415 | MEMORY MIRRORING WITH MEMORY COMPRESSION - Systems and methods to manage memory are provided. A particular method may include storing data in a primary memory that is in communication with a processor and storing in a mirrored data in a mirrored memory. The mirrored data may be compressed, and the mirrored memory may be in communication with the processor. A failure condition associated with the data of the primary memory may be detected. In response to the detected failure condition, the mirrored data in the mirrored memory may be accessed. | 05-17-2012 |
20120131248 | MANAGING COMPRESSED MEMORY USING TIERED INTERRUPTS - Systems and methods to manage memory are provided. A particular method may include initiating a memory compression operation. The method may further include initiating a first interrupt configured to affect a first process executing on a processor in response to a first detected memory level. A second initiated interrupt may be configured to affect the first process executing on the processor in response to a second detected memory level, and a third interrupt may be initiated to affect the first process executing on the processor in response to a third detected memory level. At least of the first, the second, and the third detected memory levels are affected by the memory compression operation. | 05-24-2012 |
20120131574 | Virtual machine data structures corresponding to nested virtualization levels - A system includes a processor providing hardware virtualization, and a memory to store a first virtual machine data structure corresponding to a first nested virtualization level and a second virtual machine data structure corresponding to a second nested virtualization level. The virtual machine data structures assist management of the hardware virtualization provided by the processor. The system includes a first nested virtual machine located within the first nested virtualization level and a second nested virtual machine located within the second nested virtualization level. The system includes hypervisors to manage the nested virtual machines using the virtual machine data structures. A root hypervisor is to manage the first nested virtual machine using the first virtual machine data structure. A first nested virtualization level hypervisor is to run within the first nested virtual machine and is to manage the second nested virtual machine using the second virtual machine data structure. | 05-24-2012 |
20120144146 | MEMORY MANAGEMENT USING BOTH FULL HARDWARE COMPRESSION AND HARDWARE-ASSISTED SOFTWARE COMPRESSION - Systems and methods to manage memory are provided. A particular method may include selecting one of a plurality of compression modes to perform memory compression operations at a server computer. The plurality of compression modes may include a first memory compression mode configured to perform a first memory compression operation using a compression engine, and a second compression mode configured to perform a second memory compression operation using the compression engine. At least one of the first compression operation and the second compression operation may be performed according to the selected compression mode. | 06-07-2012 |
20120173653 | VIRTUAL MACHINE MIGRATION IN FABRIC ATTACHED MEMORY - A computer program product and computer implemented method are provided for migrating a virtual machine between servers. The virtual machine is initially operated on a first server, wherein the first server accesses the virtual machine image over a network at a memory location within fabric attached memory. The virtual machine is migrated from the first server to a second server by flushing data to the virtual machine image from cache memory associated with the virtual machine on the first server and providing the state and memory location of the virtual machine to the second server. The virtual machine may then operate on the second server, wherein the second server accesses the virtual machine image over the network at the same memory location within the fabric attached memory without copying the virtual machine image. | 07-05-2012 |
20130010419 | REDUCING IMPACT OF REPAIR ACTIONS FOLLOWING A SWITCH FAILURE IN A SWITCH FABRIC - Techniques are disclosed for reducing impact of a switch failure and/or a repair action in a switch fabric. In one embodiment, a server system is provided that includes a first interposer card that operatively connects one or more server cards to a midplane. The first interposer card may include a switch module that switches network traffic for the one or more server cards. The first interposer card may be hot-swappable from the midplane, and the one or more server cards may be hot-swappable from the first interposer card. The server system may further include an interconnect between the first interposer card and a second interposer card. | 01-10-2013 |
20130010639 | SWITCH FABRIC MANAGEMENT - Techniques are disclosed for managing a switch fabric. In one embodiment, a server system is provided that includes a midplane, one or more server cards, switch modules and a management controller. The midplane may include a fabric interconnect for a switch fabric. The one or more server cards and the switch modules may be operatively connected to the midplane. The switch modules may be configured to switch network traffic for the one or more server cards. The management controller may be configured to manage the switch modules via the fabric interconnect. | 01-10-2013 |
20130013956 | REDUCING IMPACT OF A REPAIR ACTION IN A SWITCH FABRIC - Techniques are disclosed for reducing impact of a repair action in a switch fabric. In one embodiment, a server system is provided that includes a first interposer card that operatively connects one or more server cards to a midplane. The first interposer card may include a switch module that switches network traffic for the one or more server cards. The first interposer card may be hot-swappable from the midplane, and the one or more server cards may be hot-swappable from the first interposer card. | 01-10-2013 |
20130013957 | REDUCING IMPACT OF A SWITCH FAILURE IN A SWITCH FABRIC VIA SWITCH CARDS - Techniques are disclosed for reducing impact of a switch failure in a switch fabric. In one embodiment, a server system is provided that includes a midplane, one or more server cards and one or more switch cards. The midplane may include a fabric interconnect for a switch fabric. The one or more server cards may be coupled with the midplane, where each server card is hot-swappable from the midplane. The one or more switch cards may also be coupled with the midplane, where each switch card is also hot-swappable from the midplane. Each switch card includes one or more switch modules, and each switch module is configured to switch network traffic for at least one server card. | 01-10-2013 |
20130094348 | SWITCH FABRIC MANAGEMENT - Techniques are disclosed for managing a switch fabric. In one embodiment, a server system is provided that includes a midplane, one or more server cards, switch modules and a management controller. The midplane may include a fabric interconnect for a switch fabric. The one or more server cards and the switch modules may be operatively connected to the midplane. The switch modules may be configured to switch network traffic for the one or more server cards. The management controller may be configured to manage the switch modules via the fabric interconnect. | 04-18-2013 |
20130094351 | REDUCING IMPACT OF A SWITCH FAILURE IN A SWITCH FABRIC VIA SWITCH CARDS - Techniques are disclosed for reducing impact of a switch failure in a switch fabric. In one embodiment, a server system is provided that includes a midplane, one or more server cards and one or more switch cards. The midplane may include a fabric interconnect for a switch fabric. The one or more server cards may be coupled with the midplane, where each server card is hot-swappable from the midplane. The one or more switch cards may also be coupled with the midplane, where each switch card is also hot-swappable from the midplane. Each switch card includes one or more switch modules, and each switch module is configured to switch network traffic for at least one server card. | 04-18-2013 |
20130100799 | REDUCING IMPACT OF REPAIR ACTIONS FOLLOWING A SWITCH FAILURE IN A SWITCH FABRIC - Techniques are disclosed for reducing impact of a switch failure and/or a repair action in a switch fabric. In one embodiment, a server system is provided that includes a first interposer card that operatively connects one or more server cards to a midplane. The first interposer card may include a switch module that switches network traffic for the one or more server cards. The first interposer card may be hot-swappable from the midplane, and the one or more server cards may be hot-swappable from the first interposer card. The server system may further include an interconnect between the first interposer card and a second interposer card. | 04-25-2013 |
20130103329 | REDUCING IMPACT OF A REPAIR ACTION IN A SWITCH FABRIC - Techniques are disclosed for reducing impact of a repair action in a switch fabric. In one embodiment, a server system is provided that includes a first interposer card that operatively connects one or more server cards to a midplane. The first interposer card may include a switch module that switches network traffic for the one or more server cards. The first interposer card may be hot-swappable from the midplane, and the one or more server cards may be hot-swappable from the first interposer card. | 04-25-2013 |
20130254473 | IMPLEMENTING MEMORY INTERFACE WITH CONFIGURABLE BANDWIDTH - A method and system are provided for implementing enhanced memory performance management with configurable bandwidth versus power usage in a chip stack of memory chips. A chip stack of memory chips is connected in a predefined density to allow a predefined high bandwidth connection between each chip in the stack, such as with through silicon via (TSV) interconnections. Large-bandwidth data transfers are enabled from the memory chip stack by trading off increased power usage for memory performance on a temporary basis. | 09-26-2013 |
20140095769 | FLASH MEMORY DUAL IN-LINE MEMORY MODULE MANAGEMENT - Systems and methods to manage memory on a dual in-line memory module (DIMM) are provided. A particular method may include receiving at a flash application-specific integrated circuit (ASIC) a request from a processor to access data stored in a flash memory of a DIMM. The data may be transferred from the flash memory to a switch of the DIMM. The data may be routed to a dynamic random-access memory (DRAM) of the DIMM. The data may be stored in the DRAM and may be provided from the DRAM to the processor. | 04-03-2014 |
20140201314 | MIRRORING HIGH PERFORMANCE AND HIGH AVAILABLITY APPLICATIONS ACROSS SERVER COMPUTERS - Systems and methods to minor data and otherwise manage memory are provided. A buffer may be coupled to a processor and be configured to write a first copy of data to a first memory located at a first server computer and a second copy of the data to a second memory that is accessible to both the first server computer and a second server computer. The buffer may be coupled directly to at least one of the first memory and the second memory via a memory bus, copper cable, or an optical cable. The buffer may write the first and the second copies of the data concurrently. | 07-17-2014 |
20150023661 | OPTIMAL POSITIONING OF REFLECTING OPTICAL DEVICES - Reflecting optical devices are optimally positioned by an all optical switch in an optically-connected system by transmitting optical power readings taken from an optimal monitoring module that are transmitted to the all optical switch for optimal positioning of a reflecting optical device in order to produce maximum optical output power. | 01-22-2015 |
20150026432 | DYNAMIC FORMATION OF SYMMETRIC MULTI-PROCESSOR (SMP) DOMAINS - Symmetric multi-processor (SMP) nodes are dynamically configured via SMP sockets that use SMP optically-connected switches to dynamically connect SMP optically-connected links connected to the SMP nodes to form SMP domains based on best matched expected workloads for coherent traffic for exchanging SMP coherent information. The SMP nodes are dynamically added to one of the SMP domains and/or dynamically removed from one of the SMP domains. | 01-22-2015 |