Patent application number | Description | Published |
20100165712 | METHOD FOR LOW-STRESS MULTILEVEL READING OF PHASE CHANGE MEMORY CELLS AND MULTILEVEL PHASE CHANGE MEMORY - According to a method for multilevel reading of a phase change memory cell a bit line ( | 07-01-2010 |
20110080777 | Adaptive Wordline Programming Bias of a Phase Change Memory - The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell. | 04-07-2011 |
20110292721 | Adaptive Wordline Programming Bias of a Phase Change Memory - The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell. | 12-01-2011 |
20120268984 | Adaptive Wordline Programming Bias of a Phase Change Memory - The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell. | 10-25-2012 |
20120307553 | Circuitry for Reading Phase Change Memory Cells Having a Clamping Circuit - A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value. | 12-06-2012 |
Patent application number | Description | Published |
20090109738 | PHASE-CHANGE MEMORY DEVICE WITH ERROR CORRECTION CAPABILITY - A phase-change memory device includes a plurality of data PCM cells for storing data bits; data decoding circuits for selectively addressing sets of data PCM cells; and data read/program circuits for reading and programming the selected data PCM cells. The device further includes a plurality of parity PCM cells for storing parity bits associated with data bits stored in the data PCM cells; parity decoding circuits for selectively addressing sets of parity PCM cells; and parity read/program circuits for reading and programming the selected parity PCM cells. | 04-30-2009 |
20100128517 | PHASE-CHANGE MEMORY DEVICE WITH DISCHARGE OF LEAKAGE CURRENTS IN DESELECTED BITLINES AND METHOD FOR DISCHARGING LEAKAGE CURRENTS IN DESELECTED BITLINES OF A PHASE-CHANGE MEMORY DEVICE - A phase change memory device includes a bitline biasing unit; and a bitline selection unit connecting a selected bitline to the bitline biasing unit and disconnecting deselected bitlines from the bitline biasing unit in an operative condition. A bitline discharge unit is connected to the bitlines to discharge leakage currents in the bitlines. The bitline discharge unit has a voltage regulation unit and a plurality of bitline discharge switches coupled between the voltage regulation unit and a respective bitline. The bitline discharge switches are controlled to connect the deselected bitlines to the voltage regulation unit and to disconnect the selected bitline from the voltage regulation unit. The voltage regulation unit comprises a PMOS transistor coupled between a regulated voltage bus and a reference potential line. The regulated voltage bus is connected to the bitline discharge switches and the control terminal of the PMOS transistor is biased to a constant voltage. | 05-27-2010 |
20100141335 | CURRENT MIRROR CIRCUIT, IN PARTICULAR FOR A NON-VOLATILE MEMORY DEVICE - A current mirror circuit is provided with a first current mirror including a first and a second mirror transistors sharing a common control terminal; the first mirror transistor has a conduction terminal for receiving, during a first operating condition, a first reference current, and the second mirror transistor has a respective conduction terminal for providing, during the first operating condition, a mirrored current based on the first reference current. The current mirror circuit is provided with a switching stage operable to connect the control terminal to the conduction terminal of the first mirror transistor during the first operating condition, and to disconnect the control terminal from the same conduction terminal of the first mirror transistor, and either letting it substantially floating or connecting it to a reference voltage, during a second operating condition, in particular a condition of stand-by. | 06-10-2010 |
20100165714 | METHOD OF STORING AN INDICATION OF WHETHER A MEMORY LOCATION IN PHASE CHANGE MEMORY NEEDS PROGRAMMING - A phase change memory includes a float buffer which stores the result of a comparison between the current state of data in the phase change memory cells and an intended next state of each of those cells. The float buffer indicates which cells need to be programmed in order to achieve the new states and which cells happen to already be in the new states. Then, after programming of the cells, the float buffer indicates which cells still need to be programmed. Thus, a control stage uses the information in the float buffer to program only those cells whose states need to be changed. | 07-01-2010 |
20100284212 | METHOD FOR MULTILEVEL PROGRAMMING OF PHASE CHANGE CELLS USING ADAPTIVE RESET PULSES - A method for programming multilevel PCM cells envisages: forming an amorphous region of amorphous phase change material in a storage element of a PCM cell by applying one or more reset pulse; and forming a conductive path of crystalline phase change material through the amorphous region by applying one or more set pulse, a size of the conductive path defining a programmed state of the PCM cell and an output electrical quantity associated thereto, and being controlled by the value of the reset pulse and set pulse. The step of forming an amorphous region envisages adaptively and iteratively determining, during the programming operations, a value of the reset pulse optimized for electrical and/or physical properties of the PCM cell, and in particular determining a minimum amplitude value of the reset pulse, which allows programming a desired programmed state and a desired value of the output electrical quantity. | 11-11-2010 |
Patent application number | Description | Published |
20100165725 | RELIABLE SET OPERATION FOR PHASE-CHANGE MEMORY CELL - A Phase-Change Memory (PCM) device and a method of writing data to the PCM device are described. The PCM device includes a multi-phase data storage cell having at least a Set state and a Reset state that may be established using a heater configured to heat the data storage cell. A memory interface may be coupled with the heater configured to write data to the data storage cell, the data being represented by the Set or the Reset states. A write Reset pulse is used to place the data storage cell in the Reset state corresponding to a read value that is less than a read threshold. A write Set pulse that is a predetermined function of the write Reset pulse is used to place the data storage cell in the Set state. The PCM device may include additional intermediate states that enable each data storage cell to store two or more bits of information. Other embodiments may be described and claimed. | 07-01-2010 |
20120092923 | READ DISTRIBUTION MANAGEMENT FOR PHASE CHANGE MEMORY - Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory. | 04-19-2012 |
20120182783 | PROGRAMMING AN ARRAY OF RESISTANCE RANDOM ACCESS MEMORY CELLS USING UNIPOLAR PULSES - Subject matter disclosed herein relates to a memory device, and more particularly to programming a non-volatile memory device. | 07-19-2012 |
20130003450 | MIXED MODE PROGRAMMING FOR PHASE CHANGE MEMORY - Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory. | 01-03-2013 |
20130007564 | MEMORY DEVICE HAVING ADDRESS AND COMMAND SELECTABLE CAPABILITIES - Subject matter disclosed herein relates to memory management, and more particularly to partitioning a memory based on memory attributes. | 01-03-2013 |
20130010533 | DESCENDING SET VERIFY FOR PHASE CHANGE MEMORY - Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory. | 01-10-2013 |
20130227369 | ERROR DETECTION OR CORRECTION OF STORED SIGNALS AFTER ONE OR MORE HEAT EVENTS IN ONE OR MORE MEMORY DEVICES - Example embodiments described herein may relate to memory devices, and may relate more particularly to error detection or correction of stored signals in memory devices. | 08-29-2013 |
20130262743 | ENCODING PROGRAM BITS TO DECOUPLE ADJACENT WORDLINES IN A MEMORY DEVICE - Subject matter disclosed herein relates to memory operations regarding encoding program bits to be programmed into a memory array. | 10-03-2013 |
20130272063 | READ DISTRIBUTION MANAGEMENT FOR PHASE CHANGE MEMORY - Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory. | 10-17-2013 |
20130279238 | PROGRAMMING AN ARRAY OF RESISTANCE RANDOM ACCESS MEMORY CELLS USING UNIPOLAR PULSES - Subject matter disclosed herein relates to a memory device, and more particularly to programming a non-volatile memory device. | 10-24-2013 |
20130290604 | PROGRAM-DISTURB DECOUPLING FOR ADJACENT WORDLINES OF A MEMORY DEVICE - Subject matter disclosed herein relates to memory operations regarding programming bits into a memory array. | 10-31-2013 |
20130311837 | PROGRAM-DISTURB MANAGEMENT FOR PHASE CHANGE MEMORY - Subject matter disclosed herein relates to a memory device, and more particularly to read or write performance of a phase change memory. | 11-21-2013 |
Patent application number | Description | Published |
20100169740 | ACCELERATING PHASE CHANGE MEMORY WRITES - In a phase change memory, the memory array may be written in relatively small chunks. The writing of data to the array and, particularly, the writing of set data, may be accelerated using a hardware accelerator. The hardware accelerator may include an edge detector which detects a short duration signal pulse to trigger the writing of the set data to a cell. As a result, the writing of data may be accelerated, reducing the time to write in some cases. | 07-01-2010 |
20110113303 | METHOD AND APPARATUSES FOR CUSTOMIZABLE ERROR CORRECTION OF MEMORY - Described herein are a method and apparatuses for providing customizable error correction for memory arrays. In one embodiment, an apparatus includes a memory device having a memory array to store data and an analog to digital sense unit coupled to the memory array. The analog to digital sense unit senses analog signals associated with the memory array and converts the analog signals into distributions of digital values. An error-correcting code (ECC) unit receives the distributions of digital values from the analog to digital sense unit. A configurable non-volatile look-up table generates ECC parameters including error probability data and provides the ECC parameters to the ECC unit for error correction. The error probability data has error probability values that are associated with the distributions of digital values. The ECC unit executes an ECC algorithm to provide error correction using the error probability data. | 05-12-2011 |
20130003451 | REFRESH ARCHITECTURE AND ALGORITHM FOR NON-VOLATILE MEMORIES - Methods and systems to refresh a non-volatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level. | 01-03-2013 |
20130040584 | APPARATUS AND METHOD FOR READING A PHASE-CHANGE MEMORY CELL - An apparatus and a method for reading a phase-change memory cell are described. A circuit includes a current ramp circuit. A current forcing module is coupled with the current ramp circuit. A Veb emulation circuit is coupled with the current forcing module by a voltage adder, the voltage adder to sum an output from the Veb emulation circuit and a high impedance voltage source. A method includes forcing a current ramp into both a bitline and a dummy bitline, the dummy bitline having a voltage. The method also includes tripping a comparator when the current ramp provides a storage voltage with a predefined value, the storage voltage associated with the phase-change memory cell, and the predefined value independent from a resistance value of the phase-change memory cell and added in series to the voltage of the dummy bitline. | 02-14-2013 |
20130181183 | RESISTIVE MEMORY CELL STRUCTURES AND METHODS - Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material. | 07-18-2013 |
20130258768 | RELIABLE SET OPERATION FOR PHASE-CHANGE MEMORY CELL - A Phase-Change Memory (PCM) device and a method of writing data to the PCM device are described. The PCM device includes a multi-phase data storage cell having at least a Set state and a Reset state that may be established using a heater configured to heat the data storage cell. A memory interface may be coupled with the heater configured to write data to the data storage cell, the data being represented by the Set or the Reset states. A write Reset pulse is used to place the data storage cell in the Reset state corresponding to a read value that is less than a read threshold. A write Set pulse that is a predetermined function of the write Reset pulse is used to place the data storage cell in the Set state. The PCM device may include additional intermediate states that enable each data storage cell to store two or more bits of information. Other embodiments may be described and claimed. | 10-03-2013 |
20140036583 | PHASE CHANGE MEMORY DEVICE - A phase change memory device with memory cells ( | 02-06-2014 |
20140098603 | RELIABLE SET OPERATION FOR PHASE-CHANGE MEMORY CELL - A Phase-Change Memory (PCM) device and a method of writing data to the PCM device are described. The PCM device includes a multi-phase data storage cell having at least a Set state and a Reset state that may be established using a heater configured to heat the data storage cell. A memory interface may be coupled with the heater configured to write data to the data storage cell, the data being represented by the Set or the Reset states. A write Reset pulse is used to place the data storage cell in the Reset state corresponding to a read value that is less than a read threshold. A write Set pulse that is a predetermined function of the write Reset pulse is used to place the data storage cell in the Set state. The PCM device may include additional intermediate states that enable each data storage cell to store two or more bits of information. Other embodiments may be described and claimed. | 04-10-2014 |
20140269044 | METHODS AND APPARATUSES FOR CONTROLLING MEMORY WRITE SEQUENCES - Subject matter disclosed herein relates to memory operations regarding changing an order of program bits to be programmed into a memory array. | 09-18-2014 |
20140321191 | RESISTANCE VARIABLE MEMORY SENSING - The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include programming a memory cell to an initial data state and determining a data state of the memory cell by applying a programming signal to the memory cell, the programming signal associated with programming memory cells to a particular data state, and determining whether the data state of the memory cell changes from the initial data state to the particular data state during application of the programming signal. | 10-30-2014 |
20140321192 | RESISTANCE VARIABLE MEMORY SENSING - The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include circuitry to apply a programming signal to a memory cell in the array, the programming signal associated with programming resistance variable memory cells to a particular data state, and detect a change in resistance of the memory cell to determine if a data state of the memory cell changes from an initial data state to a different data state during application of the programming signal. | 10-30-2014 |
20140376306 | METHODS FOR A PHASE-CHANGE MEMORY ARRAY - Methods of operating phase-change memory arrays are described. A method includes determining a pattern to be written to a phase-change memory array and executing, according to the pattern, two or more proper reset sequences on the phase-change memory array to write the pattern to the phase-change memory array. Another method includes executing a set sequence on a phase-change memory array and performing a proper read of the phase-change memory array to obtain a pattern derived from executing the set sequence. | 12-25-2014 |