Patent application number | Description | Published |
20080232168 | LEVEL SHIFT CIRCUIT WHICH IMPROVED THE BLAKE DOWN VOLTAGE - A gate and the other end of the current path of first and second transistors are cross-connected. A third transistor is inserted to the other end of the current path of the first transistor, and a gate is supplied with a constant voltage, and further, one end of the current path and well are connected. A fourth transistor is inserted to the other end of the current path of the second transistor, and a gate is supplied with a constant voltage, and further, one end of the current path and well are connected. Fifth and sixth transistors are connected to the other end of the current path of the third and fourth transistors, and a gate is complementarily supplied with an input signal. Seventh and eighth transistors are connected to a back gate (well) of the third and fourth transistors, and a gate is complementarily supplied with an output signal. | 09-25-2008 |
20080232183 | SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell array, a word line, a source line, a row decoder, and a source line driver circuit. The memory cell array includes a memory cell unit having a plurality of memory cells connected in series. The word line is connected to control gates of the memory cells. The source line is electrically connected to sources of the memory cells positioned on one end sides of the memory cell unit. The row decoder selects the word line. The source line driver circuit is arranged in the row decoder and applies a first voltage to the source line. | 09-25-2008 |
20090027941 | SEMICONDUCTOR MEMORY DEVICE WITH POWER SUPPLY WIRING ON THE MOST UPPER LAYER - A memory cell array in a semiconductor substrate has a plurality of memory cells arranged in rows and columns. A first circuit is located at one end of the memory cell array in a column direction. A second circuit is located at the other end of the memory cell array in the column direction. A first wire is located above the memory cell array between the first circuit and the second circuit. The first wire is located in a most upper layer in the semiconductor substrate to supply power to the second circuit. | 01-29-2009 |
20090059670 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - There is provided a nonvolatile semiconductor memory device which can read and verify a cell with a negative threshold voltage by biasing voltages of a source line and well line to a positive voltage. The nonvolatile semiconductor memory device includes a voltage control circuit which applies a select gate voltage obtained by adding the biased positive voltage to a voltage set at read time of a cell with a positive threshold voltage to a select gate at a read time and verify time for the cell with the negative threshold voltage. | 03-05-2009 |
20090116292 | SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and a voltage generator. The memory cell unit includes a plurality of memory cells connected in series. Each of the memory cells includes a charge accumulation layer and a control gate. The word lines are connected to the control gate. The driver circuit selects one of the word lines and applies voltages to a selected word line and unselected word lines. The voltage generator includes first and second charge pump circuits and outputs a voltage generated by the first and second charge pump circuits to the driver circuit. The first charge pump circuit is exclusively used to generate a voltage for a first word line. The first word line is one of the unselected word lines located adjacent to the selected word line. | 05-07-2009 |
20090159949 | SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and a voltage generator. In the memory cell unit, memory cells having a charge accumulation layer and a control gate are connected in series. The word lines are connected to the control gates. The driver circuit selects the word lines. The voltage generator generates a first voltage and a second voltage lower than the first voltage. The first voltage is used by the first driver circuit to transfer a voltage to the unselected word line. The second voltage is used by circuits other than the first driver circuit. | 06-25-2009 |
20090168542 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device capable of reading and verifying a negative threshold cell by biasing a source line and a well line to a positive voltage. The nonvolatile semiconductor memory device includes a precharge circuit which precharges a bit line to the same voltage as that of the source line in reading and verifying the negative threshold cell. | 07-02-2009 |
20090273976 | SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes memory cells, a source line, a word line, a bit line, and a driver circuit. The memory cells are formed on a semiconductor layer and have a charge accumulation layer and a control gate on the charge accumulation layer. The word line is connected to gate of the memory cell. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to a source of the memory cell. The driver circuit varies potential of the semiconductor layer in conjunction with potential of the source line. | 11-05-2009 |
20100110799 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device capable of reading and verifying a negative threshold cell by biasing a source line and a well line to a positive voltage. The nonvolatile semiconductor memory device includes a precharge circuit which precharges a bit line to the same voltage as that of the source line in reading and verifying the negative threshold cell. | 05-06-2010 |
20100296345 | SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes memory cells, a source line, a word line, a bit line, and a driver circuit. The memory cells are formed on a semiconductor layer and have a charge accumulation layer and a control gate on the charge accumulation layer. The word line is connected to gate of the memory cell. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to a source of the memory cell. The driver circuit varies potential of the semiconductor layer in conjunction with potential of the source line. | 11-25-2010 |