Patent application number | Description | Published |
20080232158 | OPTIMIZED PHASE CHANGE WRITE METHOD - A method and system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC). The method and system includes an array of phase change elements with a plurality of devices providing independent control of a row access and a column access to the PCRAM. A column line (bit line) is pre-charged to a single predetermined level prior to enabling current flow to a corresponding selected phase change element. A current flow in the phase change element with a row (word line) is initiated once the column (bit line) has been pre-charged, to write data to the PCRAM cell. The current flow is terminated in the phase change element by closing the column line (bit line) preferably by quenching. | 09-25-2008 |
20090027943 | RESISTIVE MEMORY INCLUDING BIDIRECTIONAL WRITE OPERATION - A memory includes a first electrode, a second electrode, and a resistive memory element coupled between the first electrode and the second electrode. The memory includes a circuit configured to write a data value to the resistive memory element by sequentially applying a first signal from the first electrode to the second electrode and a second signal from the second electrode to the first electrode. | 01-29-2009 |
20090161416 | OPTIMIZED PHASE CHANGE WRITE METHOD - A system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC), and a design structure including the IC embodied in a machine readable medium are disclosed. The system includes an array of phase change elements with a plurality of devices providing independent control of a row access and a column access to the PCRAM. A column line (bit line) is pre-charged to a single predetermined level prior to enabling current flow to a corresponding selected phase change element. A current flow in the phase change element with a row (word line) is initiated once the column (bit line) has been pre-charged, to write data to the PCRAM cell. The current flow is terminated in the phase change element by closing the column line (bit line) preferably by quenching. | 06-25-2009 |
20100067285 | NOVEL SENSING CIRCUIT FOR PCRAM APPLICATIONS - A sensing method for a memory cell as described herein includes selecting a memory cell. A first bias applied to the memory cell induces a first response in the memory cell. A second bias applied to the memory cell induces a second response in the memory cell, the second bias different from the first bias. The method includes determining a data value stored in the memory cell based on a difference between the first and second responses and a predetermined reference. | 03-18-2010 |
20130292817 | STRUCTURE AND METHOD FOR MONITORING STRESS INDUCED FAILURES IN INTERLEVEL DIELECTRIC LAYERS OF SOLDER BUMP INTEGRATED CIRCUITS - A structure and method for monitoring interlevel dielectric stress damage. The structure includes a monitor solder bump and normal solder bumps; a set of stacked interlevel dielectric layers between the substrate and the monitor solder bump and the normal solder bumps, one or more ultra-low K dielectric layers comprising an ultra-low K material having a dielectric constant of 2.4 or less; a monitor structure in a region directly under the monitor solder bump in the ultra-low K dielectric layers and wherein the conductor density in at least one ultra-low K dielectric layer in the region directly under the monitor solder bumps is less than a specified minimum density and the conductor density in corresponding regions of the ultra-low K dielectric layers directly under normal solder bumps is greater than the specified minimum density. | 11-07-2013 |
Patent application number | Description | Published |
20090129195 | BALANCED AND BI-DIRECTIONAL BIT LINE PATHS FOR MEMORY ARRAYS WITH PROGRAMMABLE MEMORY CELLS - Disclosed is a design structure of an improved large scale memory system and, more particularly, an improved memory system that incorporates an array of memory cells that are subjected to minimal location dependent power variations and that, optionally, allows for bi-directional random access of millions of bits. Specifically, the system architecture provides a consistent amount of bit line resistance in the write and read paths to each memory cell in the array, independent of position, in order to minimize variations in power delivery to the cells and, thereby, allow for optimal cell distributions. The system architecture further allows current to pass in either direction through the cells in order to minimize element electro-migration and, thereby, extend memory cell life. | 05-21-2009 |
20090273968 | METHOD AND APPARATUS FOR IMPLEMENTING SELF-REFERENCING READ OPERATION FOR PCRAM DEVICES - A method of implementing a self-referencing read operation for a PCRAM array includes applying a stimulus to a bit line associated with a selected phase change element (PCE) to be read; comparing a first voltage on a node of the bit line with a second voltage on a delay node, wherein the second voltage represents a delayed voltage with respect to the first voltage due to a resistance/capacitance time constant associated therewith; and determining whether, during the read operation, the first voltage drops below the value of the second voltage; wherein in the event the first voltage drops below the value of the second voltage during the read operation, the PCE is determined to be programmed to an amorphous state and in the event the first voltage does not drop below the value of the second voltage, the PCE is determined to be programmed to a crystalline state. | 11-05-2009 |
20120057401 | PHASE CHANGE MEMORY CYCLE TIMER AND METHOD - A phase change memory (PCM) cycle timer and associated method are disclosed. A system includes at least one reference phase change element (PCE). The system also includes a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE throughout a settling time of the at least one reference PCE. | 03-08-2012 |
20120266115 | PHASE CHANGE MEMORY CYCLE TIMER AND METHOD - A phase change memory (PCM) cycle timer and associated method are disclosed. A system includes at least one reference phase change element (PCE). The system also includes a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE throughout a settling time of the at least one reference PCE. | 10-18-2012 |
20130099391 | CHAMFERED CORNER CRACKSTOP FOR AN INTEGRATED CIRCUIT CHIP - A corner crackstop is formed in each of the four corners of an integrated circuit (IC) chip, in which the corner crackstop differs structurally from a portion of the crackstop disposed along the sides of the IC chip. Each corner crackstop includes a plurality of layers, formed on a top surface of a silicon layer of the IC chip, within a perimeter boundary region that comprises a triangular area, in which a right angle is disposed on a bisector of the corner, equilateral sides of the triangle are parallel to sides of the IC chip, and the right angle is proximate to the corner relative to a hypotenuse of the triangle. The plurality of layers of the corner crackstop include crackstop elements, each comprising a metal cap centered over a via bar, in which the plurality of layers of the corner crackstop is chamfered to deflect crack ingress forces by each corner crackstop. | 04-25-2013 |
20140376149 | PHASE CHANGE MATERIAL VARIABLE CAPACITOR - A method of manufacturing a variable capacitor includes forming a capacitor conductor. The method also includes forming a phase change material adjacent the capacitor conductor. The method further includes forming a first contact on the capacitor conductor. The method additionally includes forming a second contact and a third contact on the phase change material. | 12-25-2014 |
20150091131 | POWER DISTRIBUTION FOR 3D SEMICONDUCTOR PACKAGE - A method including a printed circuit board electrically coupled to a bottom of a laminate substrate, the laminate substrate having an opening extending through the entire thickness of the laminate substrate, a main die electrically coupled to a top of the laminate substrate, a die stack electrically coupled to a bottom of the main die, the die stack including one or more chips stacked vertically and electrically coupled to one another, the die stack extending into the opening of the laminate substrate, and an interposer positioned between and electrically coupled to a topmost chip and the printed circuit board, the interposer providing an electrical path from the printed circuit board to the topmost chip of the die stack. | 04-02-2015 |
Patent application number | Description | Published |
20080229269 | DESIGN STRUCTURE FOR INTEGRATING NONVOLATILE MEMORY CAPABILITY WITHIN SRAM DEVICES - A design structure embodied in a machine readable medium used in a design process includes a nonvolatile static random access memory (SRAM) device, including a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data; and a pair of magnetic spin transfer devices coupled to opposing sides of the storage cell; wherein the magnetic spin transfer devices are configured to retain the storage cell data therein following removal of power to the SRAM device, and are further configured to initialize the storage cell with the retained data upon application of power to the SRAM device. | 09-18-2008 |
20090086534 | APPARATUS AND METHOD FOR IMPLEMENTING PRECISE SENSING OF PCRAM DEVICES - A precision sense amplifier apparatus includes a current source configured to introduce an adjustable reference current through a reference leg; a current mirror configured to mirror the reference current to a data leg, the data leg selectively coupled to a programmable resistance memory element; an active clamping device coupled to the data leg, and configured to clamp a fixed voltage across the memory element, thereby establishing a fixed current sinking capability thereof; and a differential sense amplifier having a first input thereof coupled to the data leg and a second input thereof coupled to the reference leg; wherein an output of the differential sense amplifier assumes a first logic state whenever the reference current is less than the fixed current sinking capability of the memory element, and assumes a second logic state whenever the reference current exceeds the fixed current sinking capability. | 04-02-2009 |
20090282375 | Circuit And Method Using Distributed Phase Change Elements For Across-Chip Temperature Profiling - Disclosed is an across-chip temperature sensing circuit and an associated method that can be used to profile the across-chip temperature gradient. The embodiments incorporate a plurality of phase change elements distributed approximately evenly across the semiconductor chip. These phase change elements are programmed to have essentially the same amorphous resistance. Temperature-dependent behavior exhibited by each of the phase change elements individually is compared to a reference (e.g., generated by a discrete reference phase change element, generated by another one of the phase change elements, or generated by an external reference) in order to profile the temperature gradient across the semiconductor chip. Once profiled, this temperature gradient can be used to redesign and/or relocate functional cores, to set stress limits for qualification of functional cores and/or to adjust operating specifications of functional cores. | 11-12-2009 |
20100174503 | Monitoring NFET/PFET Skew in Complementary Metal Oxide Semiconductor Devices - An apparatus for directly measuring performance offset of NFET transistors with respect to PFET transistors in CMOS device processing includes a ring oscillator whose frequency is used to measure random across chip variations, as well as correlated across chip variations; a balanced inverter having a input driven by the ring oscillator, wherein the balanced inverter is designed to be formed such that a current drive capability of one or more NFET devices of the inverter is substantially equal to a current drive capability of one or more PFET devices of the inverter at a given operating temperature; and a capacitor coupled to an output of the inverter, with a voltage across the capacitor indicative of whether a skew exists between NFET device performance and PFET device performance. | 07-08-2010 |
20110116312 | NON VOLATILE CELL AND ARCHITECTURE WITH SINGLE BIT RANDOM ACCESS READ, PROGRAM AND ERASE - One embodiment is a non-volatile memory cell with random access read, program, and erase. The memory cell includes a cell transistor that includes a source region, a drain region, a first insulating spacer, and a second insulating spacer. The memory cell also includes a source-side transistor, a drain-side transistor, a source-side multiplexer, a drain-side multiplexer, a source-side sense amplifier, and a drain-side write driver. A first binary value is stored in a first bit in the memory cell by trapping or releasing a first electric charge in the first insulating spacer. The first bit is read by sensing the resistive change in the cell transistor or by sensing the threshold voltage change in the cell transistor. | 05-19-2011 |
20120074559 | INTEGRATED CIRCUIT PACKAGE USING THROUGH SUBSTRATE VIAS TO GROUND LID - An integrated circuit package including a package substrate, a metal lid mounted to the package substrate, and a stack of two or more integrated circuit chips electrically connected to each other by through substrate vias. The stack of two or more integrated circuit chips is disposed within the metal lid and electrically mounted to the package substrate. An inner surface of a top of the metal lid is electrically connected to ground wires in the package substrate by the through substrate vias. The TSVs provide electromagnetic interference shielding. A conductive thermal interface material may also be used. An alternative embodiment includes a single integrated circuit chip using TSVs to ground the metal lid. | 03-29-2012 |
20120187953 | CIRCUIT FOR DETECTING STRUCTURAL DEFECTS IN AN INTEGRATED CIRCUIT CHIP, METHODS OF USE AND MANUFACTURE AND DESIGN STRUCTURES - Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit. | 07-26-2012 |
20120318648 | NORMALLY CLOSED MICROELECTROMECHANICAL SWITCHES (MEMS), METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Normally closed (shut) micro-electro-mechanical switches (MEMS), methods of manufacture and design structures are provided. A method of forming a micro-electrical-mechanical structure (MEMS), includes forming a plurality of electrodes on a substrate, forming a beam structure in electrical contact with a first of the electrodes, and bending the beam structure with a thermal process. The method further includes forming a cantilevered electrode extending over an end of the bent beam structure, and returning the beam structure to its original position, which will contact the cantilevered electrode in a normally closed position. | 12-20-2012 |
20140021622 | OPTIMIZATION METALLIZATION FOR PREVENTION OF DIELECTRIC CRACKING UNDER CONTROLLED COLLAPSE CHIP CONNECTIONS - A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads. | 01-23-2014 |
20140033148 | ELASTIC MODULUS MAPPING OF A CHIP CARRIER IN A FLIP CHIP PACKAGE - A computer-implemented method provides an elastic modulus map of a chip carrier of a flip chip package. Design data including dielectric and conductive design elements of each of vertically aligned sub-areas of each of the layers of the chip carrier are modeled as springs to provide the elastic modulus map. Determining the elastic modulus of the sub-areas of the chip carrier identifies probable mechanical failure sites during chip-join and cools down of the flip chip package. Modifying a footprint of solder bumps to the chip carrier reduces stresses applied to the identified probable mechanical failure sites. Modifying the chip carrier design to reduce a stiffness of sub-areas associated with identified probable mechanical failure sites also reduces stresses from chip-join and cool-down. | 01-30-2014 |
20140070340 | NORMALLY CLOSED MICROELECTROMECHANICAL SWITCHES (MEMS), METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Normally closed (shut) micro-electro-mechanical switches (MEMS), methods of manufacture and design structures are provided. A structure includes a beam structure that includes a first end hinged on a first electrode and in electrical contact with a second electrode, in its natural state when not actuated. | 03-13-2014 |
20150044787 | SEMICONDUCTOR TEST AND MONITORING STRUCTURE TO DETECT BOUNDARIES OF SAFE EFFECTIVE MODULUS - A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package. | 02-12-2015 |
Patent application number | Description | Published |
20080225590 | APPARATUS AND METHOD FOR INTEGRATING NONVOLATILE MEMORY CAPABILITY WITHIN SRAM DEVICES - A nonvolatile static random access memory (SRAM) device includes a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data and a pair of magnetic spin transfer devices coupled to opposing sides of the storage cell. The magnetic spin transfer devices are configured to retain the storage cell data therein following removal of power to the SRAM device, and are further configured to initialize the storage cell with the retained data upon application of power to the SRAM device. | 09-18-2008 |
20080247216 | METHOD AND APPARATUS FOR IMPLEMENTING IMPROVED WRITE PERFORMANCE FOR PCRAM DEVICES - A method of implementing a write operation for a programmable resistive random access memory array includes coupling a current source to a bit line associated with a programmable resistive memory element; prior to activating a word line associated with the memory element, precharging the bit line by passing current the bit line and through a dummy path selectively coupled to the bit line; and upon achieving a desired operating point of bit line current and bit line voltage, decoupling the dummy path from the bit line and activating the word line associated with the memory element so as to cause current from the bit line to flow for a period of time selected to program the memory element to one of a low resistance state and a high resistance state. | 10-09-2008 |
20080247218 | DESIGN STRUCTURE FOR IMPLEMENTING IMPROVED WRITE PERFORMANCE FOR PCRAM DEVICES - A design structure embodied in a machine readable medium used in a design process includes a circuit for implementing a write operation for a programmable resistive random access memory array, the circuit including a current source coupled to a bit line associated with a programmable resistive memory element; a dummy path configured for selective coupling to the bit line prior to activation of a word line associated with the memory element, wherein the passage of current through the bit line and dummy path precharges the bit line; and control circuitry for decoupling the dummy path from the bit line and for activating the word line associated with the memory element upon achieving a desired operating point of bit line current and bit line voltage, so as to cause current from the bit line to flow for a period of time selected to program the memory element to one of a low resistance state and a high resistance state. | 10-09-2008 |
20090109735 | DESIGN STRUCTURE FOR INITIALIZING REFERENCE CELLS OF A TOGGLE SWITCHED MRAM DEVICE - A design structure embodied in a machine readable medium used in a design process includes an apparatus for initializing a reference cell in a toggle switched MRAM device, with a first sense amplifier configured for performing a first read operation of the reference cell by comparing current through the reference cell with the average current passing through a pair of data cells; a first latch for storing the result of the first read operation; a second latch for storing the result of a second read operation by the first sense amplifier, wherein the second read operation is performed following the first read operation and the inversion of the value of one of the pair of the data cells; a third latch for storing the result of a third read operation by the first sense amplifier, wherein the third read operation is performed following the second read operation and the inversion of the value of the other of the pair of the data cells; and a majority compare device configured to compare of the results of the first, second and third operations respectively stored in the first, second and third latches, wherein an output of the majority compare operation is the initial state of the reference cell. | 04-30-2009 |
20090219749 | METHOD AND APPARATUS FOR IMPLEMENTING CONCURRENT MULTIPLE LEVEL SENSING OPERATION FOR RESISTIVE MEMORY DEVICES - An apparatus for sensing the data state of a multiple level, programmable resistive memory device includes an active clamping device connected to a data leg that is selectively coupled a programmable resistive memory element, the clamping device configured to clamp a fixed voltage, at a first node of the data leg, across the memory element, thereby establishing a fixed current sinking capability thereof; and a plurality of differential amplifiers, each of the differential amplifiers configured to compare a first voltage input, taken at a second node of the data leg, with a second voltage input; wherein the second voltage input for each differential amplifier comprises different reference voltages with respect to one another so as to enable each differential amplifier to detect a different resistance threshold, thereby determining a specific resistance state of the programmable resistive memory element. | 09-03-2009 |
20130285251 | ELONGATED VIA STRUCTURES - An integrated circuit structure comprises a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface. | 10-31-2013 |
20140021616 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure. | 01-23-2014 |
20140024146 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure. | 01-23-2014 |