Patent application number | Description | Published |
20080230935 | Methods for producing a pitch foam - Methods to produce a pitch foam from a hydrocarbon carbonaceous precursor material. A gaseous blowing material is dissolved in the carbonaceous precursor material, and the resultant solution is pressurized in a vessel. As the solution is exhausted from the vessel, the gaseous blowing agent and the hydrocarbons of the carbonaceous precursor material evaporate from the pressurized solution to form a foam-like solution. The pitch foam is formed from the foam-like solution by directing the foam-like solution onto a surface, whereupon, the foam-like solution solidifies into the pitch foam. | 09-25-2008 |
20120082593 | Coal Liquefaction System - The present disclosure relates to a coal liquefaction system for utilizing a hydrogenated vegetable oil to liquefy coal. The system includes a reactor for exposing a coal to a hydrogenated vegetable oil in the presence of a coal-derived solvent to form a slurry, a heater that elevates the temperature of the slurry in the reactor to facilitate liquefying the coal and liberating a volatile matter, and a centrifuge that separates the insoluble components from the slurry to obtain a de-ashed coal extract, wherein the coal extract is suitable for downstream processing. The system may also include a distillation column that distills the de-ashed coal extract to obtain a pitch. The system may also include a coker that cokes at least one of the de-ashed coal extract and the pitch to obtain a coke | 04-05-2012 |
20120091042 | Hydrogenated Vegetable Oil in Coal Liquefaction - The present disclosure provides methods and systems for coal liquefaction using a hydrogenated vegetable oil. A method of obtaining a de-ashed coal extract includes exposing a coal to a hydrogenated vegetable oil in the presence of a coal-derived solvent to form a slurry, elevating the temperature of the slurry to facilitate liquefying the coal and liberating a volatile matter, and separating the insoluble components from the slurry to obtain a de-ashed coal extract, wherein the coal extract is suitable for downstream processing. | 04-19-2012 |
20120160744 | Method of Producing Synthetic Pitch - Embodiments of a method are described for modifying pitches, oils, tars, and binders by using these materials as solvents to extract organic chemicals from coal. | 06-28-2012 |
Patent application number | Description | Published |
20090323759 | Temperature measurement with reduced extraneous infrared in a processing chamber - Temperature measurement using a pyrometer in a processing chamber is described. The extraneous light received by the pyrometer is reduced. In one example, a photodetector is used to measure the intensity of light within the processing chamber at a defined wavelength. A temperature circuit is used to convert the measured light intensity to a temperature signal, and a doped optical window between a heat source and a workpiece inside processing chamber is used to absorb light at the defined wavelength directed at the workpiece from the heat source. | 12-31-2009 |
20090325392 | SUB-SECOND ANNEALING PROCESSES FOR SEMICONDUCTOR DEVICES - An annealing method and apparatus for semiconductor manufacturing is described. The method and apparatus allows an anneal that can span a thermal budget and be tailored to a specific process and its corresponding activation energy. In some cases, the annealing method spans a timeframe from about 1 millisecond to about 1 second. An example for this annealing method includes a sub-second anneal method where a reduction in the formation of nickel pipes is achieved during salicide processing. In some cases, the method and apparatus combine the rapid heating rate of a sub-second anneal with a thermally conductive substrate to provide quick cooling for a silicon wafer. Thus, the thermal budget of the sub-second anneal methods may span the range from conventional RTP anneals to flash annealing processes (including duration of the anneal, as well as peak temperature). Other embodiments are described. | 12-31-2009 |
20130285129 | PULSED LASER ANNEAL PROCESS FOR TRANSISTORS WITH PARTIAL MELT OF A RAISED SOURCE-DRAIN - A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth. | 10-31-2013 |
20130288438 | SELECTIVE LASER ANNEALING PROCESS FOR BURIED REGIONS IN A MOS DEVICE - Laser anneal to melt regions of a microelectronic device buried under overlying materials, such as an interlayer dielectric (ILD). Melting temperature differentiation is employed to selectively melt a buried region. In embodiments a buried region is at least one of a gate electrode and a source/drain region. Laser anneal may be performed after contact formation with contact metal coupling energy into the buried layer for the anneal. | 10-31-2013 |
20150200301 | PULSED LASER ANNEAL PROCESS FOR TRANSISTORS WITH PARTIAL MELT OF A RAISED SOURCE-DRAIN - A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth. | 07-16-2015 |
Patent application number | Description | Published |
20130154016 | TIN DOPED III-V MATERIAL CONTACTS - Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstained channel structures. | 06-20-2013 |
20130267084 | METHOD FOR FORMING SUPERACTIVE DEACTIVATION-RESISTANT JUNCTION WITH LASER ANNEAL AND MULTIPLE IMPLANTS - A pulsed-laser anneal technique includes performing an implant of a selected region of a semiconductor wafer. A co-constituent implant of the selected region is performed, and the pulsed-laser anneal of the selected region performed. A pre-amorphizing implant of the selected region can also be performed. In one embodiment, the implant of the selected region is performed as an insitu implant. In another embodiment, the co-constituent implant is performed as an insitu non-donor implant. In yet another embodiment, the implant and the co-constituent implant of the selected region are performed as an insitu donor and co-constituent implant. | 10-10-2013 |
20130285017 | STRAINED CHANNEL REGION TRANSISTORS EMPLOYING SOURCE AND DRAIN STRESSORS AND SYSTEMS INCLUDING THE SAME - Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor. In embodiments of the invention, the transistor channel regions are comprised of germanium, silicon, a combination of germanium and silicon, or a combination of germanium, silicon, and tin and the source and drain regions are comprised of a doped III-V compound semiconductor material. Embodiments of the invention are useful in a variety of transistor structures, such as, for example, trigate, bigate, and single gate transistors and transistors having a channel region comprised of nanowires or nanoribbons. | 10-31-2013 |
20150054031 | TIN DOPED III-V MATERIAL CONTACTS - Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstrained channel structures. | 02-26-2015 |