Patent application number | Description | Published |
20090323511 | Combined OFDMA Preamble Index Identification, Integer Frequency Offset Estimation, and Preamble CINR Measurement - A wireless signal processor for use in identifying a maximum Carrier to Noise Interference Ratio (CINR) associated with a plurality of received OFDMA subcarriers has a candidate generator for forming a plurality of candidate values from a particular set of received subcarriers by forming candidate values based on the received subcarriers in combination with possible integer preamble offsets and possible preamble values. A candidate evaluator selects which of the possible preamble values and integer frequency offset values have the maximum CINR, and provides the maximum CINR with IFO and preamble index as outputs. | 12-31-2009 |
20090323512 | Combined OFDMA Preamble Index Identification, Integer Frequency Offset Estimation, and Preamble CINR Measurement - A wireless signal processor for use in identifying a maximum Carrier to Noise Interference Ratio (CINR) associated with a plurality of received OFDMA subcarriers has a candidate generator for forming a plurality of candidate values from a particular set of received subcarriers by forming candidate values based on the received subcarriers in combination with possible integer preamble offsets and possible preamble values. A candidate evaluator selects which of the possible preamble values and integer frequency offset values have the maximum CINR, and provides the maximum CINR with IFO and preamble index as outputs. | 12-31-2009 |
20100027693 | Stream Weight Estimation and Compensation in SIMO/MIMO OFDM Receivers - A process for equalizing streams of OFDM subcarrier data computes the noise variance for each stream, and forms a stream weighting coefficient by equalizing the noise variance, such that for a first stream having a noise variance σ | 02-04-2010 |
20100027702 | Stream Weight Estimation and Compensation in SIMO/MIMO OFDM Receivers - A process for equalizing streams of OFDM subcarrier data computes the noise variance for each stream, and forms a stream weighting coefficient by equalizing the noise variance, such that for a first stream having a noise variance σ | 02-04-2010 |
20100046645 | Interpolation IIR filter for OFDM Baseband Processing - A filter for receiver and operative on a stream of OFDM symbols has a symbol timing identifier which indicates the time interval for each symbol and also indicates a non-truncation interval and a truncation interval of the stream of symbols. The stream of OFDM symbols is applied to an infinite impulse response (IIR) filter with a reset input for resetting internal registers such that during the non-truncation interval, the reset input is not asserted, and during the truncation interval of the stream of OFDM symbols, the reset input is asserted during the intervals between symbols, as identified by the symbol timing identifier. | 02-25-2010 |
20100046646 | Interpolation IIR filter for OFDM Baseband Processing - A filter for receiver and operative on a stream of OFDM symbols has a symbol timing identifier which indicates the time interval for each symbol and also indicates a non-truncation interval and a truncation interval of the stream of symbols. The stream of OFDM symbols is applied to an infinite impulse response (IIR) filter with a reset input for resetting internal registers such that during the non-truncation interval, the reset input is not asserted, and during the truncation interval of the stream of OFDM symbols, the reset input is asserted during the intervals between symbols, as identified by the symbol timing identifier. | 02-25-2010 |
20100046647 | Interpolation IIR filter for OFDM Baseband Processing - A filter for receiver and operative on a stream of OFDM symbols has a symbol timing identifier which indicates the time interval for each symbol and also indicates a non-truncation interval and a truncation interval of the stream of symbols. The stream of OFDM symbols is applied to an infinite impulse response (IIR) filter with a reset input for resetting internal registers such that during the non-truncation interval, the reset input is not asserted, and during the truncation interval of the stream of OFDM symbols, the reset input is asserted during the intervals between symbols, as identified by the symbol timing identifier. | 02-25-2010 |
20100046648 | Interpolation IIR filter for OFDM Baseband Processing - A filter for receiver and operative on a stream of OFDM symbols has a symbol timing identifier which indicates the time interval for each symbol and also indicates a non-truncation interval and a truncation interval of the stream of symbols. The stream of OFDM symbols is applied to an infinite impulse response (IIR) filter with a reset input for resetting internal registers such that during the non-truncation interval, the reset input is not asserted, and during the truncation interval of the stream of OFDM symbols, the reset input is asserted during the intervals between symbols, as identified by the symbol timing identifier. | 02-25-2010 |
20100067623 | Method for setting Inter-Packet Gain - An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required. | 03-18-2010 |
20100067624 | Process for Packet Detection - An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required. | 03-18-2010 |
20100067625 | Level Sensitive Packet Detector - An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required. | 03-18-2010 |
20100067626 | Packet Acquisition Processor - An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required. | 03-18-2010 |
20100109796 | Multi-Band Transmit-Receive Switch for Wireless Transceiver - A transmit-receive switch has a transmit port, an antenna port, and a receive port. A first switch couples the transmit port to the antenna port when a signal TxON is asserted. A LOW_BAND signal indicates the selection of a lower band of frequencies. A tuning structure is formed by a second and third switch in series which couple the antenna port to ground through a first capacitor when TxON and LOW_BAND are both asserted, and LOW_BAND may be provided to one or more such tuning structures for multi-band frequency operation. A second capacitor couples the antenna port to ground when a fourth switch is enabled. An inductor couples the antenna port to the receive port. A third capacitor is placed across the receive port and ground. A fifth switch is closed when TxON is asserted. The first through fifth switches can be a CMOS FET with an isolated substrate coupled to ground through an associated resistor. | 05-06-2010 |
20100131577 | Programmable CORDIC Processor - A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input. | 05-27-2010 |
20100138631 | Process for QR Transformation using a CORDIC Processor - A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input. | 06-03-2010 |
20100138632 | Programmable CORDIC Processor with Stage Re-Use - A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input. | 06-03-2010 |
20100202504 | Channel Estimation Filter for OFDM receiver - A channel smoothing filter with a finite impulse response (FIR) has a controller which reads parallel sample data out of an FFT memory in such a manner as to generate an even function, the sample data applied to a preamble equalizer accompanied by a preamble sign and zero, the preamble outputs coupled to three filter processors, each filter processor having four filter engines whose outputs are summed, the channel smoothing filter generating an a register output, the register input coupled to a summer which has as inputs: the first filter processor shifted by four, the second filter processor shifted by two, the third filter processor, and the register output. Coefficients for an edge filter and a central filter are provided in Zero Sign Shift (ZSS) format, and by selection of coefficients using a canonical signed digit (CSD) algorithm, no multipliers are required for the channel smoothing FIR filter. | 08-12-2010 |