Wu, Hsinchu City
Bo-Chen Wu, Hsinchu City TW
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20080204249 | Radio frequency identification systems for electronic devices - A system comprises an electronic device for providing a particular electronic function, an radio frequency identification (RFID) tag connecting to an antenna, and an interface for connecting the primary module and the RFID tag. The RFID tag is capable of having wireless communicating through the antenna. The electronic device and the RFID tag are capable of communicating with each other through the interface. | 08-28-2008 |
20090218398 | RFID ACCES APPARATUS AND TRANSACTION METHOD USING THE SAME - The present invention discloses a RFID access apparatus and a transaction method using the same. The RFID access apparatus, coupled to a SD card socket disposed in an electrical terminal device including a controller unit coupled to said SD card socket and a radio frequency transceiver coupled to the controller unit, and being capable of accessing data recorded in a RFID tag through operating the electrical terminal device. | 09-03-2009 |
Bone-Fong Wu, Hsinchu City TW
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20100009506 | DOPANT IMPLANTATION METHOD AND INTEGRATED CIRCUITS FORMED THEREBY - A method of forming a dopant implant region in a MOS transistor device having a dopant profile having a target dopant concentration includes implanting a first concentration of dopants into a region of a substrate, where the first concentration of dopants is less than the target dopant concentration, and without annealing the substrate after the implanting step, performing at least one second implanting step to implant at least one second concentration of dopants into the region of the substrate to bring the dopant concentration in the region to the target dopant concentration. | 01-14-2010 |
Bor-Chun Wu, Hsinchu City TW
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20110102416 | Gate Driving Circuit and Related LCD Device - A gate driving circuit for an LCD device includes a shift register module for generating a plurality of scan signals corresponding to a plurality of channels according to a start signal and a clock signal, a plurality of logic circuits each corresponding to a channel of the plurality of channels, for outputting a driving signal to the channel according to a scan signal of the plurality of scan signals and a shutdown indication signal, and a plurality of shaping and delay units each coupled between two neighboring channels for outputting the shutdown indication signal to another channel after shaping and delaying the shutdown indication signal of a previous stage. | 05-05-2011 |
Bo-Shian Wu, Hsinchu City TW
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20110183454 | Method for preparing OLED by imprinting process - A method for preparing an OLED by an imprinting process is disclosed, which comprises the following steps: (A) providing a substrate, and a first electrode is formed thereon; (B) coating a mold with a first organic material ink; (C) pressing the mold coated with the first organic material ink on the substrate to transfer the first organic material ink onto the first electrode of the substrate, to obtain a first light-emitting array; (D) baking the substrate having the first light-emitting array formed thereon; and (E) forming a second electrode on the first light-emitting array. | 07-28-2011 |
C. C. Wu, Hsinchu City TW
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20080299723 | METHODS FOR FORMING CAPACITOR STRUCTURES - A method for forming a capacitor includes forming a dielectric layer over a substrate. A conductive layer is formed over the dielectric layer. Dopants are implanted through at least one of the dielectric layer and the conductive layer after forming the dielectric layer so as to form a conductive region under the dielectric layer, wherein the conductive layer is a top electrode of the capacitor and the conductive region is a bottom electrode of the capacitor. | 12-04-2008 |
Chang-Long Wu, Hsinchu City TW
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20090323507 | APPARATUS AND METHOD FOR CONVERTING GROOVE/LAND POLARITY UPON GROOVE/LAND TRACK CHANGE ON OPTICAL MEDIUM - The present invention discloses an apparatus for converting a groove/land polarity on an optical medium, which comprises a physical identification (PID) detector detecting a first sector into a first PID value, a sector information unit providing an information including a second PID value indicative of either a second sector or at least one reference groove/land changing point, a sector counter counting a first value whose an initiation is set by the sector information unit based on the information and/or the PID detector based on the first PID value, and a comparing unit determining at least one oncoming groove/land changing points, based on when the first value approaches a second value either predetermined in or generated by the sector information unit according to said information. | 12-31-2009 |
20110167323 | Error-Correcting Apparatus and Method Thereof - The invention discloses an error-correcting apparatus for decoding an input signal by using a Viterbi algorithm to generate a Viterbi-decoded signal, including an erasure unit and a decoder. The erasure unit is configured to generate at least one logic signal according to at least one path metric difference of path metrics in the Viterbi algorithm, and generate erasure information, wherein the erasure information indicates data reliability of at least one location of the Viterbi-decoded signal. The decoder is configured to decode the Viterbi-decoded signal according to the erasure information. | 07-07-2011 |
Cheng-Hua Wu, Hsinchu City TW
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20110139076 | INTELLIGENT PET-FEEDING DEVICE - An intelligent pet-feeding device is disclosed, which comprises: a frame, configured with at least one opening; a storage tank, for storing at least one kind of food while enabling each kind of food to be transported out of the frame from it corresponding opening; a communication module, capable of performing a wireless communication with an operator at a remote end; an imaging module, for capturing images and thus generating image signals accordingly; an audio transceiver module, for receiving and transmitting audio signals; and a central processing unit, electrically connected to the communication module, the imaging module and the audio transceiver module for processing signals received thereby and generated therefrom. | 06-16-2011 |
20130142395 | DISTANCE MEASUREMENT APPARATUS AND METHOD - A distance measurement apparatus and a distance measurement method are provided. The apparatus includes a line-shaped laser transmitter, an image sensing device and a processing unit. The line-shaped laser transmitter transmits a line-shaped laser, and the image sensing device senses the line-shaped laser to output a line-shaped laser image. The processing unit receives the line-shaped laser image, and segments the line-shaped laser image into several sub-line-shaped laser images. The processing unit further calculates a vertical position for a laser line in each sub-line-shaped laser image, and outputs each distance information according to the corresponding sub-line-shaped laser image and a transformation relation. | 06-06-2013 |
20130158773 | SYSTEM AND METHOD FOR GUIDING AUTOMATED GUIDED VEHICLE - A system for guiding an automated guided vehicle (AGV) is provided. The system includes a guidance path, an AGV, an image capturing apparatus and an operation unit. The guidance path guides the AGV. The AGV moves on the guidance path and is guided by the guidance path. The AGV moves in a vision guidance region after departing from the guidance path. The image capturing apparatus captures a vision guidance region associated image. The vision guidance region associated image at least includes an image of the vision guidance region. The operation unit determines whether the AGV departs from the guidance path, and calculates position information of the AGV in the vision guidance region. When the AGV departs from the guidance path, the operation unit guides the AGV according to the vision guidance region associated image. | 06-20-2013 |
Cheng-San Wu, Hsinchu City TW
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20100233437 | LITHOGRAPHIC MACHINE PLATFORM AND APPLICATIONS THEREOF - A lithographic machine platform and applications thereof is disclosed. The lithographic machine platform comprises: an electron beam or an ion beam generator generating an electron beam or an ion beam; a substrate supporting platform supporting a substrate; and a precursory gas injector injecting a precursory gas above the substrate. The present invention uses the electron beam or the ion beam to induce the precursory gas to react with the electron beam or the ion beam, and then the precursory gas is deposited on the substrate. The present invention not only fabricates a patterned layer on the substrate in a single step but also achieves a high lithographic resolution and avoids remains of contaminations by using the properties of the electron beam or the ion beam and the precursory gas. | 09-16-2010 |
Chia-Mu Wu, Hsinchu City TW
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20110122088 | PASSIVE ARCHITECTURE AND CONTROL METHOD FOR SCANNING A TOUCH PANEL - A passive architecture for scanning a touch panel includes a master IC and at least one passive touch IC connected to the master IC. The master IC generates a command to configure the scan parameters of the at least one passive touch IC, and the at least one passive touch IC scans the touch panel with the scan parameters in response to the command. | 05-26-2011 |
20130257767 | HIGH NOISE IMMUNITY SENSING METHODS AND APPARATUS FOR A CAPACITIVE TOUGH DEVICE - High noise immunity sensing methods and apparatus are provided for a capacitive touch device, which sense the capacitive touch device for self capacitance or mutual capacitance or both with different scan frequencies in a frame, to thereby suppress certain frequency noise interference. By combining time domain and space domain noise-eliminating approaches, probabilities of noise interference are reduced, without compromising other parameters. | 10-03-2013 |
20130257797 | HIGH NOISE IMMUNITY SENSING METHODS AND APPARATUS FOR A CAPACITIVE TOUCH DEVICE - A sensing method and a sensing apparatus for a capacitive touch device sense variations of self capacitances of first traces in a first direction and second traces in a second direction and variations of mutual capacitances of intersections between the first traces and the second traces, and then generates fourth sensed values from the first, second and third sensed values to serve as sensed values of the changes of the mutual capacitances of the intersections between the first traces and the second traces for identifying one or more touch points. Therefore, noise interference is suppressed and real touch points can be easily to be identified. | 10-03-2013 |
Chia-Yeh Wu, Hsinchu City TW
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20090021957 | Table lamp structure - The present invention discloses an improved table lamp, which comprises: a lamp base, an arm and a lamp hood. The lamp hood has a light-emitting element. The light-emitting element includes: a light conduction tube, a light conduction material and at least one light-emitting diode. A reflective mirror is arranged on the inner face of the lamp hood and around the light-emitting element. When the light-emitting diode emits light, the light-emitting element also emits light via the conduction of the light conduction tube and the reflection of the light conduction material. Then, the light emitted by the light-emitting element is reflected out by the reflective mirror. Thereby, the present invention can increase the illumination area, promote the brightness, decrease the number of required LEDs and reduce the cost. | 01-22-2009 |
20090027914 | Structure for a center high mounted stop lamp - The present invention discloses a structure for a center high mounted stop lamp, which comprises: a light pipe, a housing and LEDs. The light pipe has an inorganic light guide coating on a lateral side thereof and has LEDs at both ends thereof. The housing covers the light pipe and has a light reflection layer. The light reflection layer is arranged around the light pipe and behind the inorganic light guide coating. The light emitted by LEDs is scattered by the light pipe and reflected by the inorganic light guide coating. Thus, the light pipe can uniformly emit light. Further, the light emitted by the light pipe is concentrated and reflected out by the light reflection layer. Thereby, the present invention can decrease the number of required LEDs, save power, prolong the service life of LEDs and promote economic efficiency. | 01-29-2009 |
20110194297 | LED LAMP ASSEMBLY - The present invention discloses a LED lamp assembly, which comprises a lamp casing having a set of separator fixing protrusions arranged on the inner surface thereof and a set of panel fixing protrusions arranged on the inner surface thereof and below the separator fixing protrusions; a lamp fixing separator arranged inside the lamp casing and used to fix LED lamps, wherein the rim of the lamp fixing separator is fixed to the separator fixing protrusions; and a panel arranged inside the lamp casing and having at least one opening allowing the bottoms of the | 08-11-2011 |
Chih-Ming Wu, Hsinchu City TW
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20110152932 | Flexible Spine Fixing Structure - A flexible spine fixing structure is provided. The flexible spine fixing structure is used for fixing adjacent two or more vertebras. The flexible spine fixing structure comprises a first flexible part, a first fixing part and a second fixing part. The first fixing part and the second fixing part are respectively connected to two ends of the first flexible part for fixing in the first vertebra. The second flexible part is directly connected to the first flexible part. The third fixing part and the fourth fixing part are respectively connected to two ends of the second flexible part for fixing in the second vertebra. | 06-23-2011 |
20110160771 | Flexible Spine Fixing Structure - A flexible spine fixing structure for fixing to a first vertebra and a second vertebra includes a first flexible element and a second flexible element. The first flexible element includes a first flexible part, a first fixing part and a second fixing part. The first fixing part and the second fixing part are respectively connected to two ends of the first flexible part and used for fixing to the first vertebra, and the first flexible part includes a first through hole and a second through hole. The second flexible element includes a second flexible part, a third fixing part and a fourth fixing part. The third fixing part and the fourth fixing part are respectively connected to two ends of the second flexible part and used for fixing to the second vertebra. The second flexible part is disposed by penetrating through the first through hole and the second through hole. | 06-30-2011 |
20120078305 | FLEXIBLE SPINE FIXING STRUCTURE - A flexible spine fixing structure includes a first flexible element and a second flexible element. The first flexible element includes a first flexible part, a first fixing part and a second fixing part. The first fixing part and the second fixing part are respectively connected to two ends of the first flexible part and used for fixing to a first vertebra, and the first flexible part includes a first through hole and a second through hole. The second flexible element includes a second flexible part, a third fixing part and a fourth fixing part. The third fixing part and the fourth fixing part are respectively connected to two ends of the second flexible part and used for fixing to a second vertebra. The second flexible part is disposed by penetrating through the first through hole and the second through hole. | 03-29-2012 |
Chi-Hsi Wu, Hsinchu City TW
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20100270598 | METHOD FOR FORMING HIGHLY STRAINED SOURCE/DRAIN TRENCHES - A multi-step etching process produces trench openings in a silicon substrate that are immediately adjacent transistor structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms an opening bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The aggressive undercut produces a desirable stress in the etched silicon surface. The openings are then filled with a suitable source/drain material and SSD transistors with desirable I | 10-28-2010 |
20110079820 | DEVICE WITH SELF ALIGNED STRESSOR AND METHOD OF MAKING SAME - A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material. | 04-07-2011 |
20120018786 | HIGHLY STRAINED SOURCE/DRAIN TRENCHES IN SEMICONDUCTOR DEVICES - A semiconductor device is formed by a multi-step etching process that produces trench openings in a silicon substrate immediately adjacent transistor gate structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms the openings. The openings are bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The openings may be filled with a suitable source/drain material to produce SSD transistors with desirable I | 01-26-2012 |
20130161650 | DEVICE WITH SELF ALIGNED STRESSOR AND METHOD OF MAKING SAME - A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material. | 06-27-2013 |
20130330889 | METHOD OF MAKING A FINFET DEVICE - The present disclosure provides many different embodiments of fabricating a FinFET device that provide one or more improvements over the prior art. In one embodiment, a method of fabricating a FinFET includes providing a semiconductor substrate and a plurality of dummy fins and active fins on the semiconductor substrate. A predetermined group of dummy fins is removed. | 12-12-2013 |
20130334606 | FinFET with High Mobility and Strain Channel - An integrated circuit device includes a fin at least partially embedded in a shallow trench isolation (STI) region and extending between a source and a drain. The fin is formed from a first semiconductor material and having a trimmed portion between first and second end portions. A cap layer, which is formed from a second semiconductor material, is disposed over the trimmed portion of the fin to form a high mobility channel. A gate electrode structure is formed over the high mobility channel and between the first and second end portions. | 12-19-2013 |
20140291770 | Method of Making a FinFET Device - The present disclosure provides many different embodiments of fabricating a FinFET device that provide one or more improvements over the prior art. In one embodiment, a method of fabricating a FinFET includes providing a semiconductor substrate and a plurality of dummy fins and active fins on the semiconductor substrate. A predetermined group of dummy fins is removed. | 10-02-2014 |
Chin-Ju Wu, Hsinchu City TW
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20110133670 | Street lamp capable of adjusting illuminating range thereof and having LEDs as light source - A street lamp capable of adjusting illuminating range thereof and having LEDs as its light source is provided. The street lamp comprises: a main supporting member; a substrate, one end of the substrate being pivotally fixed to the main supporting member by a first fastening member, and an LED light source being provided on the surface opposite to the main supporting member; and an adjusting member provided between the main supporting member and the substrate, one end of the adjusting member being pivotally fixed to the main supporting member by a second fastening member, wherein a fixing member for adjusting the angle of the substrate to adjust the illuminating angle is provided between the substrate and the adjusting member when the first fastening member and the second fastening member are pivotally movable. | 06-09-2011 |
Chin-Weih Wu, Hsinchu City TW
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20080247205 | Controlling apparatus of an AC LED string - The invention relates to a controlling apparatus of an AC LED string, which includes a controller to control the string being capable of flickering or totally unflickering very easily. The apparatus can also connect an adjustable resistance for application on a string with various numbers of LEDs. The apparatus includes at least one set of a pair of slots with different shapes or sizes at output ends for connecting with the LED string correctively that obtains improvement and utilization. | 10-09-2008 |
20090045753 | LED lamp string - A LED lamp string, especially indicating a type of LED lamp string, which plug-fitting directly into AC power socket, and a controllable blinking or non-blinking structure which combining two or more than two groups of dual crystal current controllers in the main electrical wire circuitry to achieve results of bridge rectifier to make the current flowing through the LED lamp string become the state of DC current and thus achieve the non-blinking effect. | 02-19-2009 |
Fan-Yi Wu, Hsinchu City TW
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20110100267 | ROTARY TABLE - A rotary table includes a first plank which has a plurality of fastening portions and a plurality of rolling balls corresponding to fastening portions, and each fastening portion fastens each rolling ball to one side of the first plank, and a second plank which has a first baseboard, a second baseboard, an annular trough and at least one latch portion. The first baseboard and second baseboard have respectively a first trough and a second trough on one side thereof that are joined through the latch portion to form the second plank with the annular trough in a continuous manner at the same plane. The first plank is turnable relative to the second plank through the rolling balls moving in the annular trough. | 05-05-2011 |
Fu-An Wu, Hsinchu City TW
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20090244940 | VOLTAGE GENERATING CIRCUIT - A voltage generating circuit is provided, including a voltage output terminal, a ground terminal, a capacitor, a selector, a first switch, and a second switch. The capacitor is connected between a pump signal and the output of the selector. The selector is controlled by a first control signal and used to select the voltage source or the voltage output terminal to connect the capacitor. The first switch is controlled by a second control signal, and the second switch is controlled by a third control signal. When the first switch is turn-on, the voltage output terminal is connected to the ground terminal. When the second switch is turn-on, the voltage output terminal is connected to the voltage source. | 10-01-2009 |
20140035664 | VOLTAGE PROVIDING CIRCUIT - A voltage providing circuit includes a first circuit, a second circuit coupled with the first circuit, and a third circuit coupled with the second circuit. The first circuit is configured to receive a first input signal and to generate a first output signal. The second circuit is configured to receive the first input signal and the first output signal as inputs and to generate a second output signal. The third circuit is configured to receive the second output signal and to generate an output voltage. | 02-06-2014 |
20140084374 | CELL DESIGN - One or more techniques or systems for designing a cell are provided. The cell generally includes one or more transistors, such as a pass gate transistor, a pull up transistor, or a pull down transistor, respectively associated one or more gate to gate distances. In some embodiments, a second gate to gate distance is selected based on a first gate to gate distance. For example, the first gate to gate distance and the second gate to gate distance are associated with a first transistor. In another example, the first gate to gate distance is associated with a first transistor and the second gate to gate distance is associated with a second transistor. In this manner, a cell design is provided to improve a static noise margin (SNM) or a write margin (WM) for the cell, for example. | 03-27-2014 |
20140269110 | ASYMMETRIC SENSING AMPLIFIER, MEMORY DEVICE AND DESIGNING METHOD - A sensing amplifier for a memory device includes first and second nodes, an input device and an output device. The memory device includes first and second bit lines, and at least one memory cell coupled to the bit lines. The first and second nodes are coupled to the first and second bit lines, respectively. The input device is coupled to the first and second nodes and generates a first current pulling the first node toward a predetermined voltage in response to a first datum read out from the memory cell, and to generate a second current pulling the second node toward the predetermined voltage in response to a second datum read out from the memory cell. The output device is coupled to the first node to output the first or second datum read out from the memory cell. The first current is greater than the second current. | 09-18-2014 |
20140269114 | CIRCUIT FOR MEMORY WRITE DATA OPERATION - A pulsed dynamic LCV circuit for improving write operations for SRAM. The pulsed dynamic LCV circuit includes voltage adjustment circuitry having a plurality of selectable reduced supply voltages and timing adjustment circuitry having a plurality of selectable logical state transition timings for adjustably controlling the voltage and timing of a transition from a selected reduced supply voltage back to a nominal supply voltage. The voltage adjustment circuitry has a plurality of selectable transistors that when individually selected have a cumulative effect to pull the reduced supply voltage down further. The timing adjustment circuitry has a plurality of selectable multiplexers that when individually selected for a delayed voltage transition have a cumulative effect to delay return of voltage supplied to SRAM from a reduced supply voltage to a nominal supply voltage. | 09-18-2014 |
20150048869 | CIRCUIT AND METHOD FOR POWER MANAGEMENT - A method comprises identifying a number of power domains in a device, connecting the power domains to each other by a number of control devices during a wake-up mode of the device, and disconnecting the power domains after the wake-up mode of the device. | 02-19-2015 |
20150058664 | DYNAMIC MEMORY CELL REPLACEMENT USING COLUMN REDUNDANCY - A memory chip comprises a main memory array having a plurality of memory columns, a redundancy memory column associated with the main memory array, and a hit logic circuitry configured to generate a plurality of hit logic signals by a plurality of hit logic units in the hit logic circuitry to enable dynamic replacement of a defective memory cell in one of the memory columns for dynamic replacement by the redundancy memory column when the memory array is in operation. | 02-26-2015 |
Hsuan-Hsuan Wu, Hsinchu City TW
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20080240896 | CASSETTE EXCHANGE SYSTEM - A cassette exchange system is provided. The cassette exchange system includes a wafer temporary storage apparatus, a first cassette base, a second cassette base and a moving apparatus. The wafer temporary storage apparatus includes a number of wafer carrier units. The first cassette base is suitable for carrying a first cassette, and the second cassette base is suitable for carrying a second cassette. The moving apparatus connects the first cassette base with the second cassette base. Also, the moving apparatus sequentially moves the first cassette base and the second cassette base to the wafer temporary storage apparatus to simultaneously transfer the wafers stored in the first cassette to the second cassette. | 10-02-2008 |
Hsueh Cheng Wu, Hsinchu City TW
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20090087287 | APPARATUS AND METHOD FOR SEMICONDUCTOR WAFER TRANSFER - An apparatus for semiconductor wafer transfer comprises a first region for placement of a pod, a second region for placement of a cassette, an unloading mechanism, and a transferring mechanism for transferring wafers in the unloaded pod to the cassette horizontally. In an embodiment, the pod is unloaded by lifting the housing of the pod, and preferably the apparatus for movement of semiconductor wafers further comprises a carrying mechanism for moving the cassette toward the pod, so that the cassette can be closer to the pod for smoothing wafer transfer. | 04-02-2009 |
Jenn-Sheng Wu, Hsinchu City TW
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20090024493 | METHOD AND SYSTEM FOR MONITORING FORESTRY PRODUCTS - A method and system for monitoring forestry products are provided in the present invention, wherein at least one active communicating device is disposed on a forestry product, and reading and transmitting devices are also disposed in specific locations for building a monitoring and management mechanism to protect the forestry products from stealing. By means the method and system of the present invention, it is capable of providing real-time monitoring information and collecting evidence of illegal actions immediately so that the management staff can control the situation and status of the forestry products, which is useful for improving the efficiency of forestry management. Meanwhile, the present invention may also help to find those lawless persons who steal and fell illegally the forestry resources so as to ensure the safety of working environment for forest managing staff and sustainable management of forest and natural resources. | 01-22-2009 |
20090128336 | METHOD AND SYSTEM FOR MONITORING FORESTRY PRODUCTS - A method and system for monitoring forestry products are provided in the present invention, wherein at least one active communicating device is disposed on a forestry product, and reading and transmitting devices are also disposed in specific locations for building a monitoring and management mechanism to protect the forestry products from stealing. By means the method and system of the present invention, it is capable of providing real-time monitoring information and collecting evidence of illegal actions immediately so that the management staff can control the situation and status of the forestry products, which is useful for improving the efficiency of forestry management. Meanwhile, the present invention may also help to find those lawless persons who steal and fell illegally the forestry resources so as to ensure the safety of working environment for forest managing staff and sustainable management of forest and natural resources. | 05-21-2009 |
Jhy-Wen Wu, Hsinchu City TW
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20090053106 | Autonomous microfluidic apparatus - The present invention relates to an autonomous microfluidic apparatus. The autonomous microfluidic apparatus is substantially a substrate having a microchannel structure arranged thereon. As a microfluid is being filled in a loading well situated upstream of the microchannel structure, the microfluid is affected by interactions between gravity, adhesive force and surface tension and thus driven to flow downstream in the microchannel structure while filling a plurality of manifolds formed in a area situated downstream of the microchannel structure, so that accurate and autonomous quantification and separation of the microfluid using the plural manifolds, each having a specific length, can be achieved and provided for biomedical inspection and analysis. | 02-26-2009 |
20100152639 | WOUND TREATMENT APPARATUS - A wound treatment apparatus is disclosed, which comprises: a first portion, a second portion and a porous matrix. In an exemplary embodiment of the invention, the first portion, being an adhesive film, is formed with at least a first hole; and the second portion, being made of a flexible, water-resistant material, is formed with at least a second hole and at least a third hole in a manner that the at least one second hole and the at least one third hole are capable of communicating with each other and thus causes an accommodation space to be formed inside the second portion while the at least one second hole is arranged at a position corresponding to the at least one first hole as the second portion is connected to the first portion. Moreover, the porous matrix is received inside the accommodation space of the second portion. | 06-17-2010 |
J-Ian Wu, Hsinchu City TW
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20100066434 | TEMPERATURE COMPENSATING CIRCUIT AND METHOD - A temperature compensating circuit including a reference circuit, a transistor and a first circuit is provided. The reference circuit has a reference current and a resistance circuit, wherein the resistance circuit includes a first terminal receiving the reference current, a second terminal and a negative-temperature-coefficient resistor. The transistor has a drain, a source and a path disposed between the drain and the source, wherein the path of the transistor is connected in series with the resistance circuit, a gate of the transistor is electrically connected to the drain of the transistor and the second terminal of the resistance circuit, and the drain of the transistor produces a bias-voltage signal. The first circuit produces an output signal having a variable frequency in response to the bias-voltage signal, wherein the temperature compensating circuit utilizes the negative-temperature-coefficient resistor to compensate the variable frequency for a temperature change in the temperature compensating circuit. | 03-18-2010 |
Jieh-Tsorng Wu, Hsinchu City TW
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20090309772 | BACKGROUND CALIBRATION SYSTEM FOR CALIBRATING NON-LINEAR DISTORTION OF AMPLIFIER AND METHOD THEREOF - The present invention discloses a background calibration system and method for calibrating the non-linear distortion of the amplifier. The calibration method in the present invention includes: generating random sequences and inputting the random sequences in different amount and different sets into an amplifier; amplifying the random sequences and detecting linear and non-linear coefficients; quantizing the output linear signal from the amplifier, and generating a digital output signal; multiplying the digital output signal to generate a high-order signal; generating an estimated non-linear error for the amplifier by multiplying the high-order signal with the estimated non-linear coefficient; adding the non-linear signal with the digital output signal to generate a linear output signal; calculating the random value from the parameter extractor to determine the occurrence of non-linear distortion in the circuit, and further adjusting the non-linear coefficient to calibrating the amplifier. | 12-17-2009 |
Jiing-Yang Wu, Hsinchu City TW
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20090118231 | Pectin-modified resistant starch, a composition containing the same and method for preparing resistant starch - This invention relates to a pectin-modified resistant starch prepared by cross-linking starch with pectin by pectinesterase reaction. Such resistant starch is low amylase digestible and thus is useful in food products, including nutritional supplements, to reduce calorie content and increase fiber content. This invention also relates to a composition containing the resistant starch and a process for the preparation of the same. | 05-07-2009 |
Jin-Bao Wu, Hsinchu City TW
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20090169845 | STRUCTURAL MATERIAL OF DIAMOND LIKE CARBON COMPOSITE LAYERS AND METHOD OF MANUFACTURING THE SAME - A structural material of diamond like carbon (DLC) composite layers is provided. The structural material includes a composite material which is consisted of a metal layer, a first metal nitride layer, and a DLC thin film. The metal layer includes aluminum (Al), copper (Cu), zirconium (Zr), nickel (Ni), or vanadium (V). The first metal nitride layer includes aluminum nitride (Al—N), zirconium nitride (Zr—N), vanadium nitride (V—N), or nickel nitride (Ni—N). The DLC thin film of the structural material of DLC composite layers has high quality tetragonally bonded amorphous carbon (ta-C) with a sp | 07-02-2009 |
20100128416 | COMPOSITE CATHODE FOILS AND SOLID ELECTROLYTIC CAPACITORS COMPRISING THE SAME - A composite cathode foil is provided. The composite cathode foil includes an aluminum substrate, a metal layer formed thereon, a metal carbide layer formed on the metal layer, and a carbon layer formed on the metal carbide layer, wherein the metal of the metal layer is selected from the group consisting of IVB, VB and VIB groups. The invention also provides a solid electrolytic capacitor including the composite cathode foil. | 05-27-2010 |
20100213054 | VACUUM COATING APPARATUS WITH MUTIPLE ANODES AND FILM COATING METHOD USING THE SAME - A vacuum coating apparatus is disclosed. The apparatus includes a cathode target, a plurality of anodes, a transiting device, a pulsed arc discharge device, and a pulsed laser device. The plurality of anodes is placed on the transiting device and successively passes though a working position by the transiting device. The pulsed arc discharge device is electrically connected to the cathode target and the anode at the operable position to form plasma in a vacuum chamber for film coating. The pulsed laser device is located outside of the vacuum chamber and provides a pulsed laser beam onto the surface of the cathode surface to serve as a plasma trigger. A coating method for the vacuum coating apparatus is also disclosed. | 08-26-2010 |
20110149521 | THERMALLY CONDUCTIVE, ELECTRICALLY INSULATING COMPOSITE FILM AND STACK CHIP PACKAGE STRUCTURE UTILIZING THE SAME - Disclosed is a thermally conductive, electrically insulating composite film, including interface layers disposed on the top and bottom surface of a metal substrate, and an insulation layer. Because the film has thermal conductivity and electric insulation properties, it can be disposed between the chips of a stack chip package structure, thereby dissipating the heat in horizontal and vertical directions simultaneously. | 06-23-2011 |
20130266038 | APPARATUS AND METHOD FOR MEASURING THERMAL DIFFUSIVITY - An apparatus for measuring thermal diffusivity includes a Raman spectroscope, a heating device, and a signal analyzing unit. The Raman spectroscope is utilized to measure a Raman scattering intensity of different sites of a film to be measured. The heating device is utilized to provide a controllable thermal driving wave. The signal analyzing unit is utilized to analyze the Raman scattering intensity from the Raman spectroscope and the thermal driving wave so as to evaluate the thermal diffusivity of the film to be measured. | 10-10-2013 |
20140186716 | PROTECTED ACTIVE METAL ELECTRODE AND DEVICE WITH THE ELECTRODE - A protected active metal electrode and a device with the electrode are provided. The protected active metal electrode includes an active metal substrate and a protection layer on a surface of the active metal substrate. The protection layer at least includes a metal thin film covering the surface of the active metal substrate and an electrically-conductive thin film covering a surface of the metal thin film. A material of the metal thin film is Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, or W. A material of the electrically-conductive thin film is selected from nitride of a metal in the metal thin film, carbide of a metal in the metal thin film, a diamond-like carbon (DLC), and a combination thereof. | 07-03-2014 |
Jin-Ching Wu, Hsinchu City TW
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20090162263 | ATMOSPHERIC-PRESSURE PLASMA REACTOR - An atmospheric-pressure plasma reactor comprising a first electrode, a second electrode and a power generation unit. The first electrode and the second electrode respectively have a first opening and a second opening corresponding to each other. Disposed inside the first electrode is a gas-in space, which communicates with the first opening. Moreover, the power generation unit is coupled to the first electrode to provide the first electrode with AC power. The second electrode is grounded. The plasma process by the atmospheric-pressure plasma reactor is capable of forming high-uniformity thin film on a substrate. | 06-25-2009 |
Jiun-Yuan Wu, Hsinchu City TW
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20090289969 | IMAGE PROCESSING METHOD AND SYSTEM - The invention provides the image method and apparatus to increase the sharpness of a resized image. The image includes a plurality of pixels with an alpha value and an image data. The method detects the alpha value of neighboring first and second pixels. Weighting values of interpolated pixels between the first and second pixels are determined. The image data of the interpolated pixels are set to be identical to the image data of the first pixel when one of the first pixel or the second pixel is zero. | 11-26-2009 |
Jui-I Wu, Hsinchu City TW
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20110208981 | CURRENT LIMITING AND AVERAGING CIRCUIT AND PERIPHERAL DEVICE AND COMPUTER SYSTEM USING THE SAME - A current limiting and averaging circuit for driving a peripheral core circuit with a lower limit current value in response to a supply signal, includes a current limiting module, an energy storage module, and a converter module. The current limiting module provides a limited supply signal whose current value is smaller than or equal to an upper limit value according to the supply signal. The energy storage module stores a storage signal according to the limited supply signal when the upper limit value is higher than the lower limit current value and provides a discharge signal according to the storage signal when the upper limit value is lower than the lower limit current value. The converter module provides a driving signal for driving the peripheral core circuit in response to the limited supply signal or the limited supply signal and the discharge signal. | 08-25-2011 |
Jyh-Wen Wu, Hsinchu City TW
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20100152712 | FLUID PROCESSING SYSTEM AND COLLECTING DEVICE THEREOF - A collecting device is provided and utilized to collect a fluid, such as waste liquid or blood from a wound. The collecting device includes a first guiding element, an absorbing element and a second guiding element. The absorbing element includes a plurality of absorbing units disposed on the first guiding element. When the fluid is initially absorbed by at least one of the plurality of absorbing units, the fluid is then sequentially absorbed by the rest of the absorbing units along a predetermined path. The second guiding element is disposed on the first guiding element. The fluid absorbed by the plurality of absorbing units of the absorbing element is impeded to travel along the predetermined path by impediments of the second guiding element. | 06-17-2010 |
Ken Tang Wu, Hsinchu City TW
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20110074799 | SCAN-TYPE DISPLAY DEVICE CONTROL CIRCUIT - A scan-type display device control circuit is suitable for receiving successive frame data and driving a light-emitting diode (LED) display device accordingly. The scan-type display device control circuit includes a ping-pong buffer, a data storage controller, a line scan controller, a display buffer, and a scrambled pulse width modulation (PMW) signal generating device. The scan-type display device control circuit can utilize frame data circularly and repeatedly, so as to prevent a great mass of data from being transmitted repeatedly. Therefore, a band width for inputting data can be reduced significantly. Furthermore, the scrambled PMW signal generating device can scramble a PMW signal with a long period into a plurality of scrambled PMW signals with a short period. Therefore, the refresh rate can be efficiently enhanced without changing the band width for inputting data. | 03-31-2011 |
20120017108 | SERIAL CONTROLLER AND BI-DIRECTIONAL SERIAL CONTROLLER - A serial controller is adapted to receive an external clock and an input data, and output an inverted clock and an output data. The serial controller includes an inverter, a serial position detector, a synchronous clock generator, a serial register, and a half-cycle delay unit. Thereby, through the serial controller, the problem that the data signal and the driving clock are not synchronous when the clock series are inverted is avoided. Besides, a bi-directional serial controller further includes an identification unit and a data directing unit, and the serial controller is enabled to return the current status to a central control unit to serve as the reference for error detection. | 01-19-2012 |
20130314307 | DRIVING SYSTEM AND METHOD FOR DOT-MATRIX LIGHT-EMITTING DIODE DISPLAY DEVICE - A driving system and a method for a dot-matrix light-emitting diode display device. The driving system comprises a controller, a scan line driver, and a signal line driver. The controller provides a scan line control signal and a signal line control signal. The scan line driver generates a scan line driving signal in response to the scan line control signal. The scan line driving signal is divided into an ON period and a OFF period. The signal line driver generates a signal line driving signal in response to the signal line control signal. The signal line driver generates a discharging control signal or a charging control signal during the OFF period so that the signal line driver and the plurality of signal lines form the discharging or charging paths. Therefore, the parasitic capacitors on the scan lines are discharged or the parasitic capacitors on the signal lines are charged. | 11-28-2013 |
Kun-Tai Wu, Hsinchu City TW
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20090161275 | INTEGRATED CONTROLLING CHIP - An integrated controlling chip includes a signal processing unit, a resistance unit and an electrostatic discharge protection circuit. The signal processing unit includes an input port. The resistance unit includes a first node coupled to a signal pin of the integrated controlling chip, and includes a second node coupled to the input port of the signal processing unit. The electrostatic discharge protection circuit includes a node coupled between the first node of the resistance unit and the signal pin of the integrated controlling chip. | 06-25-2009 |
20090168282 | ESD PROTECTION CIRCUIT - An ESD protection circuit includes: a voltage decreasing module, coupled between a first voltage level and a second voltage level, wherein the first voltage level is higher than the second voltage level; a gate trigger switch, coupled between the first voltage level and the second voltage level; and a detection circuit, coupled to the gate trigger switch, for detecting an ESD event to control the gate trigger switch. | 07-02-2009 |
20090195949 | INTEGRATED CIRCUIT WITH ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An integrated circuit with an electrostatic discharge protection circuit includes a first power pad, a second power pad, at least a circuit module, and a power clamp circuit. The circuit module includes a signal pad, an internal circuit and a first bipolar transistor. A first parasitical resistance is coupled between a collector of the first bipolar transistor and the second power pad. There is at least a metal-oxide semiconductor (MOS) transistor and at least a first parasitical bipolar transistor included within the power clamp circuit. | 08-06-2009 |
20140162534 | POLISHING SYSTEM AND POLISHING METHOD - A polishing system for polishing a semiconductor wafer includes a wafer support for holding the semiconductor wafer, and a first polishing pad for polishing a region of the semiconductor wafer. The semiconductor wafer has a first diameter, and the first polishing pad has a second diameter shorter than the first diameter. | 06-12-2014 |
Mau-Lin Wu, Hsinchu City TW
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20090003385 | TX EVM IMPROVEMENT OF OFDM COMMUNICATION SYSTEM - In a wireless communication method and system, a data/pilot constellation is modulated and generated based on input information bits. Channel estimation (CE) sequence in frequency-domain is off-line generated. The frequency-domain channel estimation sequence is transformed into a time-domain channel estimation sequence by ideal IFFT to avoid IFFT (Inverse Fast Fourier Transform) impact to EVM (Error Vector Magnitude) performance. Off-line resealing the time-domain CE sequence, multiplied by a rescaling coefficient, in time-domain improves EVM performance. Further, the time-domain channel estimation sequence is off-line quantized. | 01-01-2009 |
20090122890 | OFDM DCM DEMODULATION METHOD - An OFDM DCM demodulation method is provided. The OFDM DCM demodulation method mainly includes the following steps. First, calculate a log likelihood of a first demodulation mode. Then calculate a log likelihood of a second demodulation mode. Finally, calculate a demodulation output according to the log likelihoods of the first demodulation mode and the second demodulation mode. The demodulation output may serve as an output of a demodulator of a receiving end of a DCM communication system. | 05-14-2009 |
20090285315 | APPARATUS AND METHOD FOR ADAPTIVE CHANNEL ESTIMATION AND COHERENT BANDWIDTH ESTIMATION APPARATUS THEREOF - An apparatus and a method for adaptive channel estimation and a coherent bandwidth estimation apparatus are provided. The adaptive channel estimation apparatus includes a first channel estimator, a coherent bandwidth estimator and a second channel estimator. The first channel estimator uses a predetermined approach to calculate a first channel response of each tone of an orthogonal frequency-division multiplexing (OFDM) signal. The coherent bandwidth estimator is coupled to the first channel estimator for calculating a coherent bandwidth according to the first channel responses. The second channel estimator is coupled to the first channel estimator and the coherent bandwidth estimator. For each of the tones, the second channel estimator calculates a weighted average according to the coherent bandwidth and the first channel responses of several adjacent tones including the aforementioned tone. The second channel estimator outputs the weighted average as the second channel response of the aforementioned tone. | 11-19-2009 |
Meng-Hsiu Wu, Hsinchu City TW
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20100207905 | Method of Performing Timely Calibration of a Touch Parameter and Related Apparatus and System - A method of performing timely calibration of a touch parameter for a capacitive touch panel is disclosed. The method includes storing the touch parameter into a control register, sensing an analog touch signal according to the touch parameter stored in the control register and transforming the analog touch signal into a digital touch signal, reading the digital touch signal according to a calibrating read command, calculating a modified touch parameter according to the digital touch signal and transmitting the modified touch parameter to the capacitive touch panel, changing the touch parameter stored in a control register for the modified touch parameter according to a calibrating write command, determining an optimal touch parameter according to the digital touch signal sensed by using the modified touch parameter, and changing the touch parameter stored in a storage unit for the optimal touch parameter according to an updating write command. | 08-19-2010 |
20100321328 | COORDINATES ALGORITHM AND POSITION SENSING SYSTEM OF TOUCH PANEL - A position sensing system of a touch panel including a sensing unit and a decision unit is provided. When the touch panel is touched, the sensing unit obtains the sensing capacitances of p x-directional sensing lines and q y-directional sensing lines, wherein the sensing capacitances generated by these sensing lines exceed a threshold. The decision unit takes the central coordinates of the sensing lines with peak sensing capacitances as an x base coordinate and a y base coordinate, and adjusts the x base coordinate and the y base coordinate according to the ratios of the sensing capacitances of the other sensing lines to the peak sensing capacitance respectively to obtain an interpolated x coordinate and an interpolated y coordinate. | 12-23-2010 |
20110083042 | Touch Control Device and Controller, Testing Method and System of the Same - A testing method for testing a touch control device is disclosed. In a controller of the touch control device, a processor executes an operating firmware to realize a touch control function. The testing method includes a host testing device outputting a test requirement command to the controller, the controller outputting data corresponding to an operating stage selected from a plurality of operating stages of executing the operating firmware to the host testing device according to the test requirement command, and the host testing device determining an operating status of the touch device according to data provided by the touch control device. | 04-07-2011 |
20110157076 | Method and Apparatus for Adjusting Touch Control Parameter - A method utilized for adjusting touch control parameters, for deciding time for updating a touch control parameter of a touch control device, is disclosed. The touch control parameter includes an equivalent value of base capacitance corresponding to an environmental capacitance and a threshold value corresponding to a touch event. The method includes determining an amount of a touch sensing signal being located in an invalid range when the touch sensing signal is located in the invalid range, and starting to update the equivalent value of base capacitance when the amount of the touch sensing signal being located in the invalid range is greater than a first default value. | 06-30-2011 |
20110316794 | TOUCH SENSING METHOD AND TOUCH SENSING SYSTEM - A touch sensing system including a touch interface and a processing unit is provided. The touch interface has multiple independent touch blocks. The processing unit is coupled to the touch interface. The processing unit includes an interpolating unit. The interpolating unit interpolates multiple spacing points between two adjacent touch blocks along a first direction to generate multiple first coordinate values. The processing unit determines a central block according to a threshold value and sensing values corresponding to the touch blocks, selects at least one touch block adjacent to the central block as a peripheral block, and determines a touch position on the touch interface according to the number of the spacing points, the sensing value corresponding to the peripheral block, a position of the peripheral block, the sensing value corresponding to the central block, and a position of the central block. | 12-29-2011 |
20120044158 | ELECTRONIC APPARATUS WITH TOUCH PANEL AND METHOD FOR UPDATING TOUCH PANEL - An electronic apparatus with a touch panel including a host controller, an interface unit, and a touch panel control unit is provided. The host controller is used to control an electronic apparatus implemented with the host controller. The touch panel control unit is coupled to the host controller through the interface unit. The host controller transmits an updating information to the touch panel control unit with a format of the interface unit, in which the updating data is used to update the touch panel control unit. The touch panel control unit decodes the updating data to accordingly update. | 02-23-2012 |
Meng-Huan Wu, Hsinchu City TW
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20100269103 | Method and device for multi-core instruction-set simulation - The present invention discloses a method for multi-core instruction-set simulation. The proposed method identifies the shared data segment and the dependency relationship between the different cores and thus effectively reduces the number of sync points and lowers the synchronization overhead, allowing multi-core instruction-set simulation to be performed more rapidly while ensuring that the simulation results are accurate. In addition, the present invention also discloses a device for multi-core instruction-set simulation. | 10-21-2010 |
20110197174 | Method, System and Computer Readable Medium for Generating Software Transaction-Level Modeling (TLM) Model - The present invention discloses a system for generating a software TLM model, comprising a processing unit; a compiler coupled to the processing unit to generate target binary codes of a target software; a decompiler coupled to the processing unit to decompile the target binary codes into high level codes, for example C or C++ codes, to generate a functional model of the target software, wherein the functional model includes a plurality of basic blocks; an execution time calculating module coupled to the processing unit to calculate overall execution time of the plurality of the basic blocks of the functional model; a sync point identifying module coupled to the processing unit to identify sync points of the software transaction-level modeling model; and a time annotating module coupled to the processing unit to annotate the overall execution time of the basic blocks and the sync points into the functional model to obtain the software transaction-level modeling model. | 08-11-2011 |
20110218791 | System for Simulating Processor Power Consumption and Method of the Same - The present invention provides a method for simulating processor power consumption, the method comprises: simulating a simulated processor; utilizing a power analysis model to analyze the simulated processor's execution of at least one fragment of a program, for generating power analysis of a plurality of basic blocks of the at least one fragment; computing at least one power correction factor between the plurality of basic block; utilizing a processing apparatus to generate a simulation model with power annotation based on the power analysis and the at least one power correction factor; and predicting power consumption of the simulated processor based on the simulation model with power annotation. | 09-08-2011 |
20120185231 | Cycle-Count-Accurate (CCA) Processor Modeling for System-Level Simulation - The present invention discloses a cycle-count-accurate (CCA) processor modeling, which can achieve high simulation speeds while maintaining timing accuracy of the system simulation. The CCA processor modeling includes a pipeline subsystem model and a cache subsystem model with accurate cycle with accurate cycle count information and guarantees accurate timing and functional behaviors on processor interface. The CCA processor modeling further includes a branch predictor and a bus interface (BIF) to predict the branch of pipeline execution behavior (PEB) and to simulate the data accesses between the processor and the external components via an external bus, respectively. The experimental results show that the CCA processor modeling performs 50 times faster than the corresponding Cycle-accurate (CA) model while providing the same cycle count information as the target RTL model. | 07-19-2012 |
20120191441 | High-Parallelism Synchronization Approach for Multi-Core Instruction-Set Simulation - The present invention discloses a high-parallelism synchronization method for multi-core instruction-set simulation. The proposed method utilizes a new distributed scheduling mechanism for a parallel compiled MCISS. The proposed method can enhance the parallelism of the MCISS so that the computing power of a multi-core host machine can be effectively utilized. The distributed scheduling with the present invention's prediction method significantly shortens the waiting time which an ISS spends on synchronization | 07-26-2012 |
20120197625 | Data-dependency-Oriented Modeling Approach for Efficient Simulation of OS Preemptive Scheduling - In the present disclosure, the DOM approach for the simulation of OS preemptive scheduling has presented and demonstrated. By maintaining the data-dependency between the software tasks, and guaranteeing the order of shared variable accesses, it can accurately simulate the preemption effect. Moreover, the proposed DOM OS model is implemented to enable preemptive scheduling in SystemC. | 08-02-2012 |
20120233410 | Shared-Variable-Based (SVB) Synchronization Approach for Multi-Core Simulation - The present invention discloses a shared-variable-based (SVB) approach for fast and accurate multi-core cache coherence simulation. While the intuitive, conventional approach, synchronizing at either every cycle or memory access, gives accurate simulation results, it has poor performance due to huge simulation overloads. In the present invention, timing synchronization is only needed before shared variable accesses in order to maintain accuracy while improving the efficiency in the proposed shared-variable-based approach. | 09-13-2012 |
Michael C.l. Wu, Hsinchu City TW
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20090250087 | GOLF UMBRELLA COMBINED WITH THE SPARE GOLF BALL - A kind of golf umbrella combined with a spare golf ball is mainly set with an assembling mechanism in the end of the handle of a golf umbrella. One lower end of the said assembling mechanism can be simply and firmly set on the handle with ease and it is set with a hemisphere sleeve-fit body to provide a temporary holding of a golf ball. Therefore, it becomes a last spare ball while playing golf and the practical value is thus obtained. | 10-08-2009 |
Min-Chuan Wu, Hsinchu City TW
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20110127957 | Charge/Start System and Electric Vehicle Applying the Same - A charge/start system applied in an electric vehicle is provided. The charge/start system includes a charge/start device coupled to an external power source, an on-car electric source coupled to the charge/start device and a battery unit coupled to the charge/start device for storing and providing power. In charge mode, under control of the charge/start device, anyone of the external power source and the on-car electric source provides power to the battery unit for charging the battery unit through the charge/start device. In starting mode, under control of the charge/start device, the battery unit provides power to the on-car electric source for activating the on-car electric source through the charge/start device. | 06-02-2011 |
20120126545 | ENGINE DEVICE - An engine device includes an engine, a power generating portion, a motor portion, and a transmission mechanism. The engine includes a piston and a cylinder, and the piston is arranged in the cylinder and moves back and forth between a top dead center and a bottom dead center. The power generating portion and the motor portion are annularly disposed on the periphery of the cylinder. When the piston moves from the top dead center towards the bottom dead center, the transmission mechanism drives a power generating rotor of the power generating portion to move correspondingly in a direction opposite to that of the piston and enables the power generating portion to generate electric power. When the piston is located at the bottom dead center, the motor portion actuates a motor rotor to move, and pushes the piston to move towards the top dead center through the transmission mechanism. | 05-24-2012 |
Ming-Der Wu, Hsinchu City TW
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20110165186 | NOVEL PYRIDINE ALKALOIDS, PREPARATION PROCESS THEREOF, AND THE USES OF THE PYRIDINE ALKALOIDS - The present invention relates to novel pyridine alkaloid compounds of formula (I): | 07-07-2011 |
20120164120 | NOVEL MONASCUSPURPURONES, PREPARATION PROCESS THEREOF, AND USES OF THE MONASCUSPURPURONES - The present invention relates to a novel monascuspurpurone compound of formula (I): | 06-28-2012 |
20140357555 | NOVEL MONASCUSPURPURONES, PREPARATION PROCESS THEREOF, AND USES OF THE MONASCUSPURPURONES - The present invention relates to a novel monascuspurpurone compound of formula (I): | 12-04-2014 |
M. Y. Wu, Hsinchu City TW
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20080254588 | METHODS FOR FORMING TRANSISTORS WITH HIGH-K DIELECTRIC LAYERS AND TRANSISTORS FORMED THEREFROM - A method for forming a semiconductor structure includes forming a gate dielectric layer over a substrate. A top surface of the gate dielectric layer is treated so as to at least partially nitridize the gate dielectric layer. The treated gate dielectric layer is thermally treated with an oxygen-containing precursor such that the at least partially nitridized gate dielectric layer has a nitrogen concentration between about 0.5 atomic percentage (at. %) and about 20 at %. | 10-16-2008 |
Paul Neng-Wei Wu, Hsinchu City TW
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20100112511 | Reflecting-Type Optical Inspection Apparatus and Related Dental Inspection System - A reflecting-type optical inspection apparatus is disclosed including: a holding portion configured for detachably holding an external device having a reflective surface; a connecting portion engaged with the holding portion; and a digital image sensing module engaged with the connecting portion for sensing light reflected from the reflective surface of the external device. | 05-06-2010 |
20100171827 | OPTICAL INSPECTION APPARATUS WITH A DETACHABLE LIGHT GUIDE - An optical inspection apparatus is disclosed including: a digital image sensing module, a light source, a detachable light guide configured for guiding incident light to transmit within the detachable light guide and to output from a first angle, and an adapter engaged with the digital image sensing module for guiding light emitted from the light source to the detachable light guide; wherein the detachable light guide is detachably engaged with the adapter. | 07-08-2010 |
20110235917 | DIGITAL IMAGE ANALYZING METHOD AND RELATED COMPUTER PROGRAM PRODUCT - A computer program product capable of enabling a computer to perform a digital image analyzing operation, wherein the digital image analyzing operation comprises: receiving settings of a plurality of lines corresponding to one or more image edges of a digital image; and identifying a plurality of intersections of the plurality of lines and the one or more image edges of the digital image. | 09-29-2011 |
20110261209 | DIGITAL IMAGING APPARATUS AND RELATED OBJECT INSPECTION SYSTEM - A digital imaging apparatus is disclosed including: a light source module; an image synchronization signal generator for generating an image synchronization signal; and a light source controller, coupled with the light source module and the image synchronization signal generator, for generating a light source control signal having a frequency corresponding to the image synchronization signal and synchronized with the image synchronization signal to control the light output of the light source module. | 10-27-2011 |
20120062721 | DIGITAL MICROSCOPE WITH COAXIAL LIGHT OUTPUT - A digital microscope is disclosed including: an image sensing circuit having an image sensing area thereon; a first object lens aligned with the image sensing area along an axis; a luminance device positioned outside the axis for emitting light toward a direction that is not coaxial with the axis; a light redirector positioned outside the axis for redirecting the light emitted from the luminance device; and a beam splitter positioned on the axis for changing the direction of light from the light redirector to provide an output light that is outputted substantially along the axis and coaxial with the axis; wherein the first object lens is positioned between the image sensing area and the beam splitter. | 03-15-2012 |
20130044201 | HAND-HELD FLUORESCENCE MICROSCOPE WITH PARTIAL-SPECTRUM LIGHT SOURCE - A hand-held fluorescence microscope is disclosed, including: a partial-spectrum light source, a first filtering device, a second filtering device, and an image sensor arranged inside a housing of the hand-held fluorescence microscope. The partial-spectrum light source generates a first light beam. The first filtering device filters the first light beam to provide a second light beam. The second filtering device filters a fluorescence generated by a specimen after receiving the second light beam to provide a fourth light beam. The image sensor receives the fourth light beam to generate fluorescence images. One end of the housing is provided with a light mask for surrounding the specimen to avoid external light from being entering the image sensor. The light path of the second light beam projecting to the specimen does not overlap with the light path of the fluorescence radiating from the specimen to the second filtering device. | 02-21-2013 |
Pin Shan Wu, Hsinchu City TW
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20100103319 | ON-SCREEN DISPLAY CIRCUIT AND METHOD FOR CONTROLLING THE SAME - An on-screen display (OSD) circuit comprises a microprocessor, a serial peripheral interface (SPI) controller, an upload controller and an OSD controller. The SPI controller is connected to the microprocessor for receiving data of an external flash memory. The upload controller is configured to control data access between the SPI controller and the memory. The OSD controller is configured to control a display of an operating screen by the data stored in the memory. The upload controller stores a font table or an icon table and background screen data in the memory while the OSD controller is active. | 04-29-2010 |
Ren-Jang Wu, Hsinchu City TW
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20100288637 | Gas Sensor and Manufacturing Method Thereof - A gas sensor and manufacturing method thereof. The gas sensor includes a substrate, a pair of electrodes disposed on the substrate, and a gas sensing thin film covering the electrodes, the gas sensing thin film is made up of carbon nanotubes and tin oxide. | 11-18-2010 |
20100310792 | Gas Sensor and Manufacturing Method Thereof - A gas sensor and manufacturing method thereof. The gas sensor includes a substrate, a pair of electrodes disposed on the substrate, and a gas sensing thin film covering the electrodes, the gas sensing thin film is made up of carbon nanotubes and tin oxide. | 12-09-2010 |
Rong-Tzong Wu, Hsinchu City TW
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20080308868 | HIGH VOLTAGE METAL OXIDE SEMICONDUCTOR TRANSISTOR AND FABRICATION METHOD THEREOF - A high voltage metal oxide semiconductor includes a doped substrate, two first isolation structures, a gate structure, a source region, a drain region, two second isolation structures, and two drift regions. The two first isolation structures are respectively disposed in the doped substrate. The gate structure is disposed between parts of the two first isolation structures on the doped substrate. The source region and the drain region are respectively disposed beside one side of each of the two first isolation structures in the doped substrate. The top surface of the second isolation structure is smaller than the bottom surface of the first isolation structure. The two drift regions are respectively disposed in the doped substrate, enclosing the source region and the drain region, the two first isolation structures and the second isolation structures. | 12-18-2008 |
Ruo-Ying Wu, Hsinchu City TW
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20110011148 | Method for forming patterned modified metal layer - A method for forming a patterned modified metal layer is disclosed, which comprises the following steps: (A) providing a metal base which is in the form of either a bulk metal or a metal coated substrate, and a mold with patterns; (B) applying the mold onto the metal base to transfer the patterns of the mold to the metal surface; (C) removing the mold; and (D) modifying the whole metal base or the, surface and a certain depth beneath the surface of metal base to form a modified metal layer with designated patterns. | 01-20-2011 |
20110156320 | Method for preparing patterned metal oxide layer or patterned metal layer by using solution type precursor or sol-gel precursor - Methods for preparing a patterned metal/metal oxide layer by using a solution type precursor or sol-gel precursor are provided and, especially, a method for preparing a patterned carrier transport of a solar cell and a method for preparing biomedical material are provided, which comprise the following steps: (A) providing a substrate, and a mold with designed patterns formed thereon; (B) coating the substrate with a solution of a precursor to form a precursor layer, wherein the precursor is a metal precursor or a metal oxide precursor; (C) pressing the mold together with the precursor layer to transfer the patterns of the mold onto the precursor layer; (D) curing or pre-curing the precursor layer; (E) removing the mold; and (F) conducting an optional post-treatment, if it being demanded, to further modify the properties of precursor layer. | 06-30-2011 |
Shang-Chi Wu, Hsinchu City TW
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20090108348 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. An isolation structure is formed in a substrate to define a first and a second active region, and a channel active region therebetween. A field implant region is formed below a portion of the isolation structure around the first, second, and channel active regions. A channel active region includes two first sides defining a channel width. The distance from each first side to a second side of a neighboring field implant region is d | 04-30-2009 |
20140070404 | SEMICONDUCTOR PACKAGE STRUCTURE AND INTERPOSER THEREFOR - An interposer for a semiconductor package structure includes a base substrate, a plurality of passive devices formed on the base substrate, and an identification (ID) code. The base substrate includes a first surface and an opposite second surface. The ID code is formed on the first surface or the second surface of the base substrate. | 03-13-2014 |
Shen-Cheng Wu, Hsinchu City TW
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20090104863 | PAD CONDITIONER FOR CHEMICAL MECHANICAL POLISHING - A pad conditioner for chemical mechanical polishing includes a dressing component for conditioning a pad and a housing for accommodating the dressing component. The housing includes at least one fluid hole surrounding the dressing component for providing at least a fluid. | 04-23-2009 |
Sheng Hsun Wu, Hsinchu City TW
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20110117587 | SINGLE MOLECULE DETECTION PLATFORM, MANUFACTURING METHOD THEREOF AND METHOD USING THE SAME - A single molecule detection platform is disclosed. The single molecule detection platform comprises a light-transmissive substrate, a plurality of spherical particles and a thin film. The surface of the light-transmissive substrate is etched to form a plurality of cone-shaped structures. Each spherical particle is disposed on top of each cone-shaped structure. The sizes of the plurality of spherical particles are suitable to allow only a single protein to be attached to each spherical particle. The thin film is deposited on the surface of the plurality of cone-shaped structures and acts as a reflective layer of one-dimensional waveguide. The plurality of spherical particles is not covered by the thin film. | 05-19-2011 |
Shih-Kuo Wu, Hsinchu City TW
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20100147350 | NANOWIRE THERMOELECTRIC DEVICE - A thermoelectric device is provided. The thermoelectric device includes a P-type thermoelectric component, an N-type thermoelectric component, and an electrically conductive layer. Each of the P-type thermoelectric component and the N-type thermoelectric component includes a substrate and a nanowire structure. The conductive layer connects the P-type thermoelectric component set with the N-type thermoelectric component set. The thermoelectric device is adapted for recycling heat generated by the heat source, and for effectively converting the heat into electrical energy. | 06-17-2010 |
Shyi-Yuan Wu, Hsinchu City TW
Patent application number | Description | Published |
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20090256183 | Single Gate Nonvolatile Memory Cell With Transistor and Capacitor - A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices. | 10-15-2009 |
20090256184 | Single Gate Nonvolatile Memory Cell With Transistor and Capacitor - A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices. | 10-15-2009 |
20110121373 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor memory device includes a substrate of a first impurity type, a first well region of a second impurity type in the substrate, the second impurity type being different from the first impurity type, a second well region of the first impurity type in the substrate, a patterned first dielectric layer on the substrate extending over the first and second well regions, a patterned first gate structure on the patterned first dielectric layer, a patterned second dielectric layer on the patterned first gate structure, and a patterned second gate structure on the patterned second dielectric layer. The patterned first gate structure may include a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, wherein the first section and the second section intersects each other in a cross pattern. The patterned second gate structure may include at least one of a first section extending in the first direction over the first section of the patterned first gate structure or a second section extending in the second direction over the second section of the patterned first gate structure. | 05-26-2011 |
20110140201 | LATERAL POWER MOSFET STRUCTURE AND METHOD OF MANUFACTURE - A lateral power MOSFET with a low specific on-resistance is described. Stacked P-top and N-grade regions in patterns of articulated circular arcs separate the source and drain of the transistor. | 06-16-2011 |
20110266601 | Single Gate Semiconductor Device - A semiconductor device has a gate multiple doping regions on both sides of the gate. The gate can be shared by a transistor and a capacitor. | 11-03-2011 |
20120001260 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device for use in a relatively high voltage application that comprises a substrate, a first n-type well region in the substrate to serve as a high voltage n-well (HVNW) for the semiconductor device, a pair of second n-type well regions in the first n-type well region, a p-type region in the first n-type well region between the second n-type well regions, a pair of conductive regions on the substrate between the second n-type well regions, and a number of n-type regions to serve as n-type buried layers (NBLs) for the semiconductor device, wherein the NBLs are located below the first n-type region and dispersed in the substrate. | 01-05-2012 |
20120086052 | HIGH VOLTAGE MOS DEVICE AND METHOD FOR MAKING THE SAME - A high-voltage metal-oxide-semiconductor (HVMOS) device may include a source, a drain, a gate positioned proximate to the source, a drift region disposed substantially between the drain and a region of the gate and the source, and a self shielding region disposed proximate to the drain. A corresponding method is also provided. | 04-12-2012 |
20120104492 | LOW ON-RESISTANCE RESURF MOS TRANSISTOR - The present invention relates to a low on-resistance RESURF MOS transistor, comprising: a drift region; two isolation regions formed on the drift region; a first-doping-type layer disposed between the two isolation regions; and a second-doping-type layer disposed below the first-doping-type layer. | 05-03-2012 |
20120241861 | Ultra-High Voltage N-Type-Metal-Oxide-Semiconductor (UHV NMOS) Device and Methods of Manufacturing the same - An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer. | 09-27-2012 |
20120248574 | Semiconductor Structure and Manufacturing Method and Operating Method for the Same - A semiconductor structure and a manufacturing method and an operating method for the same are provided. The semiconductor structure comprises a first well region, a second well region, a first doped region, a second doped region, an anode, and a cathode. The second well region is adjacent to the first well region. The first doped region is on the second well region. The second doped region is on the first well region. The anode is coupled to the first doped region and the second well region. The cathode is coupled to the first well region and the second doped region. The first well region and the first doped region have a first conductivity type. The second well region and the second doped region have a second conductivity type opposite to the first conductivity type. | 10-04-2012 |
20120280316 | Semiconductor Structure and Manufacturing Method for the Same - A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a first doped well, a first doped electrode, a second doped electrode, doped strips and a doped top region. The doped strips are on the first doped well between the first doped electrode and the second doped electrode. The doped strips are separated from each other. The doped top region is on the doped strips and extended on the first doped well between the doped strips. The first doped well and the doped top region have a first conductivity type. The doped strips have a second conductivity type opposite to the first conductivity type. | 11-08-2012 |
20130020680 | SEMICONDUCTOR STRUCTURE AND A METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a diode. The diode comprises a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated from each other by the first doped region. The third doped region has a first portion and a second portion adjacent to each other. The first portion and the second portion are respectively adjacent to and away from the second doped region. A dopant concentration of the first portion is bigger than a dopant concentration of the second portion. | 01-24-2013 |
20130207191 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a first doped region and a second doped region. The first doped region comprises a first contact region. The first doped region and the first contact region have a first type conductivity. The second doped region comprises a second contact region. The second doped region and the second contact region have a second type conductivity opposite to the first type conductivity. The first doped region is adjacent to the second doped region. | 08-15-2013 |
20130265102 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and method for manufacturing the same are provided. The semiconductor structure includes a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type formed in the deep well and extending down from the surface of the substrate; and a second well having the second conductive type formed in the deep well and extending down from the surface of the substrate, and the second well adjacent to the first well. The first well includes a block region and plural finger regions joined to one side of the block region, while the second well includes plural channel regions interlaced with the finger regions to separate the finger regions. | 10-10-2013 |
20130295728 | Semiconductor Structure and Manufacturing Method for the Same - A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a first doped well, a first doped electrode, a second doped electrode, doped strips and a doped top region. The doped strips are on the first doped well between the first doped electrode and the second doped electrode. The doped strips are separated from each other. The doped top region is on the doped strips and extended on the first doped well between the doped strips. The first doped well and the doped top region have a first conductivity type. The doped strips have a second conductivity type opposite to the first conductivity type. | 11-07-2013 |
20140015016 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a bulk, a gate, a source, a drain and a bulk contact region. The gate is on the bulk. The source and the drain are in the bulk on opposing sides of the gate respectively. The bulk contact region is only in a region of the bulk adjacent to the source. The bulk contact region is electrically connected to the bulk. | 01-16-2014 |
20140024205 | SEMICONDUCTOR STRUCTURE AND A METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a diode. The diode comprises a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated from each other by the first doped region. The third doped region has a first portion and a second portion adjacent to each other. The first portion and the second portion are respectively adjacent to and away from the second doped region. A dopant concentration of the first portion is bigger than a dopant concentration of the second portion. | 01-23-2014 |
20140054656 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a device region, a first doped region and a gate structure. The first doped region is formed in the substrate adjacent to the device region. The gate structure is on the first doped region. The first doped region is overlapped the gate structure. | 02-27-2014 |
20140061721 | MOS DEVICE AND METHOD FOR FABRICATING THE SAME - An improved MOS device is provided whereby the p-top layer is defined by a series of discretely placed p type top diffusion regions. The invention also provides methods for fabricating the MOS device of the invention. | 03-06-2014 |
20140061790 | SPLIT-GATE LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE - A semiconductor device includes a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A self-aligned RESURF region is disposed within the drift region between the gate and the drain region. PI gate structures including an upper polysilicon layer are disposed near the drain region, such that the upper polysilicon layer can serve as a hard mask for the formation of the double RESURF structure, thereby allowing for self-alignment of the double RESURF structure. | 03-06-2014 |
20140065781 | Ultra-High Voltage N-Type-Metal-Oxide-Semiconductor (UHV NMOS) Device and Methods of Manufacturing the same - An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer. | 03-06-2014 |
20140264855 | SEMICONDUCTOR COMPOSITE LAYER STRUCTURE AND SEMICONDUCTOR PACKAGING STRUCTURE HAVING THE SAME THEREOF - A semiconductor composite layer structure disposed on a substrate having an electronic circuit structure and a first conductive layer is disclosed. The semiconductor composite layer structure comprises a plurality of dielectric layers, a first wetting layer, a stiff layer and a second wetting layer. The dielectric layers are disposed on the substrate separately. The first wetting layer is disposed on the dielectric layer and the substrate between the dielectric layers. The stiff layer is disposed on the first wetting layer. The second wetting layer is disposed on stiff layer, for contacting with a second conductive layer. | 09-18-2014 |
20140302654 | MOS device and method of manufacturing the same - A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region. | 10-09-2014 |
20140332886 | SINGLE POLY PLATE LOW ON RESISTANCE EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR DEVICE - A semiconductor device, in particular, an extended drain metal oxide semiconductor (ED-MOS) device, defined by a doped shallow drain implant in a drift region. For example, an extend drain n-channel metal oxide semiconductor (ED-NMOS) device is defined by an n doped shallow drain (NDD) implant in the drift region. The device is also characterized by conductive layer separated from a substrate in part by a thin oxide layer and in another part by a thick/thin oxide layer. A method of fabricating a semiconductor device, in particular an ED-NMOS device, having a doped shallow drain implant of a drift region is also provided. A method is also provided for fabricating conductive layer disposed in part across a thin oxide layer and in another part across a thick/thin oxide layer. | 11-13-2014 |
20150048452 | ULTRA-HIGH VOLTAGE SEMICONDUCTOR HAVING AN ISOLATED STRUCTURE FOR HIGH SIDE OPERATION AND METHOD OF MANUFACTURE - A semiconductor device, in particular, an ultra-high metal oxide semiconductor (UHV MOS) device, is defined by a doped gradient structure in a drain region. For example, an ultra-high n-type metal oxide semiconductor (UHV NMOS) device is defined by an n-doped gradient structure in the drain region. The n-doped gradient structure has at least one of a high voltage n- (HVN-) well, a drain side high voltage n-type deep (HVND) well, and a drain side n-type well (NW) disposed in the drain region. A drain side n+ well is additionally disposed in the at least one of the HVN- well, the drain side HVND well, and the drain side NW. A method of manufacturing a UHV NMOS device having a doped gradient structure of a drain region is also provided. | 02-19-2015 |
Suh-Chin Wu, Hsinchu City TW
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20100197012 | Application of RNA Interference Targeting dhfr Gene, to Cell for Producing Secretory Protein - Biological materials are applied to a CHO cell or the like for enhancing production of a species of protein. The biological materials includes an expression vector and a silencing vector, the expression vector including a dhfr gene of a species of mammal and a gene encoding the species of protein, the silencing vector including a DNA fragment for inducing a RNA interference in the CHO cell to reduce expressions of both exogenous dhfr gene and endogenous dhfr gene after the biological material is applied to the CHO cell, and the CHO cell is thus not limited to dhfr gene deficient type. The DNA fragment consists of nucleotides characterizing a segment of a dhfr gene of the CHO cell and a segment of a dhfr gene of the species of mammal. | 08-05-2010 |
20120269853 | ATTENUATED DENGUE VIRUS VACCINE CONTAINING ADAPTIVE MUTATION FROM MRC-5 CELLS - The present invention relates to an attenuated dengue virus vaccine. In present invention, target mutagenesis at Glu | 10-25-2012 |
Sung-Yang Wu, Hsinchu City TW
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20090116368 | METHOD AND SYSTEM FOR DETERMINING DISC FORMAT FOR RECOVERY OF DATA RECORDING - A method for determining a disc format is disclosed. Data from at least one address of the disc is retrieved, wherein the at least one address is selected from a plurality of predetermined addresses related to the disc format. The disc format is determined according to the retrieved data. | 05-07-2009 |
20090175142 | METHOD AND SYSTEM OF RECORDING DATA ON A STORAGE MEDIUM - A method of recording data on a storage medium is provided. A first recording indicator is written on the storage medium to indicate a first state of a data recording thereon. A second recording indicator is written on the storage medium to indicate a second state of the data recording thereon. A recording status of the data recording is determined accordingly in accordance with the first and second indicators. | 07-09-2009 |
20100020654 | METHOD AND APPARATUS FOR DATA BUFFER CONTROL OF OPTICAL DISC PLAYER - An optical disc player for playback of a multimedia file stored in an optical disc is disclosed. The optical disc player includes a front-end loader and a back-end playback engine. The front-end loader, including a first data buffer, reads data from the optical disc and stores the read data in the first data buffer when the amount of data stored in the first data buffer is less than a first threshold. The back-end playback engine receives the data from the first data buffer and plays a multimedia segment corresponding to the received data. The front-end loader increases the first threshold of the first data buffer before a time-consuming servo behavior occurs. | 01-28-2010 |
20100060983 | Adjustable Parallax Barrier 3D Display - A parallax barrier 3D display utilizes adjustable at least one parallax barrier for having an observer always retrieve stereo vision no matter whether horizontal or vertical movements towards the parallax barrier 3D display are made. The parallax barrier is adjustable in its width and a distance from the parallax barrier 3D display, or a parallax barrier having an appropriate width or distance may be chosen from each parallax barrier set. Therefore, the observer does not have to search for sweet spots nor keep on staying at the sweet spots for retrieving stereo vision. | 03-11-2010 |
20100074071 | METHOD FOR READING DISK MANAGEMENT DATA OF AN OPTICAL DISK - The invention provides a method for reading disk management data of an optical disk. In one embodiment, the disk management data comprises data layout information of the optical disk, and a plurality of disk management data copies of the disk management data is stored on the optical disk. First, a first disk management data copy selected from the plurality of disk management data copies is read from the optical disk. An accuracy measure of the first disk management data copy is then calculated to determine whether the accuracy measure of the first disk management data copy is acceptable. When the accuracy measure of the first disk management data copy is acceptable, the optical disk is accessed according to the first disk management data copy. | 03-25-2010 |
20100232274 | METHOD AND APPARATUS FOR DETECTING DISC - A method for detecting a disc, the method includes the steps of: reading a file system of the disc; determining a type of the disc according to the file system; and abandoning a multi-session checking process upon the disc if the type of the disc is a one-session disc. | 09-16-2010 |
Szu-Pei Wu, Hsinchu City TW
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20110003346 | SYNTHESIS METHOD OF AROMATIC AMINO ACIDS - A synthesis method of aromatic amino acids according to one aspect of the present invention includes a process of preparing thermostable enzyme, a process of amino-transferring reaction and a process of product precipitation and enzyme recycling. The process of preparing thermostable enzyme comprises an isolation step of the gene of | 01-06-2011 |
Tai-Bor Wu, Hsinchu City TW
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20100075507 | Method of Fabricating a Gate Dielectric for High-K Metal Gate Devices - The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a substrate, forming an interfacial layer on the substrate by treating the substrate with radicals, and forming a high-k dielectric layer on the interfacial layer. The radicals are selected from the group consisting of hydrous radicals, nitrogen/hydrogen radicals, and sulfur/hydrogen radicals. | 03-25-2010 |
20110011148 | Method for forming patterned modified metal layer - A method for forming a patterned modified metal layer is disclosed, which comprises the following steps: (A) providing a metal base which is in the form of either a bulk metal or a metal coated substrate, and a mold with patterns; (B) applying the mold onto the metal base to transfer the patterns of the mold to the metal surface; (C) removing the mold; and (D) modifying the whole metal base or the, surface and a certain depth beneath the surface of metal base to form a modified metal layer with designated patterns. | 01-20-2011 |
Teng Chun Wu, Hsinchu City TW
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20110241719 | SOLAR CELL MEASUREMENT SYSTEM AND SOLAR SIMULATOR - A measurement system having a light source, a holding device, and a measurement device. The light source includes a plurality of light emitting diodes (LEDs) configured to generate light beams with different wavelengths, and the emission spectrum of the light source complies with a predetermined standard. The holding device is configured to hold an object under test. The measurement device is configured to measure the electrical properties of the object under test after the object under test is illuminated by the light source. | 10-06-2011 |
20110291995 | STERILIZING DEVICE AND MANUFACTURING METHOD FOR STERILIZING DEVICE - A sterilizing device comprises a light guiding member and an ultraviolet (UV) light source. The light guiding member has a surface. The UV light source emits UV light rays such that the UV light rays are guided into the guiding member based on a total internal reflection. When an object contacts or comes close to the surface, an evanescent wave from the UV light rays irradiates on the object. | 12-01-2011 |
20130079688 | APPARATUS OF CARDIOPULMONARY RESUSCITATOR - The present disclosure discloses an apparatus of cardiopulmonary resuscitator that is operated through a driving mechanism controlled and driven by air power. The driving mechanism functions to actuate a belt adapted to extend around a chest of a patient to generate reciprocating movement of pressing and releasing so as to achieve a purpose of cardiopulmonary resuscitation for recovering heartbeat and breathing of the patent. | 03-28-2013 |
Te-Sun Wu, Hsinchu City TW
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20110089888 | Multifunctional Notebook Battery Device - A notebook computer battery pack device charges an external electrical device and powers a notebook computer. The notebook computer battery pack device includes battery cells for converting chemical energy into direct current power, a first interface connector for transferring the direct current power to a notebook computer, a second interface connector for transferring the direct current power to the external electrical device, battery management circuitry for providing circuit protection, and charging circuitry for charging the external electrical device through the second interface connector. | 04-21-2011 |
Tse-Hong Wu, Hsinchu City TW
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20080198706 | BUFFER MANAGEMENT METHOD AND OPTICAL DISC DRIVE - An optical disc drive is provided, mainly comprising a buffer, a processor and a driving module for accessing an optical disc. The optical disc drive receives a plurality of write commands. Each write command comprises a data block and a destination address. The buffer buffers data blocks to be recorded to the optical disc with corresponding write commands in either a random mode or a sequential mode. The processor schedules a recording operation based on the write commands, and selectively switches the buffer to the random mode or to the sequential mode based on arrangements of data blocks buffered in the buffer. The driving module is controlled by the processor to perform the recording operation, whereby the data blocks are recorded to the optical disc when a start recording condition is met. Specifically, the start recording condition varies with the random or sequential modes. | 08-21-2008 |
20080198709 | RANDOM ACCESS CONTROL METHOD AND OPTICAL DISC DRIVE - A random access control method is provided, implemented in an optical disc drive for recording data to an optical disc. In the optical disc drive, a buffer stores a plurality of write commands each associated with a data block bound to a destination address. A processor controls the buffer to build a disc write task from the write commands in which addresses are organized in order. A drive unit is controlled by the processor, performing a recording operation to record the data blocks to the optical disc according to the disc write task; wherein the processor further controls the drive unit to verify the recorded data blocks after completing the recording operation. | 08-21-2008 |
20080201522 | BUFFER MANAGEMENT METHOD AND OPTICAL DISC DRIVE - A buffer management method is provided, particularly adaptable in an optical disc drive to access an optical disc. One or more data blocks are recorded to the optical disc in response to received write commands. Data blocks corresponding to the write commands are first buffered in a buffer of the optical disc drive. Thereafter, one or more write tasks may be organized based on the buffered write commands, each associated with a group of data blocks having consecutive destination addresses. A recording operation can be scheduled based on those write tasks, and the recording operation is performed to record the data blocks to the optical disc. | 08-21-2008 |
20090013192 | INTEGRITY CHECK METHOD APPLIED TO ELECTRONIC DEVICE, AND RELATED CIRCUIT - An integrity check method applied to an electronic device includes: fetching at least one portion of external data into a specific memory, where the external data is stored within the electronic device; during fetching the portion of the external data into the specific memory, checking whether the size of the fetched data in the specific memory reaches a predetermined value, where the predetermined value is less than the total size of the external data; and when the size of the fetched data in the specific memory reaches the predetermined value, enabling an integrity check of the fetched data. | 01-08-2009 |
20090327750 | SECURITY SYSTEM FOR CODE DUMP PROTECTION AND METHOD THEREOF - A security system for code dump protection includes a storage device, a processor, and a decryption unit. The storage device has a protected storage area storing at least an encrypted code segment. The processor is utilized for issuing at least one address pattern to the storage device for obtaining at least one information pattern corresponding to the address pattern. The decryption unit checks signal communicated between the processor and the storage device to generate a check result, and determines whether to decrypt the encrypted code segment in the protected storage area to generate a decrypted code segment to the processor according to the check result. | 12-31-2009 |
20100077120 | EMBEDDED SYSTEM AND INTERRUPTION HANDLING METHOD - An embedded system and an interruption handling method are provided. A plurality of interruption requests are received, and corresponding service routines are triggered with priority control. In the embedded system, a memory device comprises a plurality of service routines stored at different entry addresses, each related to an interruption request. A processor receives an enable signal to initialize one of the service routines through a branch instruction. A control unit buffers the interruption requests to schedule executions of corresponding service routines. When a specific service routine is to be executed, the control unit provides the branch instruction pointing to entry address of the specific service routine and asserts the enable signal to the processor, such that the processor executes the branch instruction to initialize the specific service routine. | 03-25-2010 |
20100214888 | RANDOM ACCESS CONTROL METHOD AND OPTICAL DISC DRIVER - A random access control method is provided, implemented in an optical disc drive for recording data to an optical disc. In the optical disc drive, a buffer stores a plurality of write commands each associated with a data block bound to a destination address. A processor controls the buffer to build a disc write task from the write commands in which addresses are organized in order. A drive unit is controlled by the processor, performing a recording operation to record the data blocks to the optical disc according to the disc write task; wherein the processor further controls the drive unit to verify the recorded data blocks after completing the recording operation. | 08-26-2010 |
20120233362 | BUFFER MANAGEMENT METHOD AND OPTICAL DISC DRIVE - A buffer management method operates by receiving a read command, wherein the read command comprises a read destination address for designating an associated area of a storage media; receiving write commands, wherein each of the write command comprises a data block and a write destination address for designating an associated location of the storage media to store the data block; buffering the data blocks of the write commands in a buffer; generating a latest list, wherein the latest list comprises a plurality of buffer indexes indicating buffer areas for storing the data blocks associated with the latest certain amount of received write commands; and determining whether the read destination address of the read command is associate with the latest list. | 09-13-2012 |
20130318363 | SECURITY SYSTEM FOR CODE DUMP PROTECTION AND METHOD THEREOF - A security system for code dump protection includes a storage device, a processor, and a decryption unit. The storage device has a protected storage area storing at least an encrypted code segment. The processor is utilized for issuing at least one address pattern to the storage device for obtaining at least one information pattern corresponding to the address pattern. The decryption unit checks the address pattern and the information pattern to generate a check result, and determines whether to decrypt the encrypted code segment in the protected storage area to generate a decrypted code segment to the processor according to the check result. | 11-28-2013 |
Tung-Li Wu, Hsinchu City TW
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20100321660 | METHOD AND APPARATUS FOR REDUCING DOWN TIME OF A LITHOGRAPHY SYSTEM - An apparatus includes a radiation source that emits a radiation beam that causes substantially all of a quantity of material to evaporate; and structure having first and second surface portions, a first operational mode wherein a greater quantity of a byproduct of the evaporation impinges on the first surface portion, and a second operational mode wherein a greater quantity of the byproduct impinges on the second surface portion. A different aspect involves emitting a radiation beam toward a quantity of material, the radiation beam causing substantially all of the quantity of material to evaporate; operating a structure having first and second surface portions in a first operational mode wherein a greater quantity of a byproduct of the evaporation impinges on the first surface portion; and thereafter operating the structure in a second operational mode wherein a greater quantity of the byproduct impinges on the second surface portion. | 12-23-2010 |
20130293857 | LITHOGRAPHY APPARATUS HAVING DUAL RETICLE EDGE MASKING ASSEMBLIES AND METHOD OF USE - A lithography apparatus includes at least two reticle edge masking assemblies (REMAs). The lithography apparatus further includes a light source configured to emit a light beam having a wavelength and a beam separating element configured to divide the light beam into more than one collimated light beam. Each REMA is positioned to receive one of the more than one collimating light beams and each REMA comprises a movable slit for passing the one collimated light beam therethrough. The lithography apparatus further includes at least one mask having a pattern, where the at least one mask is configured to receive light from at least one of the REMA and a projection lens configured to receive light from the at least one mask. A method of using a lithography apparatus is also discussed. | 11-07-2013 |
Wei-De Wu, Hsinchu City TW
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20090164542 | METHOD FOR CALCULATING COEFFICIENTS OF FILTER AND METHOD FOR FILTERING - A method for calculating coefficients of a filter and a method for filtering are provided. The invention directly factorizes a specific function in a cepstrum domain by spectral factorization and cepstrum technique to obtain coefficients of denominator function from the filter. In other words, the invention adopts a non-iterative algorithm to reduce computational complexity and avoid convergence due to calculating coefficients. Besides, the specific function of the invention includes a compensation function, so that a Fourier transform with greatly reduced size can be utilized in the spectral factorization to greatly save the computations and keep good system performance at a receiver. | 06-25-2009 |
20130283120 | DECODING APPARATUS WITH DE-INTERLEAVING EFFORTS DISTRIBUTED TO DIFFERENT DECODING PHASES AND RELATED DECODING METHOD THEREOF - A decoding apparatus includes a memory device and a decoding circuit. The memory device is arranged for storing a data block with inter-row interleaving in a plurality of data rows of the data block and without intra-row interleaving in each of the data rows. The decoding circuit is coupled to the memory device. The decoding circuit is arranged for accessing the memory device to perform a first decoding operation with inter-row de-interleaving memory access, and accessing the memory device to perform a second decoding operation with intra-row de-interleaving memory access memory access. | 10-24-2013 |
20130322402 | METHOD AND APPARATUS FOR PERFORMING CHANNEL CODING CONTROL - A method and apparatus for performing channel coding control are provided. The method may include: adding CRC bits to information bits, for performing channel encoding corresponding to the electronic device to generate an encoding result; performing data arrangement corresponding to the electronic device on at least one of the encoding result and a derivative thereof to generate a data arrangement result, for use of generating a processing result corresponding to the electronic device; and transmitting the processing result corresponding to the electronic device to UE. More particularly, for a same set of information bits to be transmitted from a plurality of electronic devices including the electronic device to the UE, the encoding result could be different from that in any other electronic device within the electronic devices, and a coding chain represented by the data arrangement result is different from that in any other electronic device within the electronic devices. | 12-05-2013 |
20130324138 | METHOD AND APPARATUS FOR PERFORMING CHANNEL CODING TYPE CONTROL - A method and apparatus for performing channel coding type control are provided, where the method may include: obtaining a code block size to be used during channel encoding (or decoding) for a Transport Format (TF); comparing the code block size with at least one predetermined threshold to generate at least one comparison result; selecting a specific channel coding type from a plurality of channel coding types according to the at least one comparison result; and utilizing the specific channel coding type during channel encoding (or decoding) for the TF. It is an advantage that the method can utilize code-block-size-dependent channel coding types during channel encoding (or decoding), so the channel coding gain can be increased, and therefore the goal of improving the system capacity and reducing the power consumption can be achieved. | 12-05-2013 |
20140281843 | DECODING APPARATUS WITH ADAPTIVE CONTROL OVER EXTERNAL BUFFER INTERFACE AND TURBO DECODER AND RELATED DECODING METHOD THEREOF - A decoding apparatus has an on-chip buffer, an external buffer interface, and a turbo decoder. The on-chip buffer is arranged for buffering each code block to be decoded. The external buffer interface is arranged for accessing an off-chip buffer. The turbo decoder is arranged for decoding a specific code block read from the on-chip buffer. The specific code block is not transmitted from the on-chip buffer to the off-chip buffer via the external buffer interface unless decoding fail of the specific code block is identified. | 09-18-2014 |
Wei-Hao Wu, Hsinchu City TW
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20100102872 | Dynamic Substrate Bias for PMOS Transistors to Alleviate NBTI Degradation - This invention discloses a system and method for suppressing negative bias temperature instability in PMOS transistors, the system comprises a PMOS transistor having a source connected to a power supply, and a voltage control circuitry configured to output a first and a second voltage level, the first and second voltage levels being different from each other, the first voltage level is lower than the power supply voltage, the second voltage level is equal to or higher than the power supply voltage, wherein when the PMOS transistor is turned on, the first voltage level is applied to a substrate of the PMOS transistor, and when the PMOS transistor is turned off, the second voltage level is applied to the substrate of the PMOS transistor. | 04-29-2010 |
20130113041 | SEMICONDUCTOR TRANSISTOR DEVICE WITH OPTIMIZED DOPANT PROFILE - Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel. | 05-09-2013 |
20130113047 | MOSFET STRUCTURE WITH T-SHAPED EPITAXIAL SILICON CHANNEL - A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized. | 05-09-2013 |
20130256796 | MOSFET WITH SLECTIVE DOPANT DEACTIVATION UNDERNEATH GATE - A method of fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET) device on a substrate includes doping a channel region of the MOSFET device with dopants of a first type. A source and a drain are formed in the substrate with dopants of a second type. Selective dopant deactivation is performed in a region underneath a gate of the MOSFET device. | 10-03-2013 |
20140138763 | Semiconductor Integrated Device with Channel Region - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device precursor. The semiconductor device precursor includes a substrate, source/drain regions on the substrate, dummy gate stacks separating the source/drain regions on the substrate and a doped region under the dummy gate stacks. The dummy gate stack is removed to form a gate trench. The doped region in the gate trench is recessed to form a channel trench. A channel layer is deposited in the channel trench to form a channel region and then a high-k (HK) dielectric layer and a metal gate (MG) are deposited on the channel region. | 05-22-2014 |
Wen-Chou Wu, Hsinchu City TW
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20090308653 | SHIELDING DEVICE - A shielding device for serving as an electromagnetic shield includes a shield body having a top piece and a plurality of sidewall pieces, and an electromagnetic band-gap (EBG) structure disposed on the top piece of the shield body. | 12-17-2009 |
Wing-Jin Wu, Hsinchu City TW
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20100248427 | METHOD OF HANDLING A THIN WAFER - A method of handling a thin wafer includes forming a support structure at the edge of a thinned wafer that is encapsulated by a protection layer. The support structure can be an adhesive layer enclosing the protection layer, a dielectric-filled trench embedded in the thinned wafer and surrounding the protection layer, or a housing affixing the edge of the thinned wafer. | 09-30-2010 |
Yi-Jui Wu, Hsinchu City TW
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20110181628 | POWER-SAVING AND CONTEXT-SHOWING DISPLAY INFORMATION CONVERTING SYSTEM AND CORRESPONDING APPARATUS - A context-showing and power-saving display information converting system and a corresponding apparatus are provided for lowering the power consumption of displaying images on a pixel self-emissive display device. The display information converting system includes a context-showing module and a power-saving conversion module. The context-showing module receives display information that describes the content of an image, wherein the display information includes one or more elements, and each element corresponds to a plurality of pixels displayed by a display device. In addition, the context-showing module determines a relevance of the one or more elements according to the viewing interest of the user. The power-saving conversion module converts the display information in unit of the one or more elements according to the relevance and provides the converted display information to the display device. | 07-28-2011 |
20110185205 | POWER-SAVING DISPLAY INFORMATION CONVERTING SYSTEM AND METHOD - Display information to be displayed by a display device having a power consumption model is converted according to a power-saving conversion model and the power consumption model, such that the power consumption of the display device for displaying the converted display information is lower than that for displaying the original display information. | 07-28-2011 |
20130298159 | SYSTEM AND METHOD FOR ALLOCATING ADVERTISEMENTS - According to one exemplary embodiment of an advertisement allocating system, an image object marking and response element receives a TV program signal and then marks at least one object appearing in the TV program during a current time slot; a user element tallies all the users interested in the object, and collects all the feedback information from all the users on the TV program; based on an allowable advertisement set for the current time slot, an advertisement auto-matching element computes the correlation between each specific object and each advertisement of the allowable advertisement set, computes a score for each advertisement of the allowable advertisement set, and extracts an advertisement candidate group for broadcasting. | 11-07-2013 |