Jung, CA
Byoungsok Jung, Palo Alto, CA US
Patent application number | Description | Published |
---|---|---|
20130043170 | Microfluidic ultrasonic particle separators with engineered node locations and geometries - An ultrasonic microfluidic system includes a separation channel for conveying a sample fluid containing small particles and large particles, flowing substantially parallel, adjacent to a recovery fluid, with which it is in contact. An acoustic transducer produces an ultrasound standing wave, that generates a pressure field having at least one node of minimum pressure amplitude. An acoustic extension structure is located proximate to said separation channel for positioning said acoustic node off center in said acoustic area and concentrating the large particles in said recovery fluid stream. | 02-21-2013 |
20140216992 | MICROFLUIDIC ULTRASONIC PARTICLE SEPARATORS WITH ENGINEERED NODE LOCATIONS AND GEOMETRIES - An ultrasonic microfluidic system includes a separation channel for conveying a sample fluid containing small particles and large particles, flowing substantially parallel, adjacent to a recovery fluid, with which it is in contact. An acoustic transducer produces an ultrasound standing wave, that generates a pressure field having at least one node of minimum, pressure amplitude. An acoustic extension structure is located proximate to said separation channel for positioning said acoustic node off center in said acoustic area and concentrating the large particles in said recovery fluid stream. | 08-07-2014 |
Byoungsok Jung, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20110036718 | METHODS FOR SEPARATING PARTICLES AND/OR NUCLEIC ACIDS USING ISOTACHOPHORESIS - According to one embodiment, a method includes co-feeding fluids comprising a leading electrolyte, a trailing electrolyte, and at least one of DNA and RNA to a channel, and applying an electric field to the fluids in a direction perpendicular to an axis of the channel for inducing transverse isotachophoresis. In another embodiment, a method includes co-feeding fluids to a channel. The fluids include a leading electrolyte, a trailing electrolyte, biological objects, at least one of DNA and RNA, and a spacer electrolyte having an electrophoretic mobility that is between an electrophoretic mobility of at least some of the biological objects and an electrophoretic mobility of the at least one of the DNA and the RNA. The method also includes applying an electric field to the fluids in a direction perpendicular to an axis of the channel for inducing transverse isotachophoresis. Other methods of isotachophoresis are disclosed in addition to these. | 02-17-2011 |
20120228141 | LIQUID AND GEL ELECTRODES FOR TRANSVERSE FREE FLOW ELECTROPHORESIS - The present invention provides a mechanism for separating or isolating charged particles under the influence of an electric field without metal electrodes being in direct contact with the sample solution. The metal electrodes normally in contact with the sample are replaced with high conductivity fluid electrodes situated parallel and adjacent to the sample. When the fluid electrodes transmit the electric field across the sample, particles within the sample migrate according to their electrophoretic mobility. | 09-13-2012 |
Cecile Jung, Pasadena, CA US
Patent application number | Description | Published |
---|---|---|
20130229210 | ON-CHIP POWER-COMBINING FOR HIGH-POWER SCHOTTKY DIODE BASED FREQUENCY MULTIPLIERS - A novel MMIC on-chip power-combined frequency multiplier device and a method of fabricating the same, comprising two or more multiplying structures integrated on a single chip, wherein each of the integrated multiplying structures are electrically identical and each of the multiplying structures include one input antenna (E-probe) for receiving an input signal in the millimeter-wave, submillimeter-wave or terahertz frequency range inputted on the chip, a stripline based input matching network electrically connecting the input antennas to two or more Schottky diodes in a balanced configuration, two or more Schottky diodes that are used as nonlinear semiconductor devices to generate harmonics out of the input signal and produce the multiplied output signal, stripline based output matching networks for transmitting the output signal from the Schottky diodes to an output antenna, and an output antenna (E-probe) for transmitting the output signal off the chip into the output waveguide transmission line. | 09-05-2013 |
Changho Jung, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20100052763 | CMOS Level Shifter Circuit Design - A level shifting circuit has a pair of assist circuits. The level shifting circuit includes an input point, an output point, a pair of cross-coupled PMOS transistors coupled to the output point, and a pair of NMOS transistors coupled between the input and output points. Each assist circuit includes a pair of PMOS transistors, one responsive to an input applied to the input point, the other responsive to the drain voltage of one of the NMOS transistors. The assist circuits temporarily weaken the cross-coupled PMOS transistors when an input changes from low to high, or from high to low. The assist circuits also transiently boost the output. | 03-04-2010 |
20100061161 | Self Reset Clock Buffer In Memory Devices - A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal. | 03-11-2010 |
20100142300 | Semiconductor Memory Device And Methods Of Performing A Stress Test On The Semiconductor Memory Device - A semiconductor memory device and method of performing a stress test on a semiconductor memory device are provided. In an example, the semiconductor memory device includes a multiplexer arrangement configured to switch a timing signal that controls an internal timing of the semiconductor memory device from an internal signal to an external signal during a stress mode, and further includes one or more word lines of the semiconductor memory device receiving a stress voltage during the stress mode, a duration of the stress mode based upon the external signal. In another example, the semiconductor memory device includes one or more word lines configured to receive a stress voltage during a stress mode, and a precharge circuit configured to provide a precharge voltage to a bit line of the semiconductor memory device during the stress mode. | 06-10-2010 |
20100226191 | Leakage Reduction in Memory Devices - A memory device includes a core array that includes memory cells. The memory device also includes a headswitch coupled to the core array and a positive supply voltage. The headswitch reduces leakage current from the core array by disconnecting the core array from the positive supply voltage. Additionally, head switches are added for pre-charge devices to further reduce leakage current. | 09-09-2010 |
20100238756 | Self Reset Clock Buffer In Memory Devices - A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal. | 09-23-2010 |
20110051537 | Address Multiplexing in Pseudo-Dual Port Memory - A pseudo-dual port memory address multiplexing system includes a control circuit operative to identify a read request and a write request to be accomplished during a single clock cycle. A self time tracking circuit monitors a read operation and generates a switching signal when the read operation is determined to be complete. A multiplexer is responsive to the switching signal for selectively providing a read address and a write address to a memory address unit at the proper time. | 03-03-2011 |
20110188328 | Systems and Methods for Writing to Multiple Port Memory Circuits - A multiple-port RAM circuit has a data-in line coupled to multiple bit lines and multiple bit line bars. The circuit also has multiple word lines. A memory cell is coupled to the bit lines, bit line bars, and word lines. The circuit further includes a controller than enables the word lines to substantially simultaneously write a value from the bit lines to the memory cell. | 08-04-2011 |
20130223176 | MEMORY PRE-DECODER CIRCUITS EMPLOYING PULSE LATCH(ES) FOR REDUCING MEMORY ACCESS TIMES, AND RELATED SYSTEMS AND METHODS - Memory pre-decoder circuits employing pulse latch(es) for reducing memory access times, and related systems and methods are disclosed. In one embodiment, the memory pre-decoder circuit includes a memory pre-decoder configured to pre-decode a memory address input within a memory pre-decode setup path to generate a pre-decoded memory address input. Additionally, a pulse latch is provided in the memory pre-decoder circuit outside of the memory pre-decode setup path. The pulse latch samples the pre-decoded memory address input based on a clock signal and generates a pre-decoded memory address output. As such, the memory pre-decode setup path sets up the pre-decoded memory address input prior to the clock signal for the pulse latch. In this manner, the pulse latch is configured to generate a pre-decoded memory address output without increasing setup times in the memory pre-decode setup path. | 08-29-2013 |
20130223178 | GLOBAL RESET WITH REPLICA FOR PULSE LATCH PRE-DECODERS - A global reset generation method for a pulse latch based pre-decoders in memories that comprises generating a pre-decoded memory address output for a pulse latch circuit, generating a reset signal to reset the pulse latch circuit, providing a combined signal of the pre-decoded memory address output and the reset signal, feeding the combined signal into a low voltage threshold device to manipulate resetting the pulse latch circuit, wherein generating a reset signal comprises generating a reset signal from a matched circuit that is configured to mimic the function of the latch circuit to be reset and wherein generating a reset signal comprises configuring the matched circuit to accommodate a worst case hold pulse delay to allow for resetting the pulse latch before a new clock cycle performs the resetting and having the matched circuit provide the reset signal and a pre-decoded memory address output in the same voltage domain. | 08-29-2013 |
20140112061 | WRITE WORD-LINE ASSIST CIRCUITRY FOR A BYTE-WRITEABLE MEMORY - A write-assisted memory. The write-assisted memory includes a word-line decoder that is implemented within a low VDD power domain. The write-assisted memory also includes a write-segment controller that is partially implemented within the low VDD power domain and is partially implemented within a high VDD power domain. The write-assisted memory further includes a local write word-line decoder that is implemented within the high VDD power domain. | 04-24-2014 |
20140177310 | PSEUDO-NOR CELL FOR TERNARY CONTENT ADDRESSABLE MEMORY - A method within a ternary content addressable memory (TCAM) includes receiving a match line output from a previous TCAM stage at a gate of a pull-up transistor of a current TCAM stage and at a gate of a pull-down transistor of the current TCAM stage. The method sets a match line bar at the current TCAM stage to a low value, via the pull-down transistor, when the match line output from the previous TCAM stage indicates a mismatch. The method also sets the match line bar at the current TCAM stage to a high value, via the pull-up transistor, when the match line output from the previous TCAM stage indicates a match. | 06-26-2014 |
20140185348 | HYBRID TERNARY CONTENT ADDRESSABLE MEMORY - A method within a hybrid ternary content addressable memory (TCAM) includes comparing a first portion of a search word to a first portion of a stored word in a first TCAM stage. The method further includes interfacing an output of the first TCAM stage to an input of the second TCAM stage. The method also includes comparing a second portion of the search word to a second portion of the stored word in a second TCAM stage when the first portion of the search word matches the first portion of the stored word. The first TCAM stage is different from the second TCAM stage. | 07-03-2014 |
20140185349 | STATIC NAND CELL FOR TERNARY CONTENT ADDRESSABLE MEMORY (TCAM) - A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor. | 07-03-2014 |
20140198598 | SYSTEM AND METHOD OF PERFORMING POWER ON RESET FOR MEMORY ARRAY CIRCUITS - The disclosure relates to an apparatus for deactivating one or more predecoded address lines of a memory circuit in response to one or more of the predecoded address lines being activated upon powering on of at least a portion of the apparatus. In particular, the apparatus includes a memory device; an address predecoder configured to activate one or more of a plurality of predecoded address lines based on an input address, wherein the plurality of predecoded address lines are coupled to the memory device for accessing one or more memory cells associated with the one or more activated predecoded address lines; and a power-on-reset circuit configured to deactivate one or more of the predecoded address lines in response to the one or more of the predecoded address lines being activated upon powering on the at least portion of the apparatus. | 07-17-2014 |
20140219039 | WRITE DRIVER FOR WRITE ASSISTANCE IN MEMORY DEVICE - A write assist driver circuit is provided that assists a memory cell (e.g., volatile memory bit cell) in write operations to keep the voltage at the memory core sufficiently high for correct write operations, even when the supply voltage is lowered. The write assist driver circuit may be configured to provide a memory supply voltage VddM to a bit cell core during a standby mode of operation. In a write mode of operation, the write assist driver circuit may provide a lowered memory supply voltage VddM | 08-07-2014 |
20140253201 | PULSE GENERATION IN DUAL SUPPLY SYSTEMS - Various apparatuses and methods are disclosed. The system describes a pulse generator comprising a first stage configured to be powered by a first voltage; and a second stage configured to be powered by a second voltage different from the first voltage, wherein the second stage is further configured to generate a pulse in response to an input to the first stage comprising a trigger and feedback from the second stage. | 09-11-2014 |
20140254293 | HIGH-SPEED MEMORY WRITE DRIVER CIRCUIT WITH VOLTAGE LEVEL SHIFTING FEATURES - Various aspects of a fast, energy efficient write driver capable of efficient operation in a dual-voltage domain memory architecture are provided herein. Specifically, various aspects of the write driver described herein combine a high speed driver with voltage level shifting capabilities that may be implemented efficiently in reducing use of silicon area while using lower power. The write driver circuit shifts or adjusts voltage levels between a first voltage domain to a second voltage domain. In one example, the write driver circuit is coupled to a global write bitline and a local write bitline that is coupled to one or more bitcells (of SRAM memory). The write driver circuit converts a first voltage level at the global write bitline to a second voltage level at the local write bitline during a write operation. | 09-11-2014 |
20140269112 | APPARATUS AND METHOD FOR WRITING DATA TO MEMORY ARRAY CIRCUITS - A write driver for a memory circuit includes a control circuit configured to: operate a first push-pull driver to generate a first drive signal in a first voltage domain at a first node based on an input signal in a second domain and in response to a mode select signal being in a first mode, wherein the first drive signal is at a same logic level as the input signal; operate a second push-pull driver to generate a second drive signal in the first voltage domain at a second node based on the input signal and in response to the mode select signal being in the first mode, wherein the second drive signal is at a complement logic level with respect to the input signal; and operate the first and second push-pull drivers to float the first and second nodes in response to the mode select signal being in a second mode. | 09-18-2014 |
20140355365 | PULSE GENERATOR - Various circuits and methods of operating circuits are disclosed. A circuit may include a pulse generator and a latch having an output configured to trigger the pulse generator, wherein the latch is configured to be set by an input signal and reset by feedback from the pulse generator. A method may include resetting a latch using feedback from a pulse generator by setting a latch using an input signal, triggering a pulse generator using an output from the latch, and resetting the latch using feedback from the pulse generator. | 12-04-2014 |
20150029782 | WIDE RANGE MULTIPORT BITCELL - A multiport bitcell including a pair of cross-coupled inverters is provided with increased write speed and enhanced operating voltage range by the selective isolation of a first one of the cross-coupled inverters from a power supply and ground during a write operation. The write operation occurs through a write port that includes a transmission gate configured to couple a first node driven by the first cross-coupled inverter to a write bit line. A remaining second cross-coupled inverter in the bitcell is configured to drive a second node that couples to a plurality of read ports. | 01-29-2015 |
20150067290 | MEMORY ACCESS TIME TRACKING IN DUAL-RAIL SYSTEMS - Disclosed are various apparatuses and methods for memory access time tracking in dual-rail systems. An apparatus may include a memory coupled to a first voltage rail and having a data output, a data circuit coupled to a second voltage rail and configured to receive the data output from the memory, and a timing circuit configured to adjust an access time of the memory based on a second voltage rail level. A method may include determining a voltage rail level of a data circuit, adjusting the access time of the memory based on the voltage rail level of the data circuit, outputting data from the memory, and receiving the output data by the data circuit. | 03-05-2015 |
20150085554 | STATIC NAND CELL FOR TERNARY CONTENT ADDRESSABLE MEMORY (TCAM) - A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor. | 03-26-2015 |
Chan Woo Jung, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20110063330 | METHOD AND APPARATUS FOR REDUCING ERRONEOUS COLOR EFFECTS IN A FIELD SEQUENTIAL LIQUID CRYSTAL DISPLAY - Methods and apparatuses for reducing an erroneous color effect in a field-sequential liquid crystal display (FSLCD) are disclosed. An apparatus for reducing the erroneous color effect may include a data response time compensation (RTC) block which uses an RTC lookup table to provide a fast transition response time from one gray level to another gray level for a liquid crystal pixel cell by using a response time compensation (RTC) scheme during a color LED backlighting sequence. The apparatus may also include a VCOM and Gamma reference control block to generate a voltage boost and provide boost control to the liquid crystal pixel cell in a FSLCD panel, wherein the voltage boost gives a fast gray level transition to remove residual color caused by a slow transition time between liquid crystal light transmittance levels for the liquid crystal pixel cell. | 03-17-2011 |
Christopher Jung, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20130159456 | THERAPY MANAGEMENT SYSTEM - Stored data is accessed over a computer network through a network data manager. Data may be stored and transferred to the network data manager from a product device using an uploader application. In one aspect, a request message containing an access request or identifier is received at the network data manager from a client device for access to a data storage facility. If the network data manager determines the access requestor identifier is associated with a data record that identifies a product device having a registration record, the network data manager transmits a data link to the client device to provide access to the data record by the client device over the computer network. | 06-20-2013 |
Christopher C. Jung, Mission Viejo, CA US
Patent application number | Description | Published |
---|---|---|
20090082794 | Simultaneous Proportional Control of Surgical Parameters in a Microsurgical System - A microsurgical system, and a foot controller for the improved operation of a microsurgical system, are disclosed. A surgeon may use the foot controller to simultaneously control multiple surgical parameters based upon movement of a foot pedal of the foot controller in a single plane of motion. | 03-26-2009 |
20140005488 | HYDRAULIC SYSTEM FOR SURGICAL APPLICATIONS | 01-02-2014 |
Christopher C. Jung, Mission Viego, CA US
Patent application number | Description | Published |
---|---|---|
20110301425 | Inductive Task Light For Surgical Console - A task light system for a surgical console includes a task light that can be held to a coupling location on a surgical console. The task light has an inductive coupling, a light source, and a goose neck connecting the light source to the inductive coupling. The coupling location is located on a face of the surgical console. The coupling location is configured to magnetically attract and hold the inductive coupling. The face of the surgical console where the coupling location is located is a continuous surface. | 12-08-2011 |
Cynthia M. Jung, Menlo Park, CA US
Patent application number | Description | Published |
---|---|---|
20090154340 | FAST OSPF INACTIVE ROUTER DETECTION - A fast OSPF inactive router detection technique is provided that detects the failure of a router and switches routing to an alternate router. The alternate router provides a message to the other routers in the Wide Area Network (LAN) that informs of the router failure. | 06-18-2009 |
20090158040 | METHOD AND SYSTEM FOR SECURE EXCHANGE OF DATA IN A NETWORK - A first network device implements a method for the secure exchange of data in a network. The network also includes a second network device and a remote device. The method includes establishing an indirect path to the remote device and pre-negotiating first security parameters with the remote device over the indirect path using a network layer protocol, when the second network device has an active first data link. The method further includes establishing an active second data link with the remote device and exchanging first data with the remote device over the active second data link using the first security parameters, when the first data link becomes inactive. | 06-18-2009 |
David Hann Jung, Fremont, CA US
Patent application number | Description | Published |
---|---|---|
20120127118 | TOUCH SENSOR HAVING IMPROVED EDGE RESPONSE - A sensor is provided. The sensor includes a planar sensing area including a sensor layout. The sensor layout includes an interior portion, an edge portion, and edges. The sensor layout also includes interior sensing elements, the interior sensing elements being located in the interior portion, and edge sensing elements, the edge sensing elements being located in the edge portion. The interior sensing elements are arranged in the sensor layout such that the interior sensing elements generally do not extend beyond a predetermined distance from the edges. Moreover, the edge sensing elements are arranged to extend beyond the predetermined distance and interlace with the interior sensing elements in the interior portion. The sensor further includes a controller and a connector, the connector coupling the planar sensing area to the controller. | 05-24-2012 |
20120127130 | PROPORTIONAL AREA WEIGHTED SENSOR FOR TWO-DIMENSIONAL LOCATIONS ON A TOUCH SCREEN - A touch sensor is provided including a controller and a planar layout having an edge and an interior portion. Further including a connector coupling the touch controller to the layout; a substrate made of a first material; and sensing elements made of a second material formed on the substrate and covering the layout without overlapping. Sensing elements have non-monotonic widths from the center along two perpendicular directions, and a centroid. The touch sensor including pass-through traces to couple edge to interior portions to determine two-dimensional locations for touches using a weighting that is proportional to an overlap area of the sensor elements and their centroids. The substrate may be made of a dielectric and the sensing elements made of a conductor. A method for using a controller circuit having a memory to store centroid locations and determine a two-dimensional location on a touch screen as above is also provided. | 05-24-2012 |
20120127131 | METHOD TO IMPROVE PERFORMANCE OF A PROPORTIONAL AREA WEIGHTED SENSOR FOR TWO-DIMENSIONAL LOCATIONS ON A TOUCH SCREEN - An electronic appliance including a processor and a computer-readable medium, having instructions for execution by a processor is provided. The instructions causing the processor to perform methods to obtain an error map for locations in a touch sensor. The method including inputting a geometry for a touch sensor layout; inputting coordinates for centroids of sensing elements in the touch sensor layout; and inputting a touch geometry. The method includes the steps of selecting a plurality of test points on the touch sensor layout; generating, a calculated touch location for each of the plurality of test points; and an error map from the calculated touch locations and the test points. The method may include generating an error measure from the error map; displaying, the generated error map and the generated error measure; and adjusting the geometry for the touch sensor layout if the error measure is larger than a tolerance value. | 05-24-2012 |
20150084583 | CONTROL OF WIRELESS BATTERY CHARGING - One embodiment provides a method to store electrical energy in an electronic device, which has a central processing unit (CPU) to provide operating-system and application processing in the device. The method includes controlling, from the CPU of the electronic device, communication sent from the device and received at a wireless charger within communication range of the device. The method further includes computing, in the CPU of the electronic device, a set-point condition for wireless energy flow from the wireless charger to an energy-storage component of the device, and regulating the wireless energy flow based on the set-point condition. | 03-26-2015 |
Dawoon Jung, La Jolla, CA US
Patent application number | Description | Published |
---|---|---|
20090131474 | SCREENING METHODS FOR PROTEIN KINASE B INHIBITORS EMPLOYING VIRTUAL DOCKING APPROACHES AND COMPOUNDS AND COMPOSITIONS DISCOVERED THEREBY - The present invention describes an improved method for screening compounds for activity in inhibiting the enzymatic activity of Akt1 protein kinase, also known as Protein Kinase B, an enzyme that is believed to play a key role in the inhibition of apoptosis and thus in the etiology of cancer and other conditions, including neurodegenerative diseases. In general, the method comprises: (1) providing a plurality of compounds suspected of having Akt1 kinase inhibitory activity; (2) modeling the docking of each of the plurality of the compounds with a target binding site derived from the crystal structure of a ternary complex involving Akt1, a nonhydrolyzable ATP analogue, and a peptide substrate derived from a physiological AKT substrate such that the protein active site is defined including those residues within a defined distance from the nonhydrolyzable ATP analogue; (3) ranking the docked compounds by goodness of fit; (4) further selecting compounds from compounds high ranked by goodness of fit in docking by using one or more screening criteria; (5) optionally, visually analyzing structures of compounds selected in step (4) to remove any compounds with improbable docking geometry; and (6) experimentally testing the selected compounds from step (4) or step (5), if step (5) is performed, to determine their inhibitory activity against Akt1 in order to select compounds with Akt1 inhibitory activity. The invention also encompasses pharmaceutical compositions including compounds whose inhibitory activity against Akt1 is discovered by the screening method, as well as methods of use of the pharmaceutical compositions to treat cancer and other conditions. | 05-21-2009 |
Donald Jung, Cupertino, CA US
Patent application number | Description | Published |
---|---|---|
20100183742 | PHOSPHORAMIDATE ALKYLATOR PRODRUGS FOR THE TREATMENT OF CANCER - Compositions containing, and, methods administering, TH302, are useful in treatment of cancer and other hyper-proliferative diseases. | 07-22-2010 |
Dong Ha Jung, Pleasanton, CA US
Patent application number | Description | Published |
---|---|---|
20130267042 | MRAM Fabrication Method with Sidewall Cleaning - Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described. | 10-10-2013 |
20130334633 | Magnetic Tunnel Junction With Non-Metallic Layer Adjacent to Free Layer - A spin transfer torque magnetic random access memory (STTMRAM) magnetic tunnel junction (MTJ) stack includes layers to which when electric current is applied cause switching of the direction of magnetization of at least one of the layer. The STTMRAM MTJ stack includes a reference layer (RL) with a direction of magnetization that is fixed upon manufacturing of the STTMRAM MTJ stack, a junction layer (JL) formed on top of the RL, a free layer (FL) formed on top of the JL. The FL has a direction of magnetization that is switchable relative to that of the RL upon the flow of electric current through the spin transfer torque magnetic random access memory (STTMRAM) magnetic tunnel junction (MTJ) stack. The STTMRAM MTJ stack further includes a spin confinement layer (SCL) formed on top of the FL, the SCL made of ruthenium. | 12-19-2013 |
20130341801 | Redeposition Control in MRAM Fabrication Process - Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode. | 12-26-2013 |
20140042567 | MTJ MRAM WITH STUD PATTERNING - Use of a multilayer etching mask that includes a stud mask and a removable spacer sleeve for MTJ etching to form a bottom electrode that is wider than the rest of the MTJ pillar is described. The first embodiment of the invention described includes a top electrode and a stud mask. In the second and third embodiments the stud mask is a conductive material and also serves as the top electrode. In embodiments after the stud mask is formed a spacer sleeve is formed around it to initially increase the masking width for a phase of etching. The spacer is removed for further etching, to create step structures that are progressively transferred down into the layers forming the MTJ pillar. In one embodiment the spacer sleeve is formed by net polymer deposition during an etching phase. | 02-13-2014 |
20140138609 | HIGH DENSITY RESISTIVE MEMORY HAVING A VERTICAL DUAL CHANNEL TRANSISTOR - Resistive memory cell array fabricated with unit areas able to be scaled down to 4 F | 05-22-2014 |
20140170776 | MTJ STACK AND BOTTOM ELECTRODE PATTERNING PROCESS WITH ION BEAM ETCHING USING A SINGLE MASK - Fabrication methods using Ion Beam Etching (IBE) for MRAM cell memory elements are described. In embodiments of the invention the top electrode and MTJ main body are etched with one mask using reactive etching such as RIE or magnetized inductively coupled plasma (MICP) for improved selectivity, then the bottom electrode is etched using IBE as specified in various alternative embodiments which include selection of incident angles, wafer rotational rate profiles and optional passivation layer deposited prior to the IBE. The IBE according to the invention etches the bottom electrode without the need for an additional mask by using the layer stack created by the first etching phase as the mask. This makes the bottom electrode self-aligned to MTJ. The IBE also achieves MTJ sidewall cleaning without the need for an additional step. | 06-19-2014 |
20150014800 | MTJ MEMORY CELL WITH PROTECTION SLEEVE AND METHOD FOR MAKING SAME - Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment of the present invention as applied to a memory cell comprises a top electrode layer, an upper magnetic layer, a barrier layer, a lower magnetic layer and a bottom electrode layer in a pillar formed on a landing pad; and a sleeve of dielectric material generally surrounding sidewalls of at least the barrier layer and the lower magnetic layer and partially surrounding the bottom electrode layer. The bottom electrode layer includes a ledge that extends under the sleeve of dielectric material and separates the sleeve of dielectric material from the landing pad under the bottom electrode layer. | 01-15-2015 |
20150014801 | Redeposition Control in MRAM Fabrication Process - Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode. | 01-15-2015 |
Dz-Mou Jung, Arcadia, CA US
Patent application number | Description | Published |
---|---|---|
20110191167 | SYSTEM AND METHOD FOR EXPLORING NEW SPONSORED SEARCH LISTINGS OF UNCERTAIN QUALITY - According to some example embodiments, a method includes calculating learning values associated with a plurality of listings, at least one of said learning values associated with one of said listings representing a value based, at least in part, on a probability distribution of selections of said listing. The method further includes applying said learning values to ranking scores associated with said listings to provide an updated ranking, and electronically auctioning advertising inventory to purchasers associated with said listings based, at least in part, on said updated ranking. | 08-04-2011 |
Gun Young Jung, Gwangju Si, CA US
Patent application number | Description | Published |
---|---|---|
20090159567 | POLYMER SOLUTION FOR NANOIMPRINT LITHOGRAPHY TO REDUCE IMPRINT TEMPERATURE AND PRESSURE - An improved method of forming features on substrates by imprinting is provided. In the method, a polymer solution that contains at least one polymer dissolved in at least one polymerizable monomer and the polymer solution is deposited on the substrate to form a liquid film thereon. Further, the liquid film is cured by causing the at least one monomer to polymerize and optionally cross-linking the at least one polymer to thereby form a polymer film, the polymer film having a glass transition temperature of less than 100° C., and the polymer film is imprinted with a mold having a desired pattern to form a corresponding negative pattern in the polymer film. Alternatively, the liquid film is imprinted with the mold and the liquid film is cured in the presence of the mold to form the polymer film with the negative pattern. | 06-25-2009 |
Hee Joon Jung, Palo Alto, CA US
Patent application number | Description | Published |
---|---|---|
20110269298 | Irradiation assisted nucleation of quantum confinements by atomic layer deposition - A method of fabricating quantum confinements is provided. The method includes depositing, using a deposition apparatus, a material layer on a substrate, where the depositing includes irradiating the layer, before a cycle, during a cycle, and/or after a cycle of the deposition to alter nucleation of quantum confinements in the material layer to control a size and/or a shape of the quantum confinements. The quantum confinements can include quantum wells, nanowires, or quantum dots. The irradiation can be in-situ or ex-situ with respect to the deposition apparatus. The irradiation can include irradiation by photons, electrons, or ions. The deposition is can include atomic layer deposition, chemical vapor deposition, MOCVD, molecular beam epitaxy, evaporation, sputtering, or pulsed-laser deposition. | 11-03-2011 |
20130149860 | Metal Silicide Nanowire Arrays for Anti-Reflective Electrodes in Photovoltaics - A method of fabricating single-crystalline metal silicide nanowires for anti-reflective electrodes for photovoltaics is provided that includes exposing a surface of a metal foil to oxygen or hydrogen at an elevated temperature, and growing metal silicide nanowires on the metal foil surface by flowing a silane gas mixture over the metal foil surface at the elevated temperature, where spontaneous growth of the metal silicide nanowires occur on the metal foil surface, where the metal silicide nanowires are post treated for use as an electrode in a photovoltaic cell or used directly as the electrode in the photovoltaic cell. | 06-13-2013 |
20140093654 | Irradiation Assisted Nucleation of Quantum Confinements by Atomic Layer Deposition - A method of fabricating quantum confinements is provided. The method includes depositing, using a deposition apparatus, a material layer on a substrate, where the depositing includes irradiating the layer, before a cycle, during a cycle, and/or after a cycle of the deposition to alter nucleation of quantum confinements in the material layer to control a size and/or a shape of the quantum confinements. The quantum confinements can include quantum wells, nanowires, or quantum dots. The irradiation can be in-situ or ex-situ with respect to the deposition apparatus. The irradiation can include irradiation by photons, electrons, or ions. The deposition is can include atomic layer deposition, chemical vapor deposition, MOCVD, molecular beam epitaxy, evaporation, sputtering, or pulsed-laser deposition. | 04-03-2014 |
Hong-Sik Jung, Pleasanton, CA US
Patent application number | Description | Published |
---|---|---|
20100035085 | PERPENDICULAR MAGNETIC RECORDING MEDIUM WITH IMPROVED MAGNETIC ANISOTROPY FIELD - A perpendicular magnetic recording medium comprising a substrate, a soft underlayer, a seed layer, a non-magnetic FCC NiW alloy underlayer, a non-magnetic HCP underlayer, and a magnetic layer. We have discovered that the combination of a seed layer comprising Ta and a NiW alloy underlayer uniquely improves media recording performance and thermal stability by achieving excellent coercivity of the thin bottom magnetic recording layer and narrow C axis orientation distribution. | 02-11-2010 |
Hwisung Jung, Irvine, CA US
Patent application number | Description | Published |
---|---|---|
20130046967 | Proactive Power Management Using a Power Management Unit - Embodiments of the present disclosure provide systems and methods for proactively managing power in a device. A power management unit (PMU) receives information from various subsystems of a device and estimates the total power required by each subsystem of the device. Based on this information, the PMU can predict power requirements for a particular subsystem or for one or more application(s) to execute. Based on this prediction, the PMU can reconfigure the subsystems so that the device executes more efficiently given the current battery life of the device. Proactive power management advantageously gives the PMU the capability to predict power needs of various subsystems of a device so that the power supplied to these subsystems can be managed in an intelligent way before battery resources are exhausted. | 02-21-2013 |
20130046999 | Semiconductor Device Predictive Dynamic Thermal Management - A semiconductor device includes a memory storing a lookup table including stored values associated with modes of operation of a component of the semiconductor device. A monitor monitors an operating parameter of the component in real-time, and reports a calculated value associated with the same. A power manager determines a change in the mode of operation of the component based on a comparison of the calculated value with a corresponding stored value, and adjusts a current mode of operation of the component in real-time. | 02-21-2013 |
20130047012 | Apparatus and Method for Entering Low Power Mode Based on Process, Voltage, and Temperature Considerations - A processor arrangement changes its default time interval for entering a power saving mode based sensed operating conditions and predetermined time intervals to be used under various operating conditions to optimize power saving. | 02-21-2013 |
20130047166 | Systems and Methods for Distributing an Aging Burden Among Processor Cores - Systems and methods are presented for reducing the impact of high load and aging on processor cores in a processor. A Power Management Unit (PMU) can monitor aging, temperature, and increased load on the processor cores. The PMU instructs the processor to take action such that aging, temperature, and/or increased load are approximately evenly distributed across the processor cores, so that the processor can continue to efficiently process instructions. | 02-21-2013 |
20130305068 | Leakage Variation Aware Power Management For Multicore Processors - A system and method are provided to improve power efficiency of processor cores, such as processor cores in a multicore processor. A break-even time of a processor core may be determined that affects which power saving mode a processor core should enter when an expected idle of the processor core is identified. The break-even time of the processor core may be determined during run-time to help determine an applicable power saving mode that improves power efficiency of the processor core. | 11-14-2013 |
20140032010 | System and Method for Supervised Thermal Management - System and method for incrementally varying input levels and recording respective output temperatures at the varied levels, storing, in a training table, first correlations between the varied levels of the input parameter and defined temperature ranges, detecting an input parameter level during operation and re-recording the output temperature at the detected level, generating a second correlation between the detected level and a second temperature range, determining whether the second temperature range is different from a first temperature range from among the defined temperature ranges, the first temperature range correlating to the level of the input parameter corresponding to the detected level, updating the training table when the second temperature range is different from the first temperature range, predicting an expected temperature range, and dynamically scaling, based on the expected temperature range, the detected level of the input parameter to control the output temperature in real-time. | 01-30-2014 |
20140215242 | Wearable Device-Aware Supervised Power Management for Mobile Platforms - Methods, systems, and computer program products are provided for supervised power management between a primary platform and a secondary platform. Communication between a primary platform and a secondary platform is established. An application running on the secondary platform is captured. Input features and output measures are collected to build a training set for the application, wherein the input features are collected through direct measurement and the output measures reflect characteristics of the application. Based on the training set, power consumption of the secondary platform with an expected performance level is predicted for a new application running on the secondary platform. Accordingly, an optimal power management policy is derived that minimizes the total power consumption of the primary and secondary platforms. | 07-31-2014 |
Jae Jung, Cupertino, CA US
Patent application number | Description | Published |
---|---|---|
20130038437 | SYSTEM FOR TASK AND NOTIFICATION HANDLING IN A CONNECTED CAR - The vehicular notification and control apparatus receives user input via a multimodal control system, optionally including touch-responsive control and non-contact gestural and speech control. A processor-controlled display provides visual notifications of notifications and tasks according to a dynamically prioritized queue which takes into account environmental conditions and driving context and available driver attention. The display is filtered to present only valid notifications and tasks for the current available driver attention level. Driver attention is determined using multiple, diverse sensors integrated through a sensor fusion mechanism. | 02-14-2013 |
Jae Jung, Glendale, CA US
Patent application number | Description | Published |
---|---|---|
20130287792 | COMPOSITIONS AND METHODS TO BLOCK MTB-MEDIATED EVASION - Method and compositions are disclosed for inhibiting Mtb-mediated evasion of host immunity or treating a disease or condition caused by Mtb infection in subject or patient, administering an effective amount of a molecular inhibitor, an isolated Mtb EIS peptide, polynucleotide encoding an Mtb EIS peptide, an EIS polynucleotide, or biological equivalents of each thereto. | 10-31-2013 |
20140073585 | PEPTIDE INHIBITORS OF HAUSP DEUBIQUITINASE - Two vIRF4 (Kaposi's-sarcoma-associated-herpesvirus vIRF4) peptides, vif1, corresponding to aa202-216 of vIRF4, and vif2, corresponding to aa220-236 of vIRF4, are potent and selective HAUSP antagonists. The vif1 and vif2 peptides robustly suppress HAUSP DUB enzymatic activity, ultimately leading to p53-mediated anti-cancer activity. The vif1 and vif2 peptides, along with their homologues, are useful in treating ALL. | 03-13-2014 |
Jaeho Jung, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20090047737 | Human LY6-Big Molecules and Methods of Use - The present invention is directed to human Ly6-BIG molecules and their use in diagnostic, prognostic, and treatment methods for colon, lung and other cancers, in preventing the reoccurrence of such cancers, and in diagnostic, prognostic, and treatment methods for autoimmune disorders and AIDS. | 02-19-2009 |
20120064080 | Human LY6-Big Molecules and Methods of Use - The present invention is directed to human Ly6-BIG molecules and their use in diagnostic, prognostic, and treatment methods for colon, lung and other cancers, in preventing the reoccurrence of such cancers, and in diagnostic, prognostic, and treatment methods for autoimmune disorders and AIDS. | 03-15-2012 |
Jae-Kyu Jung, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20090258892 | FUSED PYRAZOLE DERIVATIVES AND METHODS OF TREATMENT OF METABOLIC-RELATED DISORDERS THEREOF - The present invention relates to certain fused pyrazole derivatives of Formula (Ia), and pharmaceutically acceptable salts thereof, which exhibit useful pharmacological properties, for example, as agonists for the RUP25 receptor. | 10-15-2009 |
20110172209 | 3H-IMIDAZO[4,5-B]PYRIDIN-5-OL DERIVATIVES USEFUL IN THE TREATMENT OF GPR81 RECEPTOR DISORDERS - The present invention is directed to certain 3H-imidazo[4,5-b]pyridin-5-ol derivatives of Formula (Ia) and pharmaceutically acceptable salts thereof, which exhibit useful pharmacological properties, for example, as agonists of the GPR81 receptor. Also provided by the present invention are pharmaceutical compositions containing compounds of the invention, and methods of using the compounds and compositions of the invention in the treatment of GPR81 associated disorders, for example, dyslipidemia, atherosclerosis, atheromatous disease, hypertension, coronary heart disease, stroke, insulin resistance, impaired glucose tolerance, type 2 diabetes, syndrome X, obesity, psoriasis, rheumatoid arthritis, Crohn's disease, transplant rejection, multiple sclerosis, systemic lupus erythematosus, ulcerative colitis, type 1 diabetes and acne. | 07-14-2011 |
20120214766 | CANNABINOID RECEPTOR MODULATORS - The present invention relates to certain compounds of Formula Ia and pharmaceutical compositions thereof that modulate the activity of the cannabinoid CB2 receptor. The present invention further relates to certain compounds of Formula Ia and pharmaceutical compositions thereof that modulate the activities of both the CB1 receptor and the CB2 receptor. Compounds of the present invention and pharmaceutical compositions thereof are directed to methods useful in the treatment of: pain, for example bone and joint pain, muscle pain, dental pain, migraine and other headache pain, inflammatory pain, neuropathic pain, pain that occurs as an adverse effect of therapeutics and pain associated with osteoarthritis; hyperalgesia; allodynia; inflammatory hyperalgesia; neuropathic hyperalgesia; acute nociception; osteoporosis; multiple sclerosis-associated spasticity; autoimmune disorders; allergic reactions; CNS inflammation; atherosclerosis; undesired immune cell activity and inflammation; age-related macular degeneration; cough; leukemia; lymphoma; CNS tumors; prostate cancer; Alzheimer's disease; stroke-induced damage; dementia; amyotrophic lateral sclerosis, and Parkinson's disease. | 08-23-2012 |
20130165412 | CANNABINOID RECEPTOR MODULATORS - The present invention relates to certain compounds of Formula Ia and pharmaceutical compositions thereof that modulate the activity of the cannabinoid CB2 receptor. The present invention further relates to certain compounds of Formula Ia and pharmaceutical compositions thereof that modulate the activities of both the CB1 receptor and the CB2 receptor. Compounds of the present invention and pharmaceutical compositions thereof are directed to methods useful in the treatment of: pain, for example bone and joint pain, muscle pain, dental pain, migraine and other headache pain, inflammatory pain, neuropathic pain, pain that occurs as an adverse effect of therapeutics and pain associated with osteoarthritis; hyperalgesia; allodynia; inflammatory hyperalgesia; neuropathic hyperalgesia; acute nociception; osteoporosis; multiple sclerosis-associated spasticity; autoimmune disorders; allergic reactions; CNS inflammation; atherosclerosis; undesired immune cell activity and inflammation; age-related macular degeneration; cough; leukemia; lymphoma; CNS tumors; prostate cancer; Alzheimer's disease; stroke-induced damage; dementia; amyotrophic lateral sclerosis, and Parkinson's disease. | 06-27-2013 |
20140206649 | CANNABINOID RECEPTOR MODULATORS - Provided are certain methods useful in the treatment of pain comprising administering a compound of Formula Ia and pharmaceutical compositions thereof that modulate the activity of the cannabinoid CB | 07-24-2014 |
Jae U. Jung, Los Angeles, CA US
Patent application number | Description | Published |
---|---|---|
20110224133 | Highly Potent Peptides To Control Cancer And Neurodegenerative Diseases - This invention provides compositions and method of diminishing or inhibiting autophagy by administering a FLIP protein that binds to Atg3, interfering with the formation of the LC3-Atg4-Atg7-Atg3 conjugation complex necessary for autophagy induction. This invention also provides FLIP peptide fragments that promote or induce autophagy by interfering with the activity of FLIP. | 09-15-2011 |
20130316958 | HIGHLY POTENT PEPTIDES TO CONTROL CANCER AND NEURODEGENERATIVE DISEASES - This invention provides compositions and method of diminishing or inhibiting autophagy by administering a FLIP protein that binds to Atg3, interfering with the formation of the LC3-Atg4-Atg7-Atg3 conjugation complex necessary for autophagy induction. This invention also provides FLIP peptide fragments that promote or induce autophagy by interfering with the activity of FLIP. | 11-28-2013 |
Jaewoo Jung, Palo Alto, CA US
Patent application number | Description | Published |
---|---|---|
20090153567 | Systems and methods for generating personalized computer animation using game play data - Systems, methods, and computer storage media for generating a computer animation of a game. A custom animation platform receives game play data of the game and determines at least one scene based on the game play data. Then, one or more frames in the scene are set up, where at least one of the frames includes at least one non-game pre-production element of the game. Subsequently, the frames are rendered and the rendered frames are combined to generate a computer animation. | 06-18-2009 |
20090201298 | System and method for creating computer animation with graphical user interface featuring storyboards - Systems, methods, and computer readable media for customizing a computer animation. A custom animation platform prepares a storyboard including at least one customizable storyboard item and one or more replacement storyboard items configured to replace the customizable storyboard item. Then, the custom animation platform sends the storyboard and the replacement storyboard items to an interactive device via a network to thereby cause a user of the device to select one of the replacement storyboard items. The custom animation platform receives user data including the user's selection from the device and generates a computer animation based on the user data. | 08-13-2009 |
20100242069 | SYSTEM AND METHOD FOR CREATING PERSONALIZED ADVERTISEMENT AND PERSONALIZING PRODUCTS WITH INTERACTIVE GRAPHICAL USER INTERFACE EMBEDDED IN ADVERTISEMENT - Systems, methods, and computer storage media for creating a personalized advertisement. A web development platform prepares an interactive user interface including a personalization area; prepares an advertisement; embeds the user interface in the advertisement; and sends the advertisement with the embedded interactive user interface to a device via a network to thereby enable a user of the device to use the embedded interface for personalization of the personalization area. When the user uploads an image file to be displayed on the personalization area, the platform causes a process to produce a personalized video including the personalization area to thereby create a personalized advertisement and displays the personalized video on the device. | 09-23-2010 |
James Jung, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20100302153 | DEPRESSABLE TOUCH SENSOR - An input device and a method for providing an input device are provided. The input device assembly includes a base, a sensor support, and a scissor mechanism attached to the base and the sensor support. The scissor mechanism allows for only substantially uniform translation of the sensor support towards the base in response to a force biasing the sensor support substantially towards the base. | 12-02-2010 |
James (jinwha) Jung, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20090040191 | CAPACITIVE TOUCH SENSOR WITH CONDUCTIVE TRACE LINES IN BONDING REGION - Methods and apparatus are provided for a capacitive touch sensor including a circuit substrate (which may be a flexible substrate) having a touch sensor controller coupled to a plurality of contacts through a plurality of conductive traces. The contacts are formed on a first (bottom) side of the circuit substrate while the conductive traces are formed on a second (top) side of the circuit substrate, but are ohmically (electrically) coupled to the contacts through the use of conductive vias. This arrangement of conductive traces, vias and contacts allows the conductive traces to reside over the contacts and within the bonding region resulting in an improvement of over fifty percent in wasted space as compared to conventional touch sensors. | 02-12-2009 |
Jason Jung, Torrance, CA US
Patent application number | Description | Published |
---|---|---|
20090057307 | Foldable storage container - A foldable storage container can be used as a suitcase or to hold and transport sports balls and has a rear panel, two side panels, a base, a front panel and a cover. The rear panel has a top, a bottom and two side edges. The side panels are respectively formed perpendicularly on the side edges of the rear panel and are foldable. The base is mounted pivotally on the rear panel. The front panel is mounted slidably between the side panels and has a top. The cover is mounted pivotally and detachably on the top of the rear panel and is selectively locked on the top of the front panel. Therefore, the foldable storage container can be folded to occupy a smaller space for convenient storage. | 03-05-2009 |
20090095762 | STORAGE CONTAINER WITH RETRACTABLE STANDS - A storage container with retractable stands has a body and two stand assemblies. The body has a front surface, a rear surface and multiple slots. The slots are formed in the front and rear surfaces. Each stand assembly has multiple props. Each prop is mounted pivotally in a corresponding slot. The props are pivoted to stand on the ground to stand the storage container off the ground for increased convenience. When the props are held in the slots, the props are completely received in the slots to avoid additional storage volume. | 04-16-2009 |
Jay Jung, Sunnyvale, CA US
Patent application number | Description | Published |
---|---|---|
20100119420 | ABATEMENT SYSTEM HAVING ENHANCED EFFLUENT SCRUB AND MOISTURE CONTROL - Apparatus for improved treatment of effluents are provided herein. In some embodiments, an abatement system may include an exhaust conduit to flow an effluent stream therethrough; a plurality of packed beds disposed in the exhaust conduit to remove non-exhaustible effluents from the effluent stream; one or more spray jets to provide an effluent treating agent between adjacent packed beds, the effluent treating agent to remove non-exhaustible effluents from the effluent stream; and a dripper disposed in the exhaust conduit above an uppermost packed bed to provide the effluent treating agent in large droplets to wet and rinse particulate from an upper surface of the uppermost packed bed substantially without forming fine droplets. | 05-13-2010 |
Jeesung Jung, Campbell, CA US
Patent application number | Description | Published |
---|---|---|
20120267764 | BIPOLAR JUNCTION TRANSISTOR WITH LAYOUT CONTROLLED BASE AND ASSOCIATED METHODS OF MANUFACTURING - The present technology discloses a bipolar junction transistor (BJT) device integrated into a semiconductor substrate. The BJT device comprises a collector, a base and an emitter. The collector is of a first doping type on the substrate; the base is of a second doping type in the collector from the top surface of the semiconductor device and the base has a base depth; and the emitter is of a first doping type in the base from the top surface of the semiconductor device. The base depth is controlled by adjusting a layout width in forming the base. | 10-25-2012 |
20130040432 | METHODS OF MANUFACTURING LATERAL DIFFUSED MOS DEVICES WITH LAYOUT CONTROLLED BODY CURVATURE AND RELATED DEVICES - The present invention discloses a method of manufacturing an N-type LDMOS device. The method comprises forming a gate above the semiconductor substrate; forming a body, comprising forming a Pwell apart from the gate and forming a Pbase partly in the Pwell, wherein the Pbase is wider and shallower than the Pwell; and forming an N-type source and a drain contact region. Wherein the body curvature of the LDMOS device is controlled by adjusting the layout width of the Pwell. | 02-14-2013 |
Jeesung Jung, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20120244668 | SEMICONDUCTOR DEVICES WITH LAYOUT CONTROLLED CHANNEL AND ASSOCIATED PROCESSES OF MANUFACTURING - The present technology is directed generally to processes of forming semiconductor devices (e.g., JFET devices). The semiconductor device comprises a gate region, a source region, a drain region and a channel region having a channel size. The channel size is controlled by adjusting a layout width of the gate region. | 09-27-2012 |
20140024186 | METHOD FOR FORMING DUAL GATE INSULATION LAYERS AND SEMICONDUCTOR DEVICE HAVING DUAL GATE INSULATION LAYERS - Method of forming dual gate insulation layers and semiconductor device having dual gate insulation layers is disclosed. The method of forming dual gate insulation layers comprises forming a first thin layer of a thick gate insulation layer on a semiconductor substrate by oxidizing the semiconductor substrate, depositing a second thicker layer of the thick gate insulation layer on the first thin layer, removing a portion of the thick gate insulation layer to expose a surface area of the semiconductor substrate and forming a thin gate insulation layer on the exposed surface area of the semiconductor substrate. The method of forming dual gate insulation layers, when applied in fabricating semiconductor devices having dual gate insulation layers and trench isolation structures, may help to reduce a silicon stress near edges of the trench isolation structures and reduce/alleviate/prevent the formation of a leaky junction around the edges of the trench isolation structures. | 01-23-2014 |
20150084126 | LDMOS DEVICE WITH SHORT CHANNEL AND ASSOCIATED FABRICATION METHOD - A method of fabricating an LDMOS device includes: forming a gate of the LDMOS device on a semiconductor substrate; performing tilt body implantation by implanting dopants of a first conductivity type in the semiconductor substrate using a mask, wherein the tilt body implantation is implanted at an angle from a vertical direction; performing zero tilt body implantation by implanting dopants of the first conductivity type using the same mask, wherein the zero tilt body implantation is implanted with zero tilt from the vertical direction, and wherein the tilt body implantation and the zero tilt body implantation are configured to form a body region of the LDMOS device; and forming a source region and a drain contact region of the LDMOS device, wherein the source region and the drain contact region are of a second conductivity type. | 03-26-2015 |
Ji Hye Jung, Palo Alto, CA US
Patent application number | Description | Published |
---|---|---|
20120173986 | BACKGROUND SYNCHRONIZATION WITHIN A MULTI-ENVIRONMENT OPERATING SYSTEM - A device and method for synchronizing background images within a multi-environment operating system is provided herein. During operation, a processor running a first operating system environment will utilize a first background image for a first graphical user interface on the device. The first operating system will save the first background image to a shared image file. A second operating system environment being run by the processor will access the shared image file and utilize the first background image for a second GUI on an external display. | 07-05-2012 |
20120174232 | MECHANISM FOR EMBEDDING DEVICE IDENTIFICATION INFORMATION INTO GRAPHICAL USER INTERFACE OBJECTS - A mechanism for protecting software and computing devices from unintentional pre-release disclosure (“leak”) is provided that includes applying a security enhancement to an object on the graphical user interface of the computing device such that the object can be used to visually determine the origin of the leak without obstructing the user's experience or being easily detected or defeated. | 07-05-2012 |
20130311682 | Synchronizing Launch-Configuration Information Between First and Second Application Environments that are Operable on a Multi-Modal Device - A method for a multi-modal device for transferring launch information for a panel and first docking bar in a first application environment to a second application environment for a second docking bar in the second application environment includes detecting a docking of the multi-modal device to a hardware module, and displaying a user interface for the second application environment operating on the multi-modal device on the hardware module. The method includes receiving at the second application environment the launch information for launching launchable objects in the first application environment from the second application environment, and parsing, by the second application environment, the launch information to determine a change to the panel or the first docking bar. The change is in the first application environment. The method includes changing the second docking bar to include the change to the panel or the first docking bar based on parsing the launch information. | 11-21-2013 |
20130311888 | Arranging a Set of Panels in a First Application Environment Via Arrangement of the Set of Panels in a Second Application Environment for a Multi-Modal Device - A method for arranging a set of panels in a first application environment via arrangement of the set of panels in a second application environment includes receiving a request by a first application environment for configuration information for a set of panels of the first application environment from a second application environment, and receiving by the second application environment the configuration information. The method includes displaying the set of panels in a user interface of the second application environment based on the configuration information, and receiving, via the user interface, an input for changing one of the panels. The method includes receiving a request, by the first application environment, for changing the one panel in the first application environment from the second application environment, and changing the one panel in the first application environment to match the change of the one panel in the second application environment. | 11-21-2013 |
Jongsun Jung, Tustin, CA US
Patent application number | Description | Published |
---|---|---|
20100131852 | SYSTEM AND METHOD FOR DELIVERING DOCUMENTS TO PARTICIPANTS OF WORK-FLOW EVENTS OR TASKS - A system and method for transmitting documents from a document device, such as an MFP. The MFP accesses calendar and workflow servers to determine a list of information items. A user can select an information item for which the document is to be associated and the document device will then determine all of the associated document destinations, e.g., workspaces, email addresses, and the like, and then subsequently transmit the documents to all of the document destinations that are associated with the information item or a subset of the document destination associated with the information item as selected by the user. | 05-27-2010 |
Juergen Claus Jung, Palo Alto, CA US
Patent application number | Description | Published |
---|---|---|
20120281218 | OPTICAL ANALYSIS SYSTEM AND APPROACH THEREFOR - Imaging, testing and/or analysis of subjects are facilitated with a capillary-access approach. According to an example embodiment, a capillary is implanted into a specimen and adapted to accept an optical probe to facilitate optical access into the specimen. In some applications, the capillary is implanted for use over time, with one or more different probes being inserted into the capillary at different times, while the capillary is implanted. Certain applications involve capillary implantation over weeks, months or longer. Other applications are directed to the passage of fluid to and/or from a sample via the capillary. Still other applications are directed to the passage of electrical information between the sample and an external arrangement, via an implanted capillary. | 11-08-2012 |
20150057549 | LIVE BEING OPTICAL ANALYSIS SYSTEM AND APPROACH - Analysis of live beings is facilitated. According to an example embodiment of the present invention, a light-directing arrangement such as an endoscope is mounted to a live being. Optics in the light-directing arrangement are implemented to pass source light (e.g., laser excitation light) into the live being, and to pass light from the live being for detection thereof. The light from the live being may include, for example, photons emitted in response to the laser excitation light (i.e., fluoresced). The detected light is then used to detect a characteristic of the live being. | 02-26-2015 |
Kee Bum Jung, Gilroy, CA US
Patent application number | Description | Published |
---|---|---|
20120009803 | Mixing Energized and Non-Energized Gases for Silicon Nitride Deposition - A dual channel gas distributor can simultaneously distribute plasma species of an first process gas and a non-plasma second process gas into a process zone of a substrate processing chamber. The gas distributor has a localized plasma box with a first inlet to receive a first process gas, and opposing top and bottom plates that are capable of being electrically biased relative to one another to define a localized plasma zone in which a plasma of the first process gas can be formed. The top plate has a plurality of spaced apart gas spreading holes to spread the first process gas across the localized plasma zone, and the bottom plate has a plurality of first outlets to distribute plasma species of the plasma of the first process gas into the process zone. A plasma isolated gas feed has a second inlet to receive the second process gas and a plurality of second outlets to pass the second process gas into the process zone. A plasma isolator is between the second inlet and second outlets to prevent formation of a plasma of the second process gas in the plasma isolated gas feed. | 01-12-2012 |
Keewook Jung, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20090323830 | CURRENT MODE CIRCUITRY TO MODULATE A COMMON MODE VOLTAGE - In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed. | 12-31-2009 |
Kenneth Jung, San Francisco, CA US
Patent application number | Description | Published |
---|---|---|
20090311250 | METHODS AND COMPOSITIONS FOR THE DIAGNOSIS AND TREATMENT OF CANCER - Methods and compositions are provided for the diagnosis and treatment of colorectal cancers associated with amplification or overexpression of the FGFR2 gene. | 12-17-2009 |
20100008910 | METHODS AND COMPOSITIONS FOR THE DIAGNOSIS AND TREATMENT OF CANCER - Methods and compositions are provided for the diagnosis and treatment of lung cancers in particular NSCLC associated with amplification or overexpression of the PRO gene, i.e. any of PDGFRA, KIT or KDR. | 01-14-2010 |
20100028365 | METHODS AND COMPOSITIONS FOR THE DIAGNOSIS AND TREATMENT OF CANCER - Methods and compositions are provided for the diagnosis and treatment of gastric cancers associated with amplification or overexpression of the c-Myb gene. | 02-04-2010 |
Kenneth H. Jung, Newbury Park, CA US
Patent application number | Description | Published |
---|---|---|
20090123937 | Methods of selecting epidermal growth factor receptor (EGFR) binding agents - The present application relates to methods of selecting EGFr binding agents. In certain embodiments, such EGFr binding agents bind to at least a portion of a panitumumab epitope on an EGFr. In certain embodiments, such EGFr binding agents do not bind to a panitumumab epitope on an EGFr. | 05-14-2009 |
20150051091 | METHODS OF SELECTING EPIDERMAL GROWTH FACTOR RECEPTOR (EGFR) BINDING AGENTS - The present application relates to methods of selecting EGFr binding agents. In certain embodiments, such EGFr binding agents bind to at least a portion of a panitumumab epitope on an EGFr. In certain embodiments, such EGFr binding agents do not bind to a panitumumab epitope on an EGFr. | 02-19-2015 |
Kevin H. Jung, Torrance, CA US
Patent application number | Description | Published |
---|---|---|
20090057307 | Foldable storage container - A foldable storage container can be used as a suitcase or to hold and transport sports balls and has a rear panel, two side panels, a base, a front panel and a cover. The rear panel has a top, a bottom and two side edges. The side panels are respectively formed perpendicularly on the side edges of the rear panel and are foldable. The base is mounted pivotally on the rear panel. The front panel is mounted slidably between the side panels and has a top. The cover is mounted pivotally and detachably on the top of the rear panel and is selectively locked on the top of the front panel. Therefore, the foldable storage container can be folded to occupy a smaller space for convenient storage. | 03-05-2009 |
20090095762 | STORAGE CONTAINER WITH RETRACTABLE STANDS - A storage container with retractable stands has a body and two stand assemblies. The body has a front surface, a rear surface and multiple slots. The slots are formed in the front and rear surfaces. Each stand assembly has multiple props. Each prop is mounted pivotally in a corresponding slot. The props are pivoted to stand on the ground to stand the storage container off the ground for increased convenience. When the props are held in the slots, the props are completely received in the slots to avoid additional storage volume. | 04-16-2009 |
Kyung Woon Jung, Fullerton, CA US
Patent application number | Description | Published |
---|---|---|
20100036131 | N-HETEROCYCLIC CARBENE-AMIDO PALLADIUM(II) CATALYSTS AND METHOD OF USE THEREOF - A new N-heterocyclic catalyst system which contains N-heterocyclic carbene and amido as ligands, which are strongly bound to a palladium metal. Another heteroatom functionality can be used as a third ligand L. The NHC-amidate ligand system is unique in structure, and shows excellent reactivities in a number of chemical reactions. The chemical reactions include carbon-carbon and carbon-heteroatom (oxygen and nitrogen) bond formations, and oxidation reactions of saturated carbon chemicals via C—H activation. | 02-11-2010 |
Man-Young Jung, La Canada, CA US
Patent application number | Description | Published |
---|---|---|
20090090031 | Anti-slip footwear - A moisture repellant tread is provided for a positive displacement of moisture to secure the traction in the bottom of a shoe. The tread comprises a base plate and multiple short bundles of absorbent fibers. The base plate has a top surface locally bonded to the outsole with a lateral clearance between the base plate and outsole about the bonded areas, a bottom surface for contacting a floor and multiple closely arranged recesses open to the bottom surface and communicating through smaller openings formed at the top surfaces concentrically of the recesses. The fiber bundles are partially implanted in the recesses for displacing water absorbed from the floor upon contact through the openings at the top surfaces to the lateral clearance whereby the tread secures an increased traction as a wearer steps on the tread through the shoe even on a film of moisture. | 04-09-2009 |
Richard Jung, Laguna Niguel, CA US
Patent application number | Description | Published |
---|---|---|
20120145166 | Intra-oral mandibular advancement appliance - An intra-oral mandibular advancement appliance to be inserted in the mouth of a patient so as to maintain an open airway to the patient's throat and thereby improve breathing during sleep. The mandibular advancement appliance has particular application for use by those wishing to reduce the effects of snoring and/or sleep apnea. The appliance includes an upper tray assembly against which is seated the patient's teeth carried by his upper jaw and a lower tray assembly against which the patient's teeth carried by his lower jaw are seated. The lower tray assembly is mated to and slidably adjustable by the patient relative to the upper tray assembly. By virtue of the foregoing, the position of the patient's lower jaw can be selectively and continuously moved forward with respect to the position of the upper jaw to prevent an occlusion of the airway as the patient's condition changes over time. | 06-14-2012 |
Richard Jung, Irvine, CA US
Patent application number | Description | Published |
---|---|---|
20110127280 | CONTAINER WITH SLEEVE - A container assembly is provided including a container body; and a sleeve body. The sleeve body defines an open space within the sleeve body, and a first opening formed at a first end of the sleeve body concentric about a central axis of the sleeve body. The sleeve body also defines a second opening disposed on a surface of the sleeve body substantially perpendicular to the first opening. The second opening provides access to the open space, and includes an edge perimeter that provides increased elasticity to the second opening relative to the remainder of the sleeve body. | 06-02-2011 |
20110198352 | CARAFE WITH A 360 DEGREE POURING CAPABILITY - A carafe is provided including a carafe body; and a cap. The cap includes an outer lid defining a pouring space surrounded by a continuous peripheral rim. A removable cap is removably mated to the outer lid. The carafe body is movable between a non-pouring position where a liquid is contained within the carafe body and a pouring position where liquid is allowed to flow from within the carafe body into the pouring space. The liquid may be poured out from the pouring space in any direction over any portion of the continuous peripheral rim of the outer lid. | 08-18-2011 |
20120145713 | LOCKABLE CAP - A lockable cap assembly including a handle having at least one protrusion, and a flip cap defining an internal chamber surrounded by a flip cap edge. The flip cap including at least one locking groove configured to engage the at least one protrusion, and an engagement surface. The lockable cap also including a collar having a release mechanism for engaging with the engagement surface. The flip cap being moveable between an open configuration in which a portion of the flip cap edge is not in contact with a surface of the collar and a closed configuration in which the flip cap edge is in full contact with the collar. | 06-14-2012 |
Richard K. Jung, Laguna Beach, CA US
Patent application number | Description | Published |
---|---|---|
20090008284 | Container/Lid Combination For Storing Food and other Articles - A system for aiding the visual matching of containers having diverse openings with matching lids includes affixing, such as by molding or embossing, geometric planar patterns on the bottom walls of a plurality of rectangular containers having different sized openings and affixing the same geometric patterns to the top wall of the matching lids. | 01-08-2009 |
Sang-Hwa Jung, Sunnyvale, CA US
Patent application number | Description | Published |
---|---|---|
20100026361 | LEVEL SHIFTER AND DRIVING CIRCUIT INCLUDING THE SAME - The present invention related to a driving circuit including a level shifter. The driving circuit according to exemplary embodiment of the present invention includes a first level shifter, a second level shifter, and a gate driver. The first level shifter includes a path along which a pulse-on current flows in response to an on-control signal and a path along which a pulse-off control flows in response to an off-control signal. The second level shifter includes a path along which an on-current flows in response to the on-control signal and a path along which an off-control flows in response to the off-control signal. The gate driver turns on the switch in response to the pulse-on current, maintains the turned-on switch in the turn-on state in response to the on-control current, turns off the switch in response to the pulse-off current, and maintains the turned-off switch in the turn-off state in response to the off-control current. | 02-04-2010 |
Sang-Kyu Jung, Davis, CA US
Patent application number | Description | Published |
---|---|---|
20120045818 | Plant-Based Production of Heterologous Proteins - Described herein are viral amplicon-based protein expression systems and methods useful for producing heterologous proteins, such as enzymes, by agroinfiltration. The methods involve producing an | 02-23-2012 |
Seong-Ook Jung, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20090323405 | Controlled Value Reference Signal of Resistance Based Memory Circuit - Systems and methods of controlled value reference signals of resistance based memory circuits are disclosed. In a particular embodiment, a circuit device is disclosed that includes a first input configured to receive a reference control signal. The circuit device also includes an output responsive to the first input to selectively provide a controlled value reference voltage to a sense amplifier coupled to a resistance based memory cell. | 12-31-2009 |
20100157654 | Balancing A Signal Margin Of A Resistance Based Memory Circuit - A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure. The bit line is adapted to detect data having a logic one value when the bit line has a first voltage value, and to detect data having a logic zero value when the bit line has a second voltage value. The circuit further includes a second transistor load of a reference cell. The second transistor load is coupled to the first transistor load, and the second transistor load has an associated reference voltage value. A characteristic of the first transistor load, such as transistor width, is adjustable to modify the first voltage value and the second voltage value without substantially changing the reference voltage value. | 06-24-2010 |
20110176350 | RESISTANCE-BASED MEMORY WITH REDUCED VOLTAGE INPUT/OUTPUT DEVICE - A resistance-based memory with a reduced voltage I/O device is disclosed. In a particular embodiment, a circuit includes a data path including a first resistive memory cell and a first load transistor. A reference path includes a second resistive memory cell and a second load transistor. The first load transistor and the second load transistor are input and output (I/O) transistors adapted to operate at a load supply voltage similar to a core supply voltage of a core transistor within the circuit. | 07-21-2011 |
20110178768 | System and Method of Adjusting a Resistance-Based Memory Circuit Parameter - Systems and methods of resistance-based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance-based memory circuit includes determining a range of sizes for a clamp transistor and selecting a set of clamp transistors having sizes within the determined range of sizes. For each clamp transistor in the set of clamp transistors, a simulation may be executed to generate a first contour graph representing current values over a range of statistical values. The first contour graph may be used to identify a read disturbance area and a design range of the gate voltage of the clamp transistor and a load of the clamp transistor. The method may execute a simulation to generate a second contour graph representing sense margin over a range of statistical values of the gate voltage of the clamp transistor and the load of the clamp transistor. A sense margin may be selected based on the second contour graph that also satisfies the design range of the first contour graph. A sense margin may be determined for a selected clamp transistor in the set of transistors and the corresponding gate voltage and the load of the selected clamp transistor is determined based on the determined sense margin. | 07-21-2011 |
Shah Vikram Jung, Fremont, CA US
Patent application number | Description | Published |
---|---|---|
20110015947 | Collaborative Multi-facility Medication Management System - A computer implemented method and system is provided for managing health care and obtaining analytical insights using information related to health care in a collaborative environment. Health care users and health care providers access a medication management platform in the collaborative environment. The medication management platform comprises a medication management application and a research repository. The health care users and the health care providers interact and communicate with each other in the collaborative environment using collaborative tools provided on the medication management platform. The medication management application acquires health care information of the health care users' personal health records populated from health care information sources. The medication management application monitors and tracks the acquired health care information. The medication management application updates the de-identified research repository by consolidating the monitored and tracked health care information. The medication management application analyzes the consolidated health care information for obtaining the analytical insights. | 01-20-2011 |
Shah Vikram Jung, Freemont, CA US
Patent application number | Description | Published |
---|---|---|
20100280629 | NEUROMORPHIC CONTROLLED POWERED ORTHOTIC AND PROSTHETIC SYSTEM - A neuromorphic controlled powered orthotic and prosthetic system and device including a custom or universal fit fixed-ankle orthosis, to stabilize or immobilize an injured lower limb or act as an ankle prosthesis, and an actuated or powered articulated false-foot connected to the fixed-ankle orthosis or the prosthesis to form an actuated articulated false-foot orthosis. Associated with or mounted on the actuated articulated false-foot, or in or on the body, are sensors for sensing the intent of the subject to move, and the movement range of the articulating false-foot or AAFO and an environmental perturbation. An actuator is used to drive the articulated false-foot orthosis. The system and device further include a controller having an electronic circuit with a biomimetic design based on knowledge of connectivity of neurons within the spinal cord of a primitive vertebrate. The system and device include an electronic circuit made from analog very large scale integrated components and discrete electronic components capable of autonomously generating cyclic voltage output. An integral power supply serves the portable controller and AAFO. | 11-04-2010 |
20150025653 | NEUROMORPHIC CONTROLLED POWERED ORTHOTIC AND PROSTHETIC SYSTEM - A neuromorphic controlled powered orthotic and prosthetic system and device including a custom or universal fit fixed-ankle orthosis, to stabilize or immobilize an injured lower limb or act as an ankle prosthesis, and an actuated or powered articulated false-foot connected to the fixed-ankle orthosis or the prosthesis to form an actuated articulated false-foot orthosis. Associated with or mounted on the actuated articulated false-foot, or in or on the body, are sensors for sensing the intent of the subject to move, and the movement range of the articulating false-foot or AAFO and an environmental perturbation. An actuator is used to drive the articulated false-foot orthosis. The system and device further include a controller having an electronic circuit with a biomimetic design based on knowledge of connectivity of neurons within the spinal cord of a primitive vertebrate. The system and device include an electronic circuit made from analog very large scale integrated components and discrete electronic components capable of autonomously generating cyclic voltage output. An integral power supply serves the portable controller and AAFO. | 01-22-2015 |
Shane F. Jung, Torrance, CA US
Patent application number | Description | Published |
---|---|---|
20090057307 | Foldable storage container - A foldable storage container can be used as a suitcase or to hold and transport sports balls and has a rear panel, two side panels, a base, a front panel and a cover. The rear panel has a top, a bottom and two side edges. The side panels are respectively formed perpendicularly on the side edges of the rear panel and are foldable. The base is mounted pivotally on the rear panel. The front panel is mounted slidably between the side panels and has a top. The cover is mounted pivotally and detachably on the top of the rear panel and is selectively locked on the top of the front panel. Therefore, the foldable storage container can be folded to occupy a smaller space for convenient storage. | 03-05-2009 |
20090095762 | STORAGE CONTAINER WITH RETRACTABLE STANDS - A storage container with retractable stands has a body and two stand assemblies. The body has a front surface, a rear surface and multiple slots. The slots are formed in the front and rear surfaces. Each stand assembly has multiple props. Each prop is mounted pivotally in a corresponding slot. The props are pivoted to stand on the ground to stand the storage container off the ground for increased convenience. When the props are held in the slots, the props are completely received in the slots to avoid additional storage volume. | 04-16-2009 |
20090152315 | Racket bag - A racket bag has a body, at least one adjustable strap and a holding strap assembly. The body has a front panel, a rear panel, two side panels and a bottom panel. The side panels and the bottom panel are mounted between the front and rear panels and are collapsible. Each adjustable strap is mounted between the front and rear panels to adjust the distance between the front and rear panels to fit different quantities of rackets that are put between the front and rear panels. The holding strap assembly is attached to the rear panel to allow the user to hold, hang or carry the racket bag. | 06-18-2009 |
Shu F. Jung, Torrance, CA US
Patent application number | Description | Published |
---|---|---|
20090057307 | Foldable storage container - A foldable storage container can be used as a suitcase or to hold and transport sports balls and has a rear panel, two side panels, a base, a front panel and a cover. The rear panel has a top, a bottom and two side edges. The side panels are respectively formed perpendicularly on the side edges of the rear panel and are foldable. The base is mounted pivotally on the rear panel. The front panel is mounted slidably between the side panels and has a top. The cover is mounted pivotally and detachably on the top of the rear panel and is selectively locked on the top of the front panel. Therefore, the foldable storage container can be folded to occupy a smaller space for convenient storage. | 03-05-2009 |
20090095762 | STORAGE CONTAINER WITH RETRACTABLE STANDS - A storage container with retractable stands has a body and two stand assemblies. The body has a front surface, a rear surface and multiple slots. The slots are formed in the front and rear surfaces. Each stand assembly has multiple props. Each prop is mounted pivotally in a corresponding slot. The props are pivoted to stand on the ground to stand the storage container off the ground for increased convenience. When the props are held in the slots, the props are completely received in the slots to avoid additional storage volume. | 04-16-2009 |
20090152315 | Racket bag - A racket bag has a body, at least one adjustable strap and a holding strap assembly. The body has a front panel, a rear panel, two side panels and a bottom panel. The side panels and the bottom panel are mounted between the front and rear panels and are collapsible. Each adjustable strap is mounted between the front and rear panels to adjust the distance between the front and rear panels to fit different quantities of rackets that are put between the front and rear panels. The holding strap assembly is attached to the rear panel to allow the user to hold, hang or carry the racket bag. | 06-18-2009 |
Simon Jung, Alhambra, CA US
Patent application number | Description | Published |
---|---|---|
20100093254 | Doll With Dress That Transforms to Wings - Interactive and reconfigurable toy dolls are disclosed. The toy dolls have one or more associated movable components that may be actuated through user manipulation so as to transform a doll's dress into wings. | 04-15-2010 |
20100330869 | Hair Styling Mechanisms And Hair Styling Dolls - A hair styling doll with a hair styling mechanism is disclosed. The doll includes a body with a head to which a lock of hair is coupled. The doll includes an adjustment mechanism that can be manipulated to adjust the length and shape or configuration of the lock of hair. The hair is braided and the adjustment mechanism includes an elongate member that is coupled to the different sections of the braided hair. The elongate member is coupled to the hair in an alternating configuration or pattern such that pulling the elongate member results in the braided hair coiling and forming a bun-like structure. | 12-30-2010 |
Steve Jung, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20110270800 | Global Deduplication File System - Embodiments of methods and systems implementing global deduplication file systems are described. In one embodiment of the invention, a method and system implements a global deduplication file system between a plurality of interconnected systems located in different locations globally by making use of the deduplication dictionary included in metadata being periodically snapshot. In yet another embodiment of the invention, a method implements a global deduplication file system between a plurality of interconnected systems located in different locations globally and provides appropriate read/write locks. | 11-03-2011 |
20110271067 | Efficient Cloud Network Attached Storage - Snapshots of data and metadata associated with the data are created. The snapshot of the data is separate from the snapshot of the associated metadata. The snapshot of metadata is maintained locally in a cloud network attached storage (NAS) and globally. The snapshot of data is maintained according to an accessibility metric. | 11-03-2011 |
Sungeun Jung, Irvine, CA US
Patent application number | Description | Published |
---|---|---|
20120013483 | Water Supply Maintenance System - A GIS-based computerized system is provided for maintaining a water supply system having a pipe network and a plurality of measuring sensors. The maintenance system includes a transmitter that receives information from the measuring sensors, and transmits the information, a collector that collects the information transmitted by the transmitter, an information analyzer that analyzes the collected information and decides prescribed status variables for the maintenance system, a storage that stores information provided by the collector and the information analyzer, an alarm device that generates an alarm when the information analyzer decides a leak expectation, a sensor error or an abnormal operation, a pipe network analyzer that analyzes the pipe network base on the collected information. The pipe network analyzer analyzes the information stored by the storage based on a pipe network scheme that is constructed with space data of the water supply system. | 01-19-2012 |
20120150783 | Disaster Analysis and Decision System - A disaster analysis and decision system comprises a geographic area module that comprises geographic data for a given geographic area; an artificial facilities module that comprises artificial facilities data positioned in the geographic area; a disaster control facilities module that comprises disaster control facilities data for the geographic area; an environmental variable module that receives and stores environmental variables that affects the geographic area; an analysis module that analyzes how the environmental variables affect the geographic area, the artificial facilities within the geographic area and the disaster control facilities for the geographic area, and decides how to control the disaster control facilities; a report module that provides reports for the analysis; and a database that stores data from other modules. | 06-14-2012 |
Taehyung Jung, Santa Clara, CA US
Patent application number | Description | Published |
---|---|---|
20100202220 | MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR PROVIDING BIT LINE EQUALIZATION VOLTAGES - A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a first bit line. At least one bit line equalization transistor is coupled between the first bit line and a second bit line. A bit line equalization circuit is coupled with the bit line equalization transistor. The bit line equalization circuit is configured for providing a pulse to the bit line equalization transistor to substantially equalize voltages of the first bit line and the second bit line during a standby period before an access cycle of the memory cell. | 08-12-2010 |
20130286754 | Wordline Coupling Reduction Technique - A semiconductor memory includes a memory array having memory cells coupled to wordlines and bitlines. Each wordline has a left end and an opposing right end. A first wordline in every two adjacent wordlines has its left end connected to a left row driver and its right end connected to a right clamp circuit, and a second wordline in every two adjacent wordlines has its right end connected to a right row driver and its left end connected to a left clamp circuit, such that when the right clamp circuits are activated, the right clamp circuits clamp the corresponding wordline ends to a predetermined potential, and when the left clamp circuits are activated, the left clamp circuits clamp the corresponding wordline ends to the predetermined potential. | 10-31-2013 |
20140003175 | STORAGE CELL BRIDGE SCREEN TECHNIQUE | 01-02-2014 |
20140146608 | Oscillator Circuit With Location-Based Charge Pump Enable And Semiconductor Memory Including The Same - A semiconductor memory includes a plurality of memory blocks each comprising a plurality of memory cells, and a plurality of charge pumps each located near one of the plurality of memory blocks. In an access to the semiconductor memory, depending on the selected memory block, a subset or all of the plurality of charge pumps are activated in one of a predetermined number of sequences. | 05-29-2014 |
Tae Hyung Jung, Santa Clara, CA US
Patent application number | Description | Published |
---|---|---|
20090256625 | CIRCUIT AND METHOD FOR A GATE CONTROL CIRCUIT WITH REDUCED VOLTAGE STRESS - Circuit and method for a gate control output circuit having reduced voltage stress on the devices is disclosed. In a circuit of MOS transistors for supplying an output to control a transfer gate, the output having a high voltage level that exceeds a supply voltage, first and second clamping circuits are provided. The first clamping circuit ensures a voltage between the gate and the source/drain and drain/source of a PMOS transistor that couples a pumped voltage to the output does not exceed a predetermined voltage. The second clamping circuit ensures that the voltage between the gate of an NMOS transistor and the output which is coupled to the drain/source of the NMOS transistor does not exceed a predetermined amount. The clamping circuits prevent gate stress problems on the transistors by ensuring the voltages between the gates and the source/drain and drain/source terminals do not exceed predetermined voltages. | 10-15-2009 |
20120170382 | SEMICONDUCTOR MEMORY DEVICE, TEST CIRCUIT, AND TEST OPERATION METHOD THEREOF - A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells, a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads, a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads, a path selection unit configured to transfer the first data which are input through the first data pads, to both the first and second memory cells, during a test mode, and a test mode control unit configured to compare the first data of the first and second memory cells, and to control the first data pads to denote a fail status based on a comparison result, during the test mode. | 07-05-2012 |
20120173942 | SEMICONDUCTOR MEMORY DEVICE, TEST CIRCUIT, AND TEST OPERATION METHOD THEREOF - A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells; a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads; a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells during a test mode; and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode. | 07-05-2012 |
Tae-Hyung Jung, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20110158019 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device that can minimize the area of a circuit for generating a BLEQ signal by using one power source voltage terminal floated for the generation of a BLEQ signal. The semiconductor memory device includes a power source supplier configured to supply a power source of a main power source voltage terminal to a sub-power source voltage terminal in response to a mat selection signal for selecting a corresponding memory cell mat among a plurality of memory cell mats, a bit line equalization (BLEQ) signal generator configured to be coupled with the sub-power source voltage terminal and generate a BLEQ signal corresponding to a voltage level of the sub-power source voltage terminal in response to a BLEQ control signal, and a bit line equalizer configured to precharge and equalize a bit line pair in response to the BLEQ signal. | 06-30-2011 |
Taewon Jung, Irvine, CA US
Patent application number | Description | Published |
---|---|---|
20120262217 | RADIO FREQUENCY MULTI-PORT SWITCHES - A multiport radio frequency (RF) switch circuit is disclosed. The switch circuit includes a first transistor that is connected to a first port, a common antenna port, and a first enable line. The first transistor is selectively activatable in response to a first enable signal applied to the first enable line. There is also a second transistor connected to a second port, the common antenna port, and a second enable line. The second transistor is selectively activatable in response to a second enable signal applied to the second enable line. A first inductor connected to the first port and the second port compensates for parasitic capacitance between the first port and the second port from an inactive one of the transistors. | 10-18-2012 |
Thomas F. Jung, San Rafael, CA US
Patent application number | Description | Published |
---|---|---|
20120030726 | DYNAMIC VIDEO CONTENT APPARATUSES, SYSTEMS AND METHODS - A media control player includes a central processing unit, a graphics processing unit, an audio/video input, an audio/video output, a memory device, and a media control player housing. The media control player to receives broadcast content from a broadcast source and proprietary targeted messages from a proprietary targeted message source. The proprietary targeted messages are based on one or more viewers within a viewing area of a display device, sales data associated with the one or more viewers, and inventory data selected based at least in part on the sales data. The media control player combines the proprietary targeted messages and the broadcast content into a merged output signal, and provides the merged output signal to the display device such that the proprietary targeted messages are displayed in a message region of the display device and the broadcast content is displayed in a broadcast content region of the display device. | 02-02-2012 |
Tzyy-Ping Jung, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20090001262 | System and Method for Spectral Analysis - The system and method for spectral analysis uses a set of spectral data. The spectral data is arranged according to a second dimension, such as time, temperature, position, or other condition. The arranged spectral data is used in a signal separation process, such as an independent component analysis (ICA), which generates independent signals. The independent signals are then used for identifying or quantifying a target component. | 01-01-2009 |
20130127708 | CELL-PHONE BASED WIRELESS AND MOBILE BRAIN-MACHINE INTERFACE - Techniques and systems are disclosed for implementing a brain-computer interface. In one aspect, a system for implementing a brain-computer interface includes a stimulator to provide at least one stimulus to a user to elicit at least one electroencephalogram (EEG) signal from the user. An EEG acquisition unit is in communication with the user to receive and record the at least one EEG signal elicited from the user. Additionally, a data processing unit is in wireless communication with the EEG acquisition unit to receive and process the recorded at least one EEG signal to perform at least one of: sending a feedback signal to the user, or executing an operation on the data processing unit. | 05-23-2013 |
Wesley Jung, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20110262309 | REACTIVE COMPONENT REDUCTION SYSTEM AND METHODS FOR THE USE THEREOF - In accordance with the present invention, there are provided simplified systems and methods for deactivating, removing, or reducing the levels of reactive component(s) from vapor phase fluids prior to introduction thereof into fuel storage tanks. The simple apparatus described herein can be utilized to replace complex systems on the market. Simply stated, in one embodiment of the invention, the vapor phase fluid contemplated for introduction into the fuel storage tank is passed through a reaction zone (e.g., a catalytic bed) operated at appropriate temperatures to allow the reaction between free reactive components therein (e.g., oxygen and hydrogen or other fuel vapor), thereby deactivating reactive component(s) in the gas phase. | 10-27-2011 |
Wesley Jung, Bonita, CA US
Patent application number | Description | Published |
---|---|---|
20120216677 | CONTACTING SYSTEMS AND METHODS AND USES THEREOF - In accordance with the present invention, there are provided systems and methods for contacting two or more fluids, useful, for example for purifying or infusing a fluid (by allowing efficient and/or uniform addition of components to or removal of components from the fluid). The components may be undesirable components to be removed from a fluid, or a desired component or components to be added to the fluid, for example, each of which is referred to herein as “component”. In this regard, the disclosed embodiments provide for the purification or infusion of a fluid by passing a liquid and a fluid through a contacting zone which facilitates intimate mixing of the liquid and the fluid. A differential of partial pressure, activity, fugacity or concentration of the components between the liquid and the fluid facilitates the transfer of the components between the liquid and the fluid in the intimately mixed liquid and fluid. | 08-30-2012 |
Yong Baik Jung, Vernon, CA US
Patent application number | Description | Published |
---|---|---|
20120141725 | Floor Mat - A floor mat including a carpet portion, one or more hook-and-loop fastener portions, an anti-slip portion, and an edge portion is provided. The carpet portion is disposed on a top surface. The one or more hook-and-loop fastener portions are disposed on a bottom surface, each of which being corresponds to a counter fastener portion installed on a floor. The anti-slip portion is disposed on the bottom surface, comprising a plurality of bumps protruding downward from the bottom surface. The edge portion surrounds and secures the top and bottom surface. The bumps are disposed in a predetermined density and pattern. The carpet portion may comprise durable fabric. | 06-07-2012 |
Youngkyoo Jung, La Jolla, CA US
Patent application number | Description | Published |
---|---|---|
20100240983 | MULTI-PHASE PSEUDO-CONTINUOUS ARTERIAL SPIN LABELING - Techniques, systems and apparatus are described for magnetic resonance imaging. A magnetic resonance imaging (MRI) system comprises a scanner comprising a magnet, gradient coils and a radio frequency (RF) system to perform various operations. The scanner can apply a gradient field and a train of RF pulses comprising more than two phases to tag a target blood vessel, and acquire magnetic resonance signals based on the applied train of RF pulses to sample the more than two phases. The MRI system includes a data processing system in communication with the scanner to receive the acquired magnetic resonance signals and process the received magnetic resonance signal to generate images proportional to perfusion. | 09-23-2010 |