Patent application number | Description | Published |
20090014704 | CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE - A layer of nanopaiticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer. | 01-15-2009 |
20090053886 | High density chalcogenide memory cells - A non-volatile memory cell is constructed from a chalcogenide alloy structure and an associated electrode side wall. The electrode is manufactured with a predetermined thickness and juxtaposed against a side wall of the chalcogenide alloy structure, wherein at least one of the side walls is substantially perpendicular to a planar surface of the substrate. The thickness of the electrode is used to control the size of the active region created within the chalcogenide alloy structure. Additional memory cells can be created along rows and columns to form a memory matrix. The individual memory cells are accessed through address lines and address circuitry created during the formation of the memory cells. A computer can thus read and write data to particular non-volatile memory cells within the memory matrix. | 02-26-2009 |
20090166603 | METHOD OF FORMING A SMALL CONTACT IN PHASE-CHANGE MEMORY - A method of fabricating a phase-change memory cell is described. The cross-sectional area of a contact with a phase-change memory element within the cell is controlled by a width and an exposed length of a bottom electrode. The method allows the formation of very small phase-change memory cells. | 07-02-2009 |
20100193763 | CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE - A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer. | 08-05-2010 |
20110049462 | FLAT LOWER BOTTOM ELECTRODE FOR PHASE CHANGE MEMORY CELL - A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts. | 03-03-2011 |
20110121253 | MEMORY DEVICE - A memory device is described. The memory device comprises a bottom electrode, a first pair of spacers, a second pair of spacers and a phase-change element. The bottom electrode has a lower horizontal portion and a vertical portion, and the vertical portion has a top surface and a side. The first pair of spacers covers the side of the vertical portion. The second pair of spacers covers a first portion of the top surface of the vertical portion. The phase-change element is contacted a second portion of the top surface of the vertical portion. | 05-26-2011 |
Patent application number | Description | Published |
20090323388 | Buried Bit Line Anti-Fuse One-Time-Programmable Nonvolatile Memory - An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.− doped regions. Another N.sup.+ doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.− doped regions on the substrate. An anti-fuse is defined over the N.sup.+ doped region. Two insulator regions are deposited over the two P.sup.− doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed. | 12-31-2009 |
20100296328 | BURIED BIT LINE ANTI-FUSE ONE-TIME-PROGRAMMABLE NONVOLATILE MEMORY - An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.-doped regions. Another N.sup.+doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.-doped regions on the substrate. An anti-fuse is defined over the N.sup.+doped region. Two insulator regions are deposited over the two P.sup.-doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed. | 11-25-2010 |
20120280197 | FLAT LOWER BOTTOM ELECTRODE FOR PHASE CHANGE MEMORY CELL - A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts. | 11-08-2012 |
Patent application number | Description | Published |
20120193599 | PHASE CHANGE MEMORY CELL ARRAY WITH SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING - An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings. | 08-02-2012 |
20120231613 | 3D MEMORY ARRAY ARRANGED FOR FN TUNNELING PROGRAM AND ERASE - A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory. | 09-13-2012 |
20120326111 | Ge-RICH GST-212 PHASE CHANGE MEMORY MATERIALS - A phase change material comprises Ge | 12-27-2012 |
20130056699 | PHASE CHANGE MEMORY CELL HAVING VERTICAL CHANNEL ACCESS TRANSISTOR - A device includes a substrate having a first region and a second region. The first region comprises a first field effect transistor having a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal. | 03-07-2013 |
20130094273 | 3D MEMORY AND DECODING TECHNOLOGIES - A 3D memory device is based on an array of conductive pillars and a plurality of patterned conductor planes including left side and right side conductors adjacent the conductive pillars at left side and right side interface regions. Memory elements in the left side and right side interface regions comprise a programmable transition metal oxide which can be characterized by built-in self-switching behavior, or other programmable resistance material. The conductive pillars can be selected using two-dimensional decoding, and the left side and right side conductors in the plurality of planes can be selected using decoding on a third dimension, combined with left and right side selection. | 04-18-2013 |
20130140513 | THERMALLY CONFINED ELECTRODE FOR PROGRAMMABLE RESISTANCE MEMORY - A memory device includes a plurality of side-wall electrodes formed on a first side-wall of a trench within an insulating layer over a first plurality of contacts in an array of contacts in a substrate. The plurality of side-wall electrodes contact respective top surfaces of the first plurality of contacts. The side-wall electrodes respectively comprise a layer of tantalum nitride, having a composition Ta | 06-06-2013 |
20130234093 | COMPOSITE TARGET SPUTTERING FOR FORMING DOPED PHASE CHANGE MATERIALS - A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition. | 09-12-2013 |
20130286709 | BURIED BIT LINE ANTI-FUSE ONE-TIME-PROGRAMMABLE NONVOLATILE MEMORY - An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P | 10-31-2013 |
20130286711 | BLOCKING CURRENT LEAKAGE IN A MEMORY ARRAY - A method for blocking current leakage through defective memory cells in a memory array is provided. The memory cells include access devices and programmable resistance memory elements. The method includes identifying addresses of defective memory cells in the memory array, and applying a modifying bias condition to modify the defective memory cells at the identified addresses. The modifying bias condition causes the defective memory cells to transform into a current blocking condition. The method also includes storing the identified addresses in a redundancy table of addresses. An automatic test system includes a device tester adapted to identify addresses of defective memory cells in a memory array in an integrated circuit under test, and to apply a modifying bias condition to modify the defective memory cells at the identified addresses. | 10-31-2013 |
20130306931 | Sidewall Thin Film Electrode with Self-Aligned Top Electrode and Programmable Resistance Memory - A memory device includes an array of electrodes that includes thin film plates of electrode material. Multilayer strips are arranged as bit lines over respective columns in the array of electrodes, including a layer of memory material and a layer of top electrode material. The multilayer strips have a primary body and a protrusion having a width less than that of the primary body and is self-aligned with contact surfaces on the thin film plates. Memory material in the protrusion contacts surfaces on the distal ends of thin film plates of electrodes in the corresponding column in the array. The device can be made using a damascene process in self-aligned forms over the contact surfaces. | 11-21-2013 |
20140014888 | Thermally-Confined Spacer PCM Cells - A memory device includes an array of contacts and a patterned insulating layer over the array of contacts. The patterned insulating layer includes a trench. The trench includes a sidewall aligned over a plurality of contacts in the array. A plurality of bottom electrodes on a lower portion of the sidewall contacts respective top surfaces of the contacts in the plurality of contacts. A thermally confined spacer of memory material between the patterned insulating layer and an insulating fill material is formed on an upper portion of the sidewall in contact with the plurality of bottom electrodes. | 01-16-2014 |
20140042382 | SIDEWALL DIODE DRIVING DEVICE AND MEMORY USING SAME - A memory device includes a first conductor, a diode, a memory element, and a second conductor arranged in series. The diode includes a first semiconductor layer over and in electrical communication with the first conductor. A patterned insulating layer has a sidewall over the first semiconductor layer. The diode includes an intermediate semiconductor layer on a first portion of the sidewall, and in contact with the first semiconductor layer. The intermediate semiconductor layer has a lower carrier concentration than the first semiconductor layer, and can include an intrinsic semiconductor. A second semiconductor layer on a second portion of the sidewall, and in contact with the intermediate semiconductor layer, has a higher carrier concentration than the intermediate semiconductor layer. A memory element is electrically coupled to the second semiconductor layer. The second conductor is electrically coupled to the memory element. | 02-13-2014 |
20140119110 | PHASE CHANGE MEMORY CODING - An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit. | 05-01-2014 |
20140119127 | DIELECTRIC CHARGE TRAPPING MEMORY CELLS WITH REDUNDANCY - A memory cell array of dielectric charge trapping memory cells and method for performing program, read and erase operations on the memory cell array that includes bits stored at charge trapping sites in adjacent memory cells. A bit of information is stored at a first charge trapping site in a first memory cell and a second charge trapping site in a second adjacent memory cell. Storing charge at two trapping sites in adjacent memory cells increases data retention rates of the array of memory cells as each charge trapping site can be read to represent the data that is stored at the data site. Each corresponding charge trapping site can be read independently and in parallel so that the results can be compared to determine the data value that is stored at the data site in an array of dielectric charge trapping memory cells. | 05-01-2014 |
20140120665 | STACKED BIT LINE DUAL WORD LINE NONVOLATILE MEMORY - An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics. | 05-01-2014 |
20140198553 | INTEGRATED CIRCUIT 3D PHASE CHANGE MEMORY ARRAY AND MANUFACTURING METHOD - A 3D phase change memory device can store multiple bits per cell represented by a plurality of non-overlapping ranges of resistance all of which are established by different resistance ranges corresponding to respective amorphous phase thickness of the phase change memory material. An array of access devices can underlie a plurality of conductive layers, separated from each other and from the array of access devices by insulating layers. An array of pillars extending through the plurality of conductive layers contact corresponding access devices. The phase memory material is between the pillars and conductive layers. Circuitry is configured to program data in the memory cells using programming pulses having shapes that depend on the resistance range of the cell before programming and the data values to be stored. | 07-17-2014 |
20140254257 | Memory And Memory Managing Method - A method for managing memory includes setting a state of a first memory cell to a first state representing a first data and setting a state of a second memory cell to a second state representing the first data. If the state of the second memory cell has changed to a third state representing a second data different from the first data, the method also includes changing the state of the second memory cell back to the second state. | 09-11-2014 |
20140256110 | SELF ALIGNED FIN-TYPE PROGRAMMABLE MEMORY CELL - A fin-type programmable memory cell includes a bottom electrode electrically coupled to an access device, a top electrode, and an L-shaped memory material element electrically coupled to the bottom and top electrodes. A memory array includes an array of such memory cells, electrically coupled to an array of access devices. Method for making a memory cell, includes: forming a dielectric support layer over a bottom electrode, the dielectric support layer having an upper surface; forming a cavity through the dielectric support layer, exposing a surface of the bottom electrode and defining a dielectric support structure having a sidewall; forming a film of memory material over the dielectric support structure and in the cavity; depositing a dielectric spacer layer over the memory material film; forming a dielectric sidewall spacer from the dielectric spacer layer and a memory material structure having a generally horizontal portion underlying the dielectric sidewall spacer and a generally vertical portion between the dielectric sidewall spacer and the sidewall of the dielectric support structure; forming a dielectric fill; planarizing the dielectric fill to expose upper ends of the vertical portion of the memory material structure; depositing a top electrode material over the planarized dielectric fill; and forming a top electrode from the top electrode material and a memory material element from the memory material structure. | 09-11-2014 |
20140264240 | METHOD FOR MAKING MEMORY CELL BY MELTING PHASE CHANGE MATERIAL IN CONFINED SPACE - To form a memory cell with a phase change element, a hole is formed through an insulator to a bottom electrode, and a phase change material is deposited on the insulator surface covering the hole. A confining structure is formed over the phase change material so the phase change material expands into the hole when heated to melting to become electrically connected to the bottom electrode. A top electrode is formed over and electrically connects to the phase change material. The bottom electrode can include a main portion and an extension having a reduced lateral dimension. The confining structure can include capping material having a higher melting temperature than the phase change material, and sufficient tensile strength to ensure the phase change material moves into the hole when the phase change material melts and expands. The hole can be a J shaped hole. | 09-18-2014 |
20140376309 | PHASE CHANGE MEMORY MATERIAL AND SYSTEM FOR EMBEDDED MEMORY APPLICATIONS - A family of phase change materials Ge | 12-25-2014 |
20150155236 | STACKED BIT LINE DUAL WORD LINE NONVOLATILE MEMORY - An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics. | 06-04-2015 |
20150214479 | MULTIPLE PHASE CHANGE MATERIALS IN AN INTEGRATED CIRCUIT FOR SYSTEM ON A CHIP APPLICATION - A device includes first and second pluralities of memory cells with memory elements and first and second capping materials on the first and second pluralities of memory cells. First and second capping materials can comprise lower and higher density silicon nitrides. The memory elements can include a programmable resistance memory material, and the capping materials can contact the memory elements. The first and second pluralities of memory cells can have a common cell structure. The first memory cells in the can comprise a top and bottom electrodes with a memory material therebetween and the first capping material contacting the memory material. Control circuits can apply different write algorithms to the first and second pluralities of memory cells. The first and second sets of memory cells can have different operational memory characteristics by forming the first and second capping layers using different capping materials but with the same cell structure. | 07-30-2015 |