Patent application number | Description | Published |
20110161682 | PROCESSOR VOLTAGE REGULATION - A voltage regulator module (VRM) includes a first interface configured to couple to a first substrate interface at a first voltage. The VRM also includes a second interface configured to couple to a first processor interface at a second voltage. A first regulator module couples to the first interface and to the second interface. The first regulator module is configured to receive power at the first interface, to convert power to the second voltage, and to deliver power to the first processor interface at the second voltage. A method for providing power to a processor includes receiving power from a first substrate interface at a first voltage. The received power is regulated to generate power at a second voltage. The regulated power is provided to a processor at a first processor interface coupled to the processor. The processor interface delivers power to a logic group of a plurality of logic groups of the processor. | 06-30-2011 |
20130268785 | Minimizing Power Consumption for Fixed-Frequency Processing Unit Operation - A mechanism is provided for minimizing power consumption for operation of a fixed-frequency processing unit. A number of timeslots are counted in a time window where throttling is engaged to the fixed-frequency processing unit. The number of timeslots where throttling is engaged is divided by a total number of timeslots within the time window, thereby producing a performance loss (PLOSS) value. A determination is made as to whether determining whether the (PLOSS) value associated with the fixed-frequency processing unit is greater than an allowed performance loss (APLOSS) value. Responsive to the PLOSS value being less than or equal to the APLOSS value, a decrease in voltage supplied to the fixed-frequency processing unit is initiated. | 10-10-2013 |
20130268786 | Minimizing Power Consumption for Fixed-Frequency Processing Unit Operation - A mechanism is provided for minimizing power consumption for operation of a fixed-frequency processing unit. A number of timeslots are counted in a time window where throttling is engaged to the fixed-frequency processing unit. The number of timeslots where throttling is engaged is divided by a total number of timeslots within the time window, thereby producing a performance loss (PLOSS) value. A determination is made as to whether determining whether the (PLOSS) value associated with the fixed-frequency processing unit is greater than an allowed performance loss (APLOSS) value. Responsive to the PLOSS value being less than or equal to the APLOSS value, a decrease in voltage supplied to the fixed-frequency processing unit is initiated. | 10-10-2013 |
20140157033 | REDUCING POWER GRID NOISE IN A PROCESSOR WHILE MINIMIZING PERFORMANCE LOSS - In the management of a processor, logical operation activity is monitored for increases from a low level to a high level during a sampling window across multiple cores sharing a common supply rail, with at least one decoupling capacitor along the common supply rail. Responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, the processor limits the logical operations executed on the cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level. Responsive to the lower activity period ending, the processor gradually decreases the limit on the logical operations to resume normal operations. | 06-05-2014 |
20140157277 | REDUCING POWER GRID NOISE IN A PROCESSOR WHILE MINIMIZING PERFORMANCE LOSS - In the management of a processor, logical operation activity is monitored for increases from a low level to a high level during a sampling window across multiple cores sharing a common supply rail, with at least one decoupling capacitor along the common supply rail. Responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, the processor limits the logical operations executed on the cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level. Responsive to the lower activity period ending, the processor gradually decreases the limit on the logical operations to resume normal operations. | 06-05-2014 |
Patent application number | Description | Published |
20090039441 | MOSFET WITH METAL GATE ELECTRODE - Devices comprising, and method for fabricating, a MOSFET with a metal gate electrode are disclosed. In one embodiment, the MOSFET includes a first doped region configured to receive current from a current source, a second doped region configured to drain current from the first doped region when an electric field is modified between the first doped region and the second doped region, and a gate electrode configured to modify the electric field. The gate electrode may include a high-k layer, a hafnium-based metal layer formed above the high-k layer, and a polysilicon layer formed above the hafnium-based metal layer. In a further embodiment, the gate electrode further comprises a titanium-based metal layer formed between the hafnium-based metal layer and the polysilicon layer. | 02-12-2009 |
20100052071 | ENGINEERED OXYGEN PROFILE IN METAL GATE ELECTRODE AND NITRIDED HIGH-K GATE DIELECTRICS STRUCTURE FOR HIGH PERFORMANCE PMOS DEVICES - A PMOS transistor is disclosed which includes a nitrogen containing barrier to oxygen diffusion between a gate dielectric layer and a metal gate in the PMOS transistor, in combination with a low oxygen region of the metal gate in direct contact with the nitrogen containing barrier and an oxygen rich region of the metal gate above the low oxygen content metal region. The nitrogen containing barrier may be formed by depositing nitrogen containing barrier material on the gate dielectric layer or by nitridating a top region of the gate dielectric layer. The oxygen rich region of the metal gate may be formed by depositing oxidized metal on the low oxygen region of the metal gate or by oxidizing a top region of the low oxygen region of the metal gate. | 03-04-2010 |
20120228715 | ENGINEERED OXYGEN PROFILE IN METAL GATE ELECTRODE AND NITRIDED HIGH-K GATE DIELECTRICS STRUCTURE FOR HIGH PERFORMANCE PMOS DEVICES - A PMOS transistor is disclosed which includes a nitrogen containing barrier to oxygen diffusion between a gate dielectric layer and a metal gate in the PMOS transistor, in combination with a low oxygen region of the metal gate in direct contact with the nitrogen containing barrier and an oxygen rich region of the metal gate above the low oxygen content metal region. The nitrogen containing barrier may be formed by depositing nitrogen containing barrier material on the gate dielectric layer or by nitridating a top region of the gate dielectric layer. The oxygen rich region of the metal gate may be formed by depositing oxidized metal on the low oxygen region of the metal gate or by oxidizing a top region of the low oxygen region of the metal gate. | 09-13-2012 |
20130313679 | INTEGRATED CIRCUIT WITH INTEGRATED DECOUPLING CAPACITORS - Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown. | 11-28-2013 |
Patent application number | Description | Published |
20080232054 | Multi-sectioned arms for portable electronic devices - Multi-sectioned arms are used as a basic mechanism for coupling the display and the base of a portable electronic device. With this mechanism, one single portable electronic device can support all of the following capabilities. The display can move continuously, relative to the back edge of the base, along any combination of up and down, left and right, and forward and backward directions. The display can be tilted up and down as well as sideways and also set to portrait and landscape orientations. The base can be tilted forward for typing comfort and better heat dispersion. There is also an anti-tipping mechanism. When the display is in conventional open or close positions, each arm can be folded and parked alongside, parallel to, and away from the edge of the base. The arms can be detached from the computer. The base and the display can overlay each other in four ways. | 09-25-2008 |
20110252628 | Multi-sectioned arms for portable electronic devices - Multi-sectioned arms are used as a basic mechanism for coupling the display and the base of a portable computer. With this mechanism, one single computer can support all of the following capabilities. The display can move continuously, relative to the back edge of the base, along any combination of up and down, backward and forward, and left and right directions. The display can be tilted up and down as well as sideway for viewing angle adjustment, and also set to portrait and landscape orientations. When the display is in conventional open or close positions, each arm can be folded and parked alongside and parallel to as well as away from the edge of the base. The arms can be detached from the computer. The base and the display can overlay each other in four ways. Finally, mechanical mechanisms for implementations of the arms and connections to the computer including friction joint mechanisms and attachment mechanisms for connecting the arm to the display and the base, are presented. A method of assembling the multi-sectioned arm is presented. | 10-20-2011 |