Patent application number | Description | Published |
20090060585 | IMAGE FORMING APPARATUS - A communication unit has a first conveyance part connected to a toner cartridge and provided with a feed port for a toner from the toner cartridge, and a second conveyance part connected to a developing device and provided with a replenishment port for a toner to the developing device. In a state locked by the lock mechanism, the first conveyance part and the second conveyance part are connected to each other, and the feed port of the first conveyance part and the replenishment port of the second conveyance part are opened, allowing for a toner replenishment. In a lock-released state, the feed port of the first conveyance part and the replenishment port of the second conveyance part are closed by a circular arc-shaped shutter member and a rotary shutter member, allowing the first conveyance part and the second conveyance part to be separable from each other. | 03-05-2009 |
20090169240 | DEVELOPING DEVICE, IMAGE FORMING APPARATUS USING THE SAME, AND METHOD FOR PEELING OFF SEALING MEMBER OF THE DEVELOPING DEVICE - A developing device includes a developer reservoir having developer stored therein, a developing roller for carrying developer, a sealing member which is brought into close contact with the developer portion so as to cover a communication port in communication with inside of the developer reservoir, and a sealing passing member for passing the sealing member peeled off the developer reservoir, wherein the sealing member is peeled off the developer reservoir to open the communication port and the sealing passing member has an opening with an approximately elliptical shape, through which the sealing member passes. | 07-02-2009 |
Patent application number | Description | Published |
20080232027 | SOLID ELECTROLYTIC CAPACITOR - Cathode electrode part | 09-25-2008 |
20090296318 | SOLID ELECTROLYTIC CAPACITOR - A solid electrolytic capacitor includes a negative terminal, first to fourth capacitor elements coupled to the negative terminal, first and second positive terminals connected to the first to fourth capacitor elements, and a package resin covering the first to fourth capacitor elements. Each of the first to fourth capacitor elements has a first end and a second end opposite to the first end, and each of the first to fourth capacitor elements includes a negative electrode provided at the first end and a positive electrode provided at the second end. The first to fourth capacitor elements are stacked in this order. The positive electrodes of the first and fourth capacitor elements extend in a first direction from the respective negative electrodes of the first and fourth capacitor elements. The positive electrodes of the second and third capacitor elements extend in a second direction, opposite to the first direction, from the respective negative electrodes of the second and third capacitor elements. This solid electrolytic capacitor has a small leakage current. | 12-03-2009 |
20130222977 | SOLID ELECTROLYTIC CAPACITOR - A solid electrolytic capacitor includes a capacitor element including a cathode portion and an anode portion, a cathode terminal bonded to the cathode portion, an anode terminal bonded to the anode portion, and an enclosure resin covering the capacitor element. The cathode terminal includes a cathode lower surface portion, a cathode connection portion, and a cathode support portion. The cathode connection portion is connected to an end portion of the cathode lower surface portion on an anode side and bonded to the cathode portion through a conductive adhesive. The cathode support portion is connected to a side portion of the cathode lower surface and brought into contact with a lower surface of the cathode portion on an end portion side of the cathode portion without involving the conductive adhesive therebetween. | 08-29-2013 |
20130329341 | ELECTROLYTIC CAPACITOR - An electrolytic capacitor includes a multilayered-capacitor-elements unit, a pair of positive electrode terminals, a negative electrode terminal, and an outer-package resin. The multilayered-capacitor-elements unit includes multiple capacitor elements of which positive electrodes are oriented oppositely to each other. The positive electrodes are connected to the positive electrode terminals, respectively, and negative electrodes of the capacitor elements are connected to the negative electrode terminal. Each of the positive electrode terminals includes a bottom section and a double-back section on which the positive electrodes of the capacitor element is disposed. The double-back section is formed by doubling over an end section extending toward the negative electrode. | 12-12-2013 |
Patent application number | Description | Published |
20140214375 | ARITHMETIC APPARATUS AND ARITHMETIC METHOD - An arithmetic method executed by a computer, the arithmetic method includes performing arithmetic operation to simulate conveyance of an object by a conveying device in a three-dimensional simulation space in which the object and the conveying device are disposed, the conveying device moving the object by pushing the object with a pushing-out surface of a pusher or lifting up the object by supporting the object from below with a supporting surface of a lifter, and moving the object to a position where the object is in contact with the pushing-out surface of the pusher or the supporting surface of the lifter when it is detected that a certain reference point of the object is present in a certain region in a moving direction of the pushing-out surface of the pusher or the supporting surface of the lifter in the arithmetic operation to simulate the conveyance. | 07-31-2014 |
20140214376 | ARITHMETIC DEVICE AND ARITHMETIC METHOD - A computer-readable recording medium stores therein a computer program. The computer program causes a computer to execute a process including: carrying out simulation computation of a simulation in which a conveyed object and a conveying device are arranged in a three-dimensional simulation space, the conveying device moving the conveyed object by pushing the conveyed object with a pushing surface of a pusher or lifting the conveyed object by supporting the conveyed object from below with a supporting surface of a lifter, and in which the conveying device conveys the conveyed object; and rotating, to carry out the simulation computation, the conveyed object around a predetermined reference point of the conveyed object when a distance between coordinates of the pushing surface of the pusher or coordinates of the supporting surface of the lifter and coordinates of the predetermined reference point is made equal to or smaller than a predetermined distance. | 07-31-2014 |
20140214384 | RECORDING MEDIUM, COMPUTING APPARATUS, AND COMPUTING METHOD - A computing method for a simulation in which an article, a conveyor, and a table are plotted in a three dimensional simulated space, and in which the conveyor conveys the article includes setting a priority representing a degree at which the lifter is handled as a single unit as the article higher than another priority representing a degree at which the table is handled as a single unit as the article when the lifter moves the article placed on the table upwardly, and setting the priority representing a degree at which the lifter is handled as a single unit as the article lower than the priority representing a degree at which the table is handled as a single unit as the article when the lifter conveying the article moves downwardly below the table. | 07-31-2014 |
Patent application number | Description | Published |
20100153923 | METHOD, COMPUTER PROGRAM AND COMPUTER SYSTEM FOR ASSISTING IN ANALYZING PROGRAM - A method for grouping algorithms included in a program into groups and thus for assisting in analyzing the program. The method includes the steps of: converting each of the algorithms into a directed graph; judging, as to each representative directed graph stored in a storage unit of a computer system, whether or not the directed graph obtained by the conversion is similar to the representative directed graph; and determining a group to which the directed graph obtained by the conversion belongs from among groups stored in the storage unit in accordance with the similarity judgment. A computer system for performing the above method and a computer program for causing a computer system to perform the above method are also described. | 06-17-2010 |
20110004869 | PROGRAM, APPARATUS, AND METHOD OF OPTIMIZING A JAVA OBJECT - An apparatus, method and article of manufacture tangibly embodying computer readable instructions for optimizing a Java object on a target computer program. The apparatus includes: a storage unit for storing a value of the object and management information on the object in association with each other; a code generation unit for generating, from the target computer program, optimized code and unoptimized code; a switching unit for switching from executing the target computer program using the optimized code to executing the target computer program using the unoptimized code in response to an event in which the value of the object is written while the target computer program is executed by using the optimized code; and a management unit for managing the object by accessing the management information by a non-detection write operation in which writing to the object is performed without being detected. | 01-06-2011 |
20120042306 | COMPILING SYSTEM AND METHOD FOR OPTIMIZING BINARY CODE - A compiling system and method for optimizing binary code. The method includes the step of replacing a memory access on a stack area in order to save a value of a register with local variable access. The method further includes: giving a call number to a call instruction and an inlined code in response to an inline expansion of a code to be called by the call instruction; creating a parent-child relationship information for at least one of the call number; processing the memory accesses with an escaped stack pointer as a base address if a stack pointer has escaped; prohibiting a replacement of a prohibited memory access if the stack pointer has escaped; and replacing unprohibited memory access with the local variable access if the stack pointer has escaped. | 02-16-2012 |
20130067431 | PROGRAM, APPARATUS, AND METHOD OF OPTIMIZING A JAVA OBJECT - An apparatus, method and article of manufacture tangibly embodying computer readable instructions for optimizing a Java object on a target computer program. The apparatus includes: a storage unit for storing a value of the object and management information on the object in association with each other; a code generation unit for generating, from the target computer program, optimized code and unoptimized code; a switching unit for switching from executing the target computer program using the optimized code to executing the target computer program using the unoptimized code in response to an event in which the value of the object is written while the target computer program is executed by using the optimized code; and a management unit for managing the object by accessing the management information by a non-detection write operation in which writing to the object is performed without being detected. | 03-14-2013 |
20130311981 | METHOD, PROGRAM, AND SYSTEM FOR CODE OPTIMIZATION - Method, program and system for code optimization. The method includes detecting a sign assignment instruction having an input operand and an output operand identical in size to each other. Analyzing and determining whether a value of the input operand results from an add or subtract operation and if the value is greater than the value prior to the operation. If so then removing the sign assignment instruction on the condition that the input operand and the output operand of the sign assignment instruction have their addresses identical to each other and replacing the sign assignment instruction with a copy instruction for copying the value of the input operand of the sign assignment instruction to a value of the output operand on the condition that the addresses of the input operand and the output operand of the sign assignment instruction are not identical and do not overlap each other. | 11-21-2013 |
20160062752 | METHOD, PROGRAM, AND SYSTEM FOR CODE OPTIMIZATION - Method, program and system for code optimization. A sign assignment instruction with identically sized packed decimal format input and output operands is detected where the sign assignment instruction assigns a value of zero to a packed decimal data value input operand having a value of negative zero. If the input operand to the sign assignment instruction does not result from an add or subtract operation, or the value of the input operand is not greater than a value prior to that operation, the possibility that the value of the input operand of the sign assignment instruction is negative zero is checked when the input operand and the output operand have identical addresses. An instruction is generated and inserted for executing the sign assignment instruction only when there is the possibility that the operand value is negative zero. | 03-03-2016 |
Patent application number | Description | Published |
20150268942 | CONTROLLING EXECUTION OF BINARY CODE - An apparatus for controlling an execution of a binary code by multiple threads includes a detection unit configured to detect an occurrence of modification of a first part that is a part of a first binary code by a self-modifying code; a specifying unit configured to specify a second part that is a part corresponding to the first part in a second binary code acquired by converting the first binary code, in response to detection of the occurrence of modification of the first part by the self-modifying code; and a correction unit configured to correct the second part such that a specific thread that executes the second part of the second binary code among the multiple threads causes an exception. | 09-24-2015 |
20150293754 | CONTROLLING EXECUTION OF BINARY CODE - An apparatus for controlling an execution of a binary code by multiple threads includes a detection unit configured to detect an occurrence of modification of a first part that is a part of a first binary code by a self-modifying code; a specifying unit configured to specify a second part that is a part corresponding to the first part in a second binary code acquired by converting the first binary code, in response to detection of the occurrence of modification of the first part by the self-modifying code; and a correction unit configured to correct the second part such that a specific thread that executes the second part of the second binary code among the multiple threads causes an exception. | 10-15-2015 |
20150324176 | OPTIMIZING IF STATEMENTS IN COMPUTER PROGRAMMING - A method for optimizing if statements in a program includes obtaining, by a processing device, for each of conditional expressions of a plurality of if statements in the program, a set of conditional expressions having an inclusion relation; computing, for each of the set, a position with low execution frequency in the program as a move destination of a conditional expression having an inclusion relation, using information of the set in which the conditional expression is included; and moving the conditional expression to the computed move destination of the conditional expression. | 11-12-2015 |
20150324177 | OPTIMIZING IF STATEMENTS IN COMPUTER PROGRAMMING - A method for optimizing if statements in a program includes obtaining, by a processing device, for each of conditional expressions of a plurality of if statements in the program, a set of conditional expressions having an inclusion relation; computing, for each of the set, a position with low execution frequency in the program as a move destination of a conditional expression having an inclusion relation, using information of the set in which the conditional expression is included; and moving the conditional expression to the computed move destination of the conditional expression. | 11-12-2015 |
Patent application number | Description | Published |
20120311550 | METHOD FOR OPTIMIZING BINARY CODES IN LANGUAGE HAVING ACCESS TO ZONED DECIMAL TYPE VARIABLE, OPTIMIZATION APPARATUS AND COMPUTER PROGRAM FOR THE SAME - An optimization technique for optimizing binary codes in a language having access to a zoned decimal type variable and applicable to binary codes including instructions which can cause side effects. The optimization technique includes: detecting, for each variable, an area including access to a zoned decimal type variable and not including an instruction that can cause a side effect, from the binary codes read into a memory; and performing, in the detected area, a process for converting a zoned decimal type variable to a binary type variable, a process for deleting such a pack/unpack code that a converted result does not change even in case the pack/unpack code is deleted, from the binary codes, or a process for performing combination of the processes. | 12-06-2012 |
20120317560 | METHOD FOR OPTIMIZING BINARY CODES IN LANGUAGE HAVING ACCESS TO ZONED DECIMAL TYPE VARIABLE, OPTIMIZATION APPARATUS AND COMPUTER PROGRAM FOR THE SAME - An optimization technique for optimizing binary codes in a language having access to a zoned decimal type variable and applicable to binary codes including instructions which can cause side effects. The optimization technique includes: detecting, for each variable, an area including access to a zoned decimal type variable and not including an instruction that can cause a side effect, from the binary codes read into a memory; and performing, in the detected area, a process for converting a zoned decimal type variable to a binary type variable, a process for deleting such a pack/unpack code that a converted result does not change even in case the pack/unpack code is deleted, from the binary codes, or a process for performing combination of the processes. | 12-13-2012 |
Patent application number | Description | Published |
20100076142 | Defoaming agent for water based paint - A defoaming agent which can effectively eliminate foams generated in the occasions of preparation, coating, drying and baking of water-based paint, by addition thereof by itself, without combined use of other kind(s) of defoaming agent(s), and furthermore without impairing appearance of baked coated film of the paint or recoatability of the paint is provided. Such a defoaming agent for water-based paint has the composition comprising (1) polyoxyethylene hydrogenated castor oil triisostearates and (2) polyalkyl vinyl ether, polybutadiene, polybutene or polyisoprene, which are dissolved in (3) liquid normal paraffin, liquid isoparaffin or liquid cycloparaffin, at such a ratio that the blended amount of (1) occupies 2-90% by weight of the total composition. | 03-25-2010 |
20120129996 | Defoaming Agent for Water-based Paint - A defoaming agent which can effectively eliminate foams generated in the occasions of preparation, coating, drying and baking of water-based paint, by addition thereof by itself, without combined use of other kind(s) of defoaming agent(s), and furthermore without impairing appearance of baked coated film of the paint or recoatability of the paint is provided. Such a defoaming agent for water-based paint has the composition comprising (1) polyoxyethylene hydrogenated castor oil triisostearates and (2) polyalkyl vinyl ether, polybutadiene, polybutene or polyisoprene, which are dissolved in (3) liquid normal paraffin, liquid isoparaffin or liquid cycloparaffin, at such a ratio that the blended amount of (1) occupies 2-90% by weight of the total composition. | 05-24-2012 |
Patent application number | Description | Published |
20090278716 | SAMPLE HOLD CIRCUIT FOR USE IN TIME-INTERLEAVED A/D CONVERTER APPARATUS INCLUDING PARALLELED LOW-SPEED PIPELINE A/D CONVERTERS - A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor. | 11-12-2009 |
20100073214 | DIFFERENTIAL OPERATIONAL AMPLIFIER CIRCUIT CORRECTING SETTLING ERROR FOR USE IN PIPELINED A/D CONVERTER - A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region. | 03-25-2010 |
20110031543 | IMAGING DEVICE BY BURIED PHOTODIODE STRUCTURE - An n-type region as a charge storage region of a photodiode is buried in a substrate. The interface between silicon and a silicon oxide film is covered with a high concentration p-layer and a lower concentration p-layer is formed only in the portion immediately below a floating electrode for signal extraction. Electrons generated by light are stored in the charge storage region, thereby changing the potential of the portion of the p-layer at the surface of the semiconductor region. The change is transmitted through a thin insulating film to the floating electrode by capacitive coupling and read out by a buffer transistor. Initialization of charges is executed by adding a positive high voltage to the gate electrode of a first transfer transistor such that the electrons stored in the charge storage region are transferred to the n+ region and generation of reset noise is protected. | 02-10-2011 |
20110193553 | Magnetic array sensor circuit to process an output from a magnetic sensor array - A magnetic array sensor circuit to process an output from a magnetic sensor array including a plurality of magnetic sensor elements arranged in an array. The circuit includes a regulating circuit to reduce an offset variation of the output from the magnetic sensor elements arranged in the array. | 08-11-2011 |
20120127004 | A/D CONVERSION INTEGRATED CIRCUIT - An A/D conversion integrated circuit including a plurality of A/D converters which can inhibit noises from being propagated by capacitive coupling from a conductor which transmits a digital signal is provided. In an A/D converter | 05-24-2012 |
20120193692 | SEMICONDUCTOR ELEMENT AND SOLID-STATE IMAGING DEVICE - A semiconductor element includes a base-body region of p-type; a charge-generation buried region of a n-type, implementing a photodiode together with the base-body region, configured to create a first potential valley in the base-body region; an accumulation region of n-type, being buried in a part of the upper portion of the base-body region, configured to create a second potential valley deeper than the first potential valley; a transfer-gate insulation film provided on a surface of the base-body region; a transfer-gate electrode provided on the transfer-gate insulation film, configured to control a potential of a transfer channel formed in the base-body region between the charge-generation buried region and the accumulation region; and a recessed-potential creation mechanism configured to create a stair-like-shaped potential barrier for electronic shuttering. | 08-02-2012 |
20120193743 | SEMICONDUCTOR ELEMENT AND SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes a semiconductor region of p-type; a buried region of n-type, configured to serve as a photodiode together with the semiconductor region; a extraction region of n-type, configured to extract charges generated by the photodiode from the buried region, having higher impurity concentration than the buried region; a read-out region of n-type, configured to accumulate charges, which are transferred from the buried region having higher impurity concentration than the buried region; and a potential gradient changing mechanism, configured to control a potential of the channel, and to change a potential gradient of a potential profile from the buried region to the read-out region and a potential gradient of a potential profile from the buried region to the extraction region, so as to control the transferring/extraction of charges. | 08-02-2012 |
20120301150 | OPTICAL-INFORMATION ACQUIRING ELEMENT, OPTICAL INFORMATION ACQUIRING ELEMENT ARRAY, AND HYBRID SOLID-STATE IMAGING DEVICE - A optical-information acquisition element encompasses a semiconductor layer ( | 11-29-2012 |
20130044247 | SOLID-STATE IMAGE PICKUP DEVICE, METHOD OF READING PIXEL SIGNAL, AND PIXEL - In a pixel | 02-21-2013 |
20130057418 | PIPELINED A/D CONVERTER CIRCUIT PROVIDED WITH A/D CONVERTER CIRCUIT PARTS OF STAGES EACH INCLUDING PRECHARGE CIRCUIT - A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal. | 03-07-2013 |
20130120180 | A/D CONVERTER - An A/D converter | 05-16-2013 |
20140014821 | A/D CONVERTER, IMAGE SENSOR DEVICE, AND METHOD OF GENERATING DIGITAL SIGNAL FROM ANALOG SIGNAL - According to this A/D converter, a first A/D conversion operation for performing integral A/D conversion and a second A/D conversion operation for performing cyclic A/D conversion are realized based on control of operational procedures in a same circuit configuration. Moreover, in the first A/D conversion operation, since a capacity of a capacitor used in the integration of an output signal is greater than a capacity of a capacitor used for storing an input analog signal and a standard reference voltage, the analog signal that is input in the integral A/D conversion is attenuated according to the capacity ratio and subject to sampling and integration. Consequently, the voltage range of the analog signal that is output in the integral A/D conversion also decreases according to the capacity ratio of the capacitors, and the A/D converter can be therefore constructed with a single-ended configuration. | 01-16-2014 |
20140232917 | SOLID STATE IMAGE PICK-UP DEVICE, AND PIXEL | 08-21-2014 |
20140319325 | LAMP SIGNAL GENERATION CIRCUIT AND CMOS IMAGE SENSOR - A ramp signal generation circuit | 10-30-2014 |
20150215549 | SOLID-STATE IMAGE PICKUP DEVICE - A solid-state image pickup device | 07-30-2015 |
Patent application number | Description | Published |
20090252978 | METHOD FOR METAL-RESIN JOINING AND A METAL-RESIN COMPOSITE, A METHOD FOR GLASS-RESIN JOINING AND A GLASS-RESIN COMPOSITE, AND A METHOD FOR CERAMIC-RESIN JOINING AND A CERAMIC-RESIN COMPOSITE - The present invention provides a method for joining a metallic material, a glass material or a ceramic material, and a resin material, that have no limitation in their field of application and that can form a strong joint by an easy method. The method for joining a metallic material, a glass material or a ceramic material, and a resin material is characterized in that joining is effected by heating a portion to be joined, in such a state that the metallic material, glass material or ceramic material is coupled with the resin material, to a temperature at which bubbles (preferably the sphere equivalent diameter from 0.01 mm to 5.0 mm) are generated in the resin material at the portion to be joined. As a heating source for heating the portion to be joined, a laser light source is used, especially. | 10-08-2009 |
20110095002 | LASER LAP WELDING METHOD FOR GALVANIZED STEEL SHEETS - A laser lap welding method, for a galvanized steel sheet, includes preparing two steel sheets in lap configuration, at least one of which is the galvanized steel sheet, so that a galvanized layer thereof is located at an interface of the steel sheets; and irradiating a surface of any one of the two steel sheets in an overlapped region with a laser to perform lap welding. The welding is performed by applying the laser to travel at a predetermined power density and at a predetermined traveling velocity so as to partially and temporarily form an elongated hole in a molten pool extending backward from a laser irradiation spot at least in the steel sheet on the surface side, whereby metal vapor produced by laser irradiation is vented through the elongated hole backward in a laser traveling direction and in a laser irradiation source side. | 04-28-2011 |