Patent application number | Description | Published |
20110027800 | Derivatives of 1,2-dihydro-7-hydroxyquinolines Containing Fused Rings - The present invention describes novel dyes, including coumarins, rhodamines, and rhodols that incorporate additional fused aromatic rings. The dyes of the invention absorb at a longer wavelength than structurally similar dyes that do not possess the fused aromatic rings. Many of the dyes of the invention are useful fluorescent dyes. The invention includes chemically reactive dyes, dye-conjugates, and the use of such dyes in staining samples and detecting ligands or other analytes. | 02-03-2011 |
20110086341 | FLUORINATED RESORUFIN COMPOUNDS AND THEIR APPLICATION - The invention provides novel fluorinated resorufin compounds that are of use in a variety of assay formats. Also provided are methods of using the compounds and kits that include a compound of the invention and instructions detailing the use of the compound in one or more assay formats. | 04-14-2011 |
20110236887 | MODIFIED ACTINOMYCIN-BASED NUCLEIC ACID STAINS AND METHODS OF THEIR USE - Actinomycin-based near IR emitting compounds and methods of their use as nucleic acid stains are provided. | 09-29-2011 |
20120004397 | VIOLET LASER EXCITABLE DYES AND THEIR METHOD OF USE - The present invention provides dye compounds optimally excited at about 400 nm and have a Stokes shift of at least about 80 nm. These dyes find use in detection of analyte in a sample and the preparation of dye-conjugates. | 01-05-2012 |
20120045848 | PYRENYLOXYSULFONIC ACID FLUORESCENT AGENTS - The invention provides a novel class of reactive fluorescent agents that are based on a pyrene sulfonic acid nucleus. The agents are readily incorporated into conjugates with other species by reacting the reactive group with a group of complementary reactivity on the other species of the conjugate. Also provided are methods of using the compounds of the invention to detect and/or quantify an analyte in a sample. In an exemplary embodiment, the invention provides multi-color assays incorporating the compounds of the invention. | 02-23-2012 |
20120315661 | Derivatives of 1,2-dihydro-7-hydroxyquinolines Containing Fused Rings - The present invention describes novel dyes, including coumarins, rhodamines, and rhodols that incorporate additional fused aromatic rings. The dyes of the invention absorb at a longer wavelength than structurally similar dyes that do not possess the fused aromatic rings. Many of the dyes of the invention are useful fluorescent dyes. The invention includes chemically reactive dyes, dye-conjugates, and the use of such dyes in staining samples and detecting ligands or other analytes. | 12-13-2012 |
20130079497 | PYRENYLOXYSULFONIC ACID FLUORESCENT AGENTS - The invention provides a novel class of reactive fluorescent agents that are based on a pyrene sulfonic acid nucleus. The agents are readily incorporated into conjugates with other species by reacting the reactive group with a group of complementary reactivity on the other species of the conjugate. Also provided are methods of using the compounds of the invention to detect and/or quantify an analyte in a sample. In an exemplary embodiment, the invention provides multi-color assays incorporating the compounds of the invention. | 03-28-2013 |
20130102014 | FLUORINATED RESORUFIN COMPOUNDS AND THEIR APPLICATION - The invention provides novel fluorinated resorufin compounds that are of use in a variety of assay formats. Also provided are methods of using the compounds and kits that include a compound of the invention and instructions detailing the use of the compound in one or more assay formats. | 04-25-2013 |
20130273569 | VIOLET LASER EXCITABLE DYES AND THEIR METHOD OF USE - The present invention provides dye compounds optimally excited at about 400 nm and have a Stokes shift of at least about 80 nm. These dyes find use in detection of analyte in a sample and the preparation of dye-conjugates. | 10-17-2013 |
Patent application number | Description | Published |
20130267084 | METHOD FOR FORMING SUPERACTIVE DEACTIVATION-RESISTANT JUNCTION WITH LASER ANNEAL AND MULTIPLE IMPLANTS - A pulsed-laser anneal technique includes performing an implant of a selected region of a semiconductor wafer. A co-constituent implant of the selected region is performed, and the pulsed-laser anneal of the selected region performed. A pre-amorphizing implant of the selected region can also be performed. In one embodiment, the implant of the selected region is performed as an insitu implant. In another embodiment, the co-constituent implant is performed as an insitu non-donor implant. In yet another embodiment, the implant and the co-constituent implant of the selected region are performed as an insitu donor and co-constituent implant. | 10-10-2013 |
20130288438 | SELECTIVE LASER ANNEALING PROCESS FOR BURIED REGIONS IN A MOS DEVICE - Laser anneal to melt regions of a microelectronic device buried under overlying materials, such as an interlayer dielectric (ILD). Melting temperature differentiation is employed to selectively melt a buried region. In embodiments a buried region is at least one of a gate electrode and a source/drain region. Laser anneal may be performed after contact formation with contact metal coupling energy into the buried layer for the anneal. | 10-31-2013 |
20140070320 | INTEGRATED CIRCUITS WITH SELECTIVE GATE ELECTRODE RECESS - Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit. | 03-13-2014 |
20150060945 | TRANSISTORS WITH HIGH CONCENTRATION OF BORON DOPED GERMANIUM - Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm | 03-05-2015 |
20150079776 | INTEGRATED CIRCUITS WITH SELECTIVE GATE ELECTRODE RECESS - Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit. | 03-19-2015 |
20150155384 | ENHANCED DISLOCATION STRESS TRANSISTOR - A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation. | 06-04-2015 |
20150200301 | PULSED LASER ANNEAL PROCESS FOR TRANSISTORS WITH PARTIAL MELT OF A RAISED SOURCE-DRAIN - A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth. | 07-16-2015 |
Patent application number | Description | Published |
20140092003 | DIRECT HAPTIC FEEDBACK - An electronic device comprises an input device and logic to register one or more input events and one or more haptic effects associated with the one or more input events for an application on an electronic device, receive an input event, retrieve one or more haptics effects, and pass the one or more haptics effects associated with the input event to a haptics actuator. Other embodiments may be described. | 04-03-2014 |
20140184502 | PORTABLE DEVICE WITH DISPLAY MANAGEMENT BASED ON USER INTENT INTELLIGENCE - The claimed subject matter provides a system for enhancing user experience while conserving power in a portable device. The system includes logic to: determine whether a portable electronic device is being held for viewing; and maintain performance of a display of the portable electronic device at least partially in response to a determination that the portable electronic device is being held for viewing. | 07-03-2014 |
20150077139 | MULTI-DIMENSIONAL ELECTRODES FOR CAPACITIVE SENSING - Techniques for three dimensional capacitive sensing are described herein. The techniques include a system including a three dimensional transmitting electrode to emit charge having an electric field. The system may include a three dimensional receiving electrode to receive the charge creating a capacitance between the transmitting electrode and the receiving electrode. | 03-19-2015 |
20150084875 | ENHANCED HAPTIC FEEDBACK FOR HANDHELD MOBILE COMPUTING DEVICES - Embodiments of the invention describe systems, apparatuses and methods for providing enhanced haptic feedback for handheld mobile computing devices. Embodiments of the invention detect a user touch input on a touchscreen input/output (I/O) interface of a handheld mobile computing device. One or more characteristics of the user touch input are determined, including one or more of a duration of the user touch input, a direction of the user touch input, or a force applied during the user touch input. A control signal comprising one or more pulses is generated to drive one or more actuators included in the handheld mobile computing device to generate an adjustable haptic effect, wherein the control signal is generated based, at least in part, on the determined one or more characteristics of the user touch input. | 03-26-2015 |
20150094031 | NOTIFICATION ACKNOWLEDGEMENT IN ELECTRONIC DEVICES - In one example a controller comprises logic, at least partially including hardware logic, configured to receive a notification of an incoming event and terminate the notification in response to at least one of a predetermined motion applied to the controller or a predetermined touch applied to a touch surface. Other examples may be described. | 04-02-2015 |
20150145805 | DETECTING GESTURES ON THE SIDE OF A COMPUTING DEVICE - Embodiments of apparatus and methods for detecting gestures are described. In embodiments, an apparatus may include a transmitter-receiver electrode arrangement to generate an electric field projecting beyond a side of a computing device, so that changes to the electric field caused by user gestures on or near the outer surface of the side may be sensed. The transmitter-receiver electrode arrangement may include at least a transmitter and a receiver that are different, but complementary in geometry and disposition, disposed relative to an inner surface of the side of the computing device. Moreover, a capacitive sensor may be disposed in the computing device to output electrical signals indicative of changes to the electric field sensed. Other embodiments may be described and/or claimed. | 05-28-2015 |
20150153840 | COMPUTING SYSTEMS FOR PERIPHERAL CONTROL - Embodiments of computing systems, and related methods, are disclosed herein. In some embodiments, a computing system may include a peripheral device (e.g., an image capture device and/or an audio output device) and control logic. The control logic may be coupled with a sensor system and the peripheral device to receive a trigger signal; receive, from the sensor system, one or more interaction signals indicative of a user interaction with the computing system; and, in response to receipt of the trigger signal and the one or more interaction signals, generate a control signal for output to the peripheral device to control operation of the peripheral device. Other embodiments may be disclosed and/or claimed. | 06-04-2015 |
20150261366 | MECHANISM FOR FACILITATING FLEXIBLE WRAPAROUND DISPLAYS FOR COMPUTING DEVICES - A mechanism is described for facilitating flexible wraparound displays at computing devices according to one embodiment. A method of embodiments, as described herein, includes placing a flexible wraparound display at a computing device, where the flexible wraparound display being represented as a single display that is flexibly wrapped around the computing device. The method may further include calibrating the flexible wraparound display for performing its functions using one or more default components of the computing device. | 09-17-2015 |
Patent application number | Description | Published |
20080244195 | METHODS AND APPARATUSES TO SUPPORT MEMORY TRANSACTIONS USING PARTIAL PHYSICAL ADDRESSES - Methods and apparatuses to support memory transactions using partial physical addresses are disclosed. Method embodiments generally comprise home agents monitoring multiple responses to multiple memory requests, wherein at least one of the responses has a partial address for a memory line, resolving conflicts for the memory requ'fvests, and suspending conflict resolution for the memory requests which match partial address responses until determining the full address. Apparatus embodiments generally comprise a home agent having a response monitor and a conflict resolver. The response monitor may observe a snoop response of a memory agent, wherein the snoop response only has a partial address and is for a memory line of a memory agent. The conflict resolver may suspend conflict resolution for memory transactions which match the partial address of the memory line until the conflict resolver receives a full address for the memory line. | 10-02-2008 |
20090006871 | METHOD, SYSTEM, AND APPARATUS FOR A CORE ACTIVITY DETECTOR TO FACILITATE DYNAMIC POWER MANAGEMENT IN A DISTRIBUTED SYSTEM - A system and method to provide source controlled dynamic power management. An activity detector in a source determines expected future resource usage. Based on that expected usage, the source generates a power management command and sends that command to a destination. The destination then adjusts the power level of the resource based in the command. | 01-01-2009 |
20120079032 | APPARATUS, SYSTEM, AND METHODS FOR FACILITATING ONE-WAY ORDERING OF MESSAGES - Methods, apparatus and systems for facilitating one-way ordering of otherwise independent message classes. A one-way message ordering mechanism facilitates one-way ordering of messages of different message classes sent between interconnects employing independent pathways for the message classes. In one aspect, messages of a second message class may not pass messages of a first message class. Moreover, when messages of the first and second classes are received in sequence, the ordering mechanism ensures that messages of the first class are forwarded to, and received at, a next hop prior to forwarding messages of the second class. | 03-29-2012 |
20120089850 | Optimizing Power Usage By Factoring Processor Architectural Events To PMU - A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit. | 04-12-2012 |
20130031400 | OPTIMIZING POWER USAGE BY PROCESSOR CORES BASED ON ARCHITECTURAL EVENTS - A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit. | 01-31-2013 |
20130151782 | Providing Common Caching Agent For Core And Integrated Input/Output (IO) Module - In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed. | 06-13-2013 |
20130151930 | Injecting A Data Error Into A Writeback Path To Memory - In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed. | 06-13-2013 |
20130254572 | OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU - A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit. | 09-26-2013 |
20140112339 | HIGH PERFORMANCE INTERCONNECT - A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state | 04-24-2014 |
20140164799 | OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU - A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit. | 06-12-2014 |
20140201463 | HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL - A request is received that is to reference a first agent and to request a particular line of memory to be cached in an exclusive state. A snoop request is sent intended for one or more other agents. A snoop response is received that is to reference a second agent, the snoop response to include a writeback to memory of a modified cache line that is to correspond to the particular line of memory. A complete is sent to be addressed to the first agent, wherein the complete is to include data of the particular line of memory based on the writeback. | 07-17-2014 |
20140214955 | APPARATUS, SYSTEM, AND METHODS FOR FACILITATINGONE-WAY ORDERING OF MESSAGES - Methods, apparatus and systems for facilitating one-way ordering of otherwise independent message classes. A one-way message ordering mechanism facilitates one-way ordering of messages of different message classes sent between interconnects employing independent pathways for the message classes. In one aspect, messages of a second message class may not pass messages of a first message class. Moreover, when messages of the first and second classes are received in sequence, the ordering mechanism ensures that messages of the first class are forwarded to, and received at, a next hop prior to forwarding messages of the second class. | 07-31-2014 |
20150081984 | HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL - A request is received that is to reference a first agent and to request a particular line of memory to be cached in an exclusive state. A snoop request is sent intended for one or more other agents. A snoop response is received that is to reference a second agent, the snoop response to include a writeback to memory of a modified cache line that is to correspond to the particular line of memory. A complete is sent to be addressed to the first agent, wherein the complete is to include data of the particular line of memory based on the writeback. | 03-19-2015 |
20150095580 | SCALABLY MECHANISM TO IMPLEMENT AN INSTRUCTION THAT MONITORS FOR WRITES TO AN ADDRESS - A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored. | 04-02-2015 |
20150127907 | METHOD, APPARATUS AND SYSTEM FOR HANDLING CACHE MISSES IN A PROCESSOR - In an embodiment, a processor includes one or more cores, and a distributed caching home agent (including portions associated with each core). Each portion includes a cache controller to receive a read request for data and, responsive to the data not being present in a cache memory associated with the cache controller, to issue a memory request to a memory controller to request the data in parallel with communication of the memory request to a home agent, where the home agent is to receive the memory request from the cache controller and to reserve an entry for the memory request. Other embodiments are described and claimed. | 05-07-2015 |
20150127962 | OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU - A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit. | 05-07-2015 |
20150128142 | VIRTUAL RETRY QUEUE - A starvation mode is entered and a particular dependency of a first request in a retry queue is identified. The particular dependency is determined to be acquired and the first request is retried based on acquisition of the particular dependency. | 05-07-2015 |
20150143051 | Providing Common Caching Agent For Core And Integrated Input/Output (IO) Module - In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed. | 05-21-2015 |
20150178202 | METHOD AND APPARATUS FOR CACHE LINE WRITE BACK OPERATION - An apparatus and method are described for performing a cache line write back operation. For example, one embodiment of a method comprises: initiating a cache line write back operation directed to a particular linear address; determining if a dirty cache line identified by the linear address exists at any cache of a cache hierarchy comprised of a plurality of cache levels; writing back the dirty cache line to memory if the dirty cache line exists in one of the caches; and responsively maintaining or placing the dirty cache line in an exclusive state in at least a first cache of the hierarchy. | 06-25-2015 |
20150178206 | CACHE COHERENCY APPARATUS AND METHOD MINIMIZING MEMORY WRITEBACK OPERATIONS - An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M′) state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache. | 06-25-2015 |
20150186191 | DEADLOCK PREVENTION IN A PROCESSOR - Disclosed herein is a caching agent for preventing deadlock in a processor. The caching agent includes a receiver configured to receive a request from a core of the processor. The caching agent includes ingress logic coupled to the receiver to determine that the request is potentially a cacheable request. The ingress logic is to determine that the request does not deplete an available coherence resource. The ingress logic is to allow the request to be processed in response to the determination that the request does not deplete the available coherence resource. | 07-02-2015 |
20150186275 | Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near Memory Reads On Cache Line Memory Writes Into A Two Level System Memory - A processor is described that includes one or more processing cores. The processing core includes a memory controller to interface with a system memory having a near memory and a far memory. The processing core includes a plurality of caching levels above the memory controller. The processor includes logic circuitry to track state information of a cache line that is cached in one of the caching levels. The state information including a selected one of an inclusive state and a non inclusive state. The inclusive state indicates that a copy or version of the cache line exists in near memory. The non inclusive states indicates that a copy or version of the cache line does not exist in the near memory. The logic circuitry is to cause the memory controller to handle a write request that requests a direct write into the near memory without a read of the near memory beforehand if a system memory write request generated within the processor targets the cache line when the cache line is in the inclusive state. | 07-02-2015 |
20150269104 | RING PROTOCOL FOR LOW LATENCY INTERCONNECT SWITCH - Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's. | 09-24-2015 |