Patent application number | Description | Published |
20090316498 | CIRCUIT AND METHOD FOR VDD-TRACKING CVDD VOLTAGE SUPPLY - Circuit and methods for providing the CVDD supply to the cells in an SRAM array while maintaining a desired VDD voltage. A circuit is described for tracking the VDD supply voltage and providing a CVDD supply for the SRAM cells that maintains an offset above VDD until a maximum voltage for the CVDD voltage is reached. The CVDD voltage supplies the word line drivers and the cells in an SRAM array, while the bit line precharge and the remaining circuitry is operated on the VDD supply. By maintaining a maximum offset between the voltage CVDD and the supply voltage VDD, the SRAM will have the required static noise margins for reliable operation, while a lowered VDD_min voltage may also be obtained. A method for supplying a CVDD voltage to an SRAM cell array is disclosed where the CVDD voltage tracks a VDD supply voltage plus a predetermined offset voltage. | 12-24-2009 |
20100080045 | ROBUST 8T SRAM CELL - This invention discloses a static random access memory (SRAM) cell which comprises a pair of cross-coupled inverters having a first storage node, a first NMOS transistor having a source and a drain connected between the first storage node and a bit-line, a second NMOS transistor having a source and a drain connected between a gate of the first NMOS transistor and a word-line, the second NMOS transistor having a gate connected to a first column select line, and a third NMOS transistor having a source and a drain connected between a ground (VSS) and the gate of the first NMOS transistor, and a gate connected to a second column select line, the second column select line being complementary to the first column select line. | 04-01-2010 |
20100123505 | ULTRA-LOW VOLTAGE LEVEL SHIFTING CIRCUIT - A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, the first blocking device being configured to conduct active current when the first signal is in static state or transitions from a logic HIGH to a logic LOW, and the first blocking device being configured to shut off active current when the first signal transitions from the logic LOW to the logic HIGH. | 05-20-2010 |
20100124099 | 8T LOW LEAKAGE SRAM CELL - This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters having a storage node, and a NMOS transistor having a gate terminal, a first and a second source/drain terminal connected to the storage node, a read word-line (RWL) and a read bit-line (RBL), respectively, the RWL and RBL being activated during a read operation and not being activated during any write operation. | 05-20-2010 |
20100157692 | Distributed VDC for SRAM Memory - An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected. | 06-24-2010 |
20100214863 | MEMORY POWER GATING CIRCUIT AND METHODS - A power gating circuit configured to couple with a memory array having an internal voltage, wherein the power gating circuit includes circuitry having an output signal that raises the internal voltage of the memory array if the internal voltage is lower than a first threshold voltage, and lowers the internal voltage if the internal voltage is higher than a second threshold voltage, thereby retaining the internal voltage between the first threshold voltage and the second threshold voltage. | 08-26-2010 |
20100278002 | CIRCUIT AND METHOD OF PROVIDING CURRENT COMPENSATION - Some embodiments regard a method comprising: during a leakage sampling phase, recognizing a voltage level dropped due to a leakage current associated with a signal linestoring the voltage level; and during a reading phase, using the voltage level to provide an amount of compensation current to the signal line. | 11-04-2010 |
20110007596 | Low-Leakage Power Supply Architecture for an SRAM Array - A method of forming an integrated circuit structure includes providing a chip; forming a static random access memory (SRAM) cell including a transistor on the chip; and forming a bias transistor configured to gate a power supply voltage provided to the SRAM cell on the chip. The bias transistor and the transistor of the SRAM cell are formed simultaneously. | 01-13-2011 |
20110080798 | Digital Retention Voltage Generation - A first embodiment of the present invention is a system for generating a voltage comprising a comparator operable to compare an operation voltage to a reference voltage, control logic operable to selectively output as a control signal an incremented signal or a decremented signal based on a comparison of the operation voltage to the reference voltage by the comparator, and a device module operable to increase or decrease the operation voltage based on the control signal. | 04-07-2011 |
20110199847 | SENSE AMPLIFIER WITH LOW SENSING MARGIN AND HIGH DEVICE VARIATION TOLERANCE - In an embodiment related to a sense amplifier, the sense amplifier includes a pair of transistors (e.g., transistors P | 08-18-2011 |
20110209109 | HIGH-SPEED SRAM - A method includes a) receiving a design for a static random access memory (SRAM) array including an SRAM cell having a read port cell, the read port cell including first and second MOS transistors each having an initial threshold voltage (Vth); b) adjusting one of a gate channel width (Wg) or a gate channel length (Lg) of one of the first and second MOS transistors to modify the Vth of at least one of the first and second MOS transistors; c) simulating a response of the SRAM array, the simulation providing response data for the SRAM array including the Vth for the first and second MOS transistors; and d) iteratively repeating steps b) and c) until a desired Vth is achieved. | 08-25-2011 |
20110267901 | SWITCHED CAPACITOR BASED NEGATIVE BITLINE VOLTAGE GENERATION SCHEME - A memory device includes an array of memory cells, the memory device including a bitline biasing circuit for biasing a bitline during a write operation. The bitline biasing circuit operating to provide a negative biasing voltage to the bitline. The magnitude of the negative biasing voltage is inversely proportional to a memory cell supply voltage level provided at a memory cell supply voltage node. | 11-03-2011 |
20110292754 | MEMORY WORD-LINE DRIVER HAVING REDUCED POWER CONSUMPTION - A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit. | 12-01-2011 |
20120037997 | METHOD AND APPARATUS FOR WORD LINE DRIVER WITH DECREASED GATE RESISTANCE - A semiconductor device comprises first, second, and third. The first conductor is a gate conductor formed above an oxide region over a substrate and having a contact. The second conductor is coupled to the contact and extends across a width of the oxide region. The second conductor has a lower resistance than the gate conductor. The third conductor is a word line conductor. The second conductor is routed to not intersect the word line conductor. | 02-16-2012 |
20120099382 | READING MEMORY DATA - A circuit includes a reference data line configured to receive a reference voltage value, a memory cell, a data line coupled to the memory cell and configured to have a data logic value associated with data stored in the memory cell, a first circuit coupled to the reference data line and to the data line, and an output node configured to selectively receive the data logic value from the data line or receive the data logic value through the first circuit, based on the reference voltage value and a trip point used to trigger the first circuit to provide the data logic value through the first circuit. | 04-26-2012 |
20120181707 | Distributed Metal Routing - A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias. | 07-19-2012 |
20120195106 | SRAM Timing Cell Apparatus and Methods - Apparatus and methods for providing SRAM timing tracking cell circuits are disclosed. In an embodiment, an apparatus comprises an SRAM array comprising static random access memory cells arranged in rows and columns; a plurality of word lines each coupled to memory cells along one of the rows; a clock generation circuit for outputting clock signals; a word line generation circuit for generating a pulse on the plurality of word lines responsive to one of the clock signals and for ending the pulse responsive to one of the clock signals; and a tracking cell for receiving a clock signal and for outputting a word line pulse end signal to the clock generation circuit, following an SRAM tracking time; wherein the tracking cell further comprises SRAM tracking circuits positioned in the SRAM array and coupled in series to provide a signal indicating the SRAM tracking time. Methods for SRAM timing are disclosed. | 08-02-2012 |
20120236675 | Methods and Apparatus for Memory Word Line Driver - A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed. | 09-20-2012 |
20120253775 | Multidimensional Monte-Carlo Simulation for Yield Prediction - An embodiment includes a computer program product for providing a yield prediction. The computer program product has a non-transitory computer readable medium with a computer program embodied thereon. The computer program comprises computer program code for obtaining a representation of a circuit. The circuit comprises a common path and a critical path, and the critical path represents multiple parallel paths. The computer program further comprises computer program code for obtaining a first table representing the common path and a second table representing the multiple parallel paths and computer program code for performing a variable based simulation based on the representation of the circuit, the first table, and the second table. The computer program also comprises computer program code for determining a result indication of each of the multiple parallel paths based on the variable based simulation compared with a predetermined specification. | 10-04-2012 |
20120306537 | ULTRA-LOW VOLTAGE LEVEL SHIFTING CIRCUIT - A voltage level shifter having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) includes a first PMOS transistor and a second PMOS transistor each with a source connected to the VCCH, a gate of the first PMOS transistor being coupled to a drain of the second PMOS transistor, and a gate of the second PMOS transistor being coupled to a drain of the first PMOS transistor. The voltage level shifter further includes a first NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, such that the voltage level shifter can operate at a lower VCCL. | 12-06-2012 |
20120313177 | Multiple Finger Structure - A multiple finger structure comprises a plurality of active regions placed between a pair of dummy POLY lines. The active regions comprise a plurality of multiple fingered NMOS transistors, which are part of a sense amplifier of an SRAM memory circuit. The drain and source of each multiple fingered NMOS transistor have an SiP/SiC epitaxial growth region. The active regions extend and overlap with the dummy POLY lines. The overlap between the active regions and the dummy POLY lines helps to reduce edge imperfection at the edge of the active regions. | 12-13-2012 |
20120327730 | SRAM Differential Voltage Sensing Apparatus - An SRAM differential voltage sensing apparatus is coupled to a memory circuit. The memory circuit comprises a memory bank, a plurality of bit lines, a plurality of data lines coupled to the plurality of bit lines via a plurality of transmission gates and a sense amplifier. When the sense amplifier operates in a characterization mode, the transmission gates and pre-charge circuits are turned off. The differential voltage sensing apparatus applies a characterization signal to the sense amplifier and obtains the parameters of the memory circuit through a trial and error process. | 12-27-2012 |
20130019218 | HIGH-SPEED SRAM - A method includes a) receiving a design for a static random access memory (SRAM) array including an SRAM cell having a read port cell, the read port cell including first and second MOS transistors each having an initial threshold voltage (Vth); b) adjusting one of a gate channel width (Wg) or a gate channel length (Lg) of one of the first and second MOS transistors to modify the Vth of at least one of the first and second MOS transistors; c) simulating a response of the SRAM array, the simulation providing response data for the SRAM array including the Vth for the first and second MOS transistors; and d) iteratively repeating steps b) and c) until a desired Vth is achieved. | 01-17-2013 |
20130194880 | READING MEMORY DATA - A circuit includes a memory array comprising K number of rows. The circuit further including a reference column. The reference column includes M cells of a first cell type configured to provide a first leakage current, K-M cells of a second cell type different from the first cell type, the K-M cells are configured to provide a second leakage current, and a reference data line connected to the cells of the first cell type and the cells of the second cell type. The circuit further includes a sensing circuit configured to determine a value stored in a memory cell of the memory array based on a voltage of the reference data line. | 08-01-2013 |
20140073124 | EDGE DEVICES LAYOUT FOR IMPROVED PERFORMANCE - A method includes forming a first plurality of fingers over an active area of a semiconductor substrate. Each of the first plurality of fingers has a respective length that extends in a direction that is parallel to width direction of the active area. The first plurality of fingers form at least one gate of at least one transistor having a source and a drain formed by a portion of the active area. A first dummy polysilicon structure is formed over a portion of the active area between an outer one of the first plurality of fingers and a first edge of the semiconductor substrate. A second dummy polysilicon structure is over the semiconductor substrate between the first dummy polysilicon structure and the first edge of the semiconductor substrate. | 03-13-2014 |
20140118869 | ESD Protection Scheme Using I/O Pads - Some embodiments relate to an IC that includes an ESD-susceptible circuit. The IC includes a number of IC pads that are electrically coupled to respective nodes on the ESD-susceptible circuit. The IC pads are electrically accessible from external to the IC, and include one or more power supply pads and one or more I/O pads. The IC also includes a number of ESD protection devices coupled to the plurality of IC pads, respectively. A trigger circuit on the IC is configured to detect an ESD event impingent on a power supply pad and, in response to the detection, to trigger concurrent shunting of energy of the ESD event over both an ESD clamp element of an I/O pad and an ESD clamp element of the power supply pad. Other embodiments are also disclosed. | 05-01-2014 |
20140198555 | Methods and Apparatus for ROM Devices - Methods and apparatus for the encoding of an input sequence of digit data into a sequence of storage cells of a ROM device are disclosed. The input sequence is divided into a first kind of groups and a second kind of groups. A first kind of group comprises a plurality of consecutive first digits, two first kind of groups are separated by a second kind of group, the second kind of group comprises consecutive digits without any consecutive first digits, and the second kind of group has a starting digit which is the second digit. A starting storage cell is programmed to the active state to store the starting digit of the second kind of group. The rest digits of the second kind of group are programmed one digit at a time, based on a shared terminal which has been programmed for the proceeding storage cell. | 07-17-2014 |
20140247672 | READING MEMORY DATA - A circuit includes one or more memory cells, a data line associated with the one or more memory cells, one or more reference cells, a reference data line associated with the one or more reference cells, a first circuit coupled to the reference data line and the data line, and a second circuit. The first circuit is configured to output a first logical value based on a voltage level of the data line upon occurrence of a voltage level of the reference data line reaching a trip point. The second circuit is configured to output a second logical value based on the voltage level on the data line prior to the occurrence of the voltage level of the reference data line reaching the trip point, and to output the first logical value after the occurrence of the voltage level of the reference data line reaching the trip point. | 09-04-2014 |