Patent application number | Description | Published |
20100108502 | Sputtering Target and Oxide Semiconductor Film - A sputtering target containing oxides of indium (In), gallium (Ga) and zinc (Zn), which includes a compound shown by ZnGa | 05-06-2010 |
20100127256 | SEMICONDUCTOR THIN FILM, SEMICONDUCTOR THIN FILM MANUFACTURING METHOD AND SEMICONDUCTOR ELEMENT - An amorphous oxide thin film containing amorphous oxide is exposed to an oxygen plasma generated by exciting an oxygen-containing gas in high frequency. The oxygen plasma is preferably generated under the condition that applied frequency is 1 kHz or more and 300 MHz or less and pressure is 5 Pa or more. The amorphous oxide thin film is preferably exposed by a sputtering method, ion-plating method, vacuum deposition method, sol-gel method or fine particle application method. | 05-27-2010 |
20110006297 | PATTERNED CRYSTALLINE SEMICONDUCTOR THIN FILM, METHOD FOR PRODUCING THIN FILM TRANSISTOR AND FIELD EFFECT TRANSISTOR - A patterned crystalline semiconductor thin film which is obtained by a method including: forming an amorphous thin film comprising indium oxide as a main component, crystallizing part of the amorphous thin film to allow the part to be semiconductive, and removing an amorphous part of the partially crystallized thin film by etching. | 01-13-2011 |
20110050733 | THIN FILM TRANSISTOR MANUFACTURING METHOD, THIN FILM TRANSISTOR, THIN FILM TRANSISTOR SUBSTRATE AND IMAGE DISPLAY APPARATUS, IMAGE DISPLAY APPARATUS AND SEMICONDUCTOR DEVICE - To provide a method for producing a thin film transistor improved in stability, uniformity, reproducibility, heat resistance, durability or the like, a thin film transistor, a thin film transistor substrate, an image display apparatus, an image display apparatus and a semiconductor device. | 03-03-2011 |
20110168994 | SPUTTERING TARGET FOR OXIDE THIN FILM AND PROCESS FOR PRODUCING THE SPUTTERING TARGET - Disclosed is a sputtering target that can suppress the occurrence of anomalous discharge in the formation of an oxide semiconductor film by sputtering method and can continuously and stably form a film. Also disclosed is an oxide for a sputtering target that has a rare earth oxide C-type crystal structure and has a surface free from white spots (a poor appearance such as concaves and convexes formed on the surface of the sputtering target). Further disclosed is an oxide sintered compact that has a bixbyite structure and contains indium oxide, gallium oxide, and zinc oxide. The composition amounts (atomic %) of indium (In), gallium (Ga), and zinc (Zn) fall within a composition range satisfying the following formula: In/(In+Ga+Zn)<0.75 | 07-14-2011 |
20110180763 | OXIDE SINTERED BODY AND SPUTTERING TARGET - An oxide sintered body includes indium oxide and gallium solid-solved therein, the oxide sintered body having an atomic ratio “Ga/(Ga+In)” of 0.001 to 0.12, containing indium and gallium in an amount of 80 atom % or more based on total metal atoms, and having an In | 07-28-2011 |
20110198586 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING SAME - A thin film transistor including a gate electrode, a gate-insulating film, an oxide semiconductor film in contact with the gate-insulating film, and source and drain electrodes which connect to the oxide semiconductor film and are separated with a channel part therebetween, wherein the oxide semiconductor film comprises a crystalline indium oxide which includes hydrogen element, and the content of the hydrogen element contained in the oxide semiconductor film is 0.1 at % to 5 at % relative to all elements which form the oxide semiconductor film. | 08-18-2011 |
20110243835 | INDIUM OXIDE SINTERED COMPACT AND SPUTTERING TARGET - A sintered body includes an indium oxide crystal, and an oxide solid-dissolved in the indium oxide crystal, the oxide being oxide of one or more metals selected from the group consisting of aluminum and scandium, the sintered body having an atomic ratio “(total of the one or more metals)/(total of the one or more metals and indium)×100)” of 0.001% or more and less than 45%. | 10-06-2011 |
20110260157 | SEMICONDUCTOR DEVICE, THIN FILM TRANSISTOR AND A METHOD FOR PRODUCING THE SAME - A semiconductor device, a thin film transistor, and a method for producing the same capable of decreasing the management cost, and capable of decreasing the production steps to reduce the production cost are proposed. A method for producing a thin film transistor | 10-27-2011 |
20140001040 | SPUTTERING TARGET AND OXIDE SEMICONDUCTOR FILM | 01-02-2014 |
20140167033 | OXIDE SINTERED BODY AND SPUTTERING TARGET - An oxide sintered body includes indium oxide and gallium solid-solved therein, the oxide sintered body having an atomic ratio “Ga/(Ga+In)” of 0.001 to 0.12, containing indium and gallium in an amount of 80 atom % or more based on total metal atoms, and having an In | 06-19-2014 |
20140339073 | Sputtering Target and Oxide Semiconductor Film - A sputtering target containing oxides of indium (In), gallium (Ga) and zinc (Zn), which includes a compound shown by ZnGa | 11-20-2014 |
Patent application number | Description | Published |
20100121204 | BLOOD VESSEL STATE EVALUATING DEVICE, BLOOD VESSEL STATE EVALUATING METHOD, AND COMPUTER-READABLE RECORDING MEDIUM STORING BLOOD VESSEL STATE EVALUATING PROGRAM - A phase line tilt calculating unit (actual measurement) receives phase characteristics Pa(f) and Pb(f) outputted from frequency conversion units, and calculates phase difference characteristics of actual measurement based on a phase difference on each frequency component between the phase characteristics. A phase line tilt calculating unit (model) calculates phase difference characteristics between a transfer function Ga(f) and a transfer function Gb(f) calculated by a transfer function calculating unit, and outputs the calculated phase difference characteristics to a search unit. The search unit fits a variable k and determines a variable k | 05-13-2010 |
20110288667 | INDUSTRIAL ROBOT SYSTEM - Provided is an industrial robot system which enables a reduction in an installation/adjustment period, and an increase in a no-error continuous operation period, and includes an action planning section ( | 11-24-2011 |
20140257117 | MEASUREMENT DEVICE, MEASUREMENT METHOD, AND RECORDING MEDIUM STORING A MEASUREMENT PROGRAM - A measurement device includes a detection device to detect a pulse wave signal at a first measurement location in a vascular pathway from the heart of a measurement subject to an area where an arterial aneurysm is predicted to occur and a pulse wave signal at a second measurement location in a vascular pathway from the heart of the measurement subject to an area that is different from the area where an arterial aneurysm is predicted to occur, a comparison device to calculate a comparison result by comparing frequency characteristics between the pulse wave signals, and a determination device to determine at least one of the presence/absence and size of an arterial aneurysm based on a predetermined characteristic amount for a frequency contained in the comparison result. | 09-11-2014 |
Patent application number | Description | Published |
20080309398 | MULTIPLIER CIRCUIT - A multiplier circuit includes a bias circuit which outputs a reference voltage and a bias signal, a first delay circuit which inputs a input signal and outputs a first delayed signal according to the reference voltage and the bias signal, a second delay circuit which inputs an inversed input signal and outputs a second delay signal according to the reference voltage and the bias signal and an OR circuit which outputs a OR logic result generated with the first and second delayed signals. | 12-18-2008 |
20090009164 | MAGNETO-SENSITIVE INTEGRATED CIRCUIT - A magneto-sensitive integrated circuit which amplifies a magneto-sensitive output voltage of a Hall element by an amplifier to generate an amplified voltage, converts an output voltage of the amplifier into a digital signal by an A/D converter; and generates a reference voltage of magnitude corresponding to an indicated value. The amplifier includes voltage superposition means which superposes a DC voltage corresponding to the reference voltage on the amplified voltage to generate the output voltage of the amplifier. | 01-08-2009 |
20110148472 | VOLTAGE CHANGE DETECTION DEVICE - A voltage change detection device is provided, which can reduce a deviation of a detection potential and can detect a voltage change within a predetermined detection potential even when the threshold voltage of a field effect transistor is deviated. The voltage change detection device includes a first field effect transistor, a second field effect transistor, and a detection signal generator. The first field effect transistor has a drain connected to a power supply potential, a source connected to a first constant current source or a first resistor at a first node, and a gate connected to a fixed voltage. The second field effect transistor has a drain and a gate connected to the power supply potential and a source connected to a second constant current source or a second resistor at a second node. The detection signal generator generates a detection signal indicating that the power supply potential has crossed a predetermined detection potential according to a comparison between a voltage at the first node and a voltage at the second node. | 06-23-2011 |
20110291869 | DETECTING DEVICE - A detecting device has: a detecting element to which a first constant voltage is applied; a resistance element connected to the detecting element; a switching element having a first terminal to the resistance element, a second terminal controlled to a second constant voltage lower than the first constant voltage, and a control terminal sets the first terminal and the second terminal in a conducting state; a control unit, according to a conducting/non-conducting state, controls voltage to the control terminal to maintain a potential difference between the detecting element and the resistance element; and an AD converter converting, into a digital value, a potential of a potential difference between the first constant voltage and the first terminal being voltage-divided at the detecting element and the resistance element to the detecting element, a first reference potential is the first constant voltage, and a second reference potential is voltage to the first terminal. | 12-01-2011 |
20120086387 | CHARGING CONTROL SYSTEM AND DEVICE - A charging control system for charging a secondary battery from a solar battery, including a first path for transmitting power from the solar battery to the secondary battery, a second path for sensing the voltage of the secondary battery, and a comparison unit for comparing the solar battery voltage with the sensed voltage of the secondary battery. The first path includes a first interrupter, controlled by the comparison unit, which interrupts the first path to prevent discharge of the secondary battery through the solar battery when the solar battery voltage falls below the secondary battery voltage. The second path includes a second interrupter that interrupts the second path after the first path is interrupted, to prevent the secondary battery from discharging through the second path when not being charged through the first path. | 04-12-2012 |
20120133040 | SEMICONDUCTOR CHIP AND SOLAR SYSTEM - There is provided a semiconductor chip having four sides and being substantially formed in a rectangle, the semiconductor chip including: a first terminal which is located along one side of the four sides of the semiconductor chip and which is to be electrically connected to a solar cell outside the semiconductor chip; a second terminal which is located along the one side of the semiconductor chip and which is to be electrically connected to a secondary cell outside the semiconductor chip; and an interconnection line that electrically interconnects the first terminal and the second terminal. | 05-31-2012 |
20120194105 | VOLTAGE DETERMINATION DEVICE AND CLOCK CONTROL DEVICE - A voltage determination device includes a reference voltage generation circuit; a determination target voltage line; a first voltage line; a second voltage line; and a switching circuit disposed between the first voltage line and the second voltage line. The switching circuit is provided for performing a switching operation according to a level of the determination target voltage. The voltage determination device includes a determining circuit for determining the level of the determination target voltage, and a control unit is provided for controlling a level of an electric current flowing between the first voltage line and the second voltage line. The control unit controls a resistivity between the switching circuit and the second voltage line so that the level of the electric current is maintained at a specific level when the determining circuit determines the level of the determination target voltage. | 08-02-2012 |
20140097872 | VOLTAGE CHANGE DETECTION DEVICE - A voltage change detection device, which reduces a deviation of a detection potential and detects a voltage change within a predetermined detection potential even when the threshold voltage of a field effect transistor is deviated. The voltage change detection device includes a first field effect transistor, a second field effect transistor, and a detection signal generator. The first field effect transistor has a drain connected to a power supply potential, a source connected to a first constant current source or a first resistor at a first node, and a gate connected to a fixed voltage. The second field effect transistor has a drain and a gate connected to the power supply potential and a source connected to a second constant current source or a second resistor at a second node. The detection signal generator generates a detection signal indicating that the power supply potential has crossed a predetermined detection potential. | 04-10-2014 |
20140184138 | SEMICONDUCTOR CHIP AND SOLAR SYSTEM - There is provided a semiconductor chip having four sides and being substantially formed in a rectangle, the semiconductor chip including: a first terminal which is located along one side of the four sides of the semiconductor chip and which is to be electrically connected to a solar cell outside the semiconductor chip; a second terminal which is located along the one side of the semiconductor chip and which is to be electrically connected to a secondary cell outside the semiconductor chip; and an interconnection line that electrically interconnects the first terminal and the second terminal. | 07-03-2014 |
20140232321 | CHARGING CONTROL SYSTEM AND DEVICE - A charging control system for charging a secondary battery from a solar battery, including a first path for transmitting power from the solar battery to the secondary battery, a second path for sensing the voltage of the secondary battery, and a comparison unit for comparing the solar battery voltage with the sensed voltage of the secondary battery. The first path includes a first interrupter, controlled by the comparison unit, which interrupts the first path to prevent discharge of the secondary battery through the solar battery when the solar battery voltage falls below the secondary battery voltage. The second path includes a second interrupter that interrupts the second path after the first path is interrupted, to prevent the secondary battery from discharging through the second path when not being charged through the first path. | 08-21-2014 |
20150130399 | CHARGING CONTROL SYSTEM AND DEVICE - A charging control system for charging a secondary battery from a solar battery, including a first path for transmitting power from the solar battery to the secondary battery, a second path for sensing the voltage of the secondary battery, and a comparison unit for comparing the solar battery voltage with the sensed voltage of the secondary battery. The first path includes a first interrupter, controlled by the comparison unit, which interrupts the first path to prevent discharge of the secondary battery through the solar battery when the solar battery voltage falls below the secondary battery voltage. The second path includes a second interrupter that interrupts the second path after the first path is interrupted, to prevent the secondary battery from discharging through the second path when not being charged through the first path. | 05-14-2015 |
Patent application number | Description | Published |
20090184427 | FLASH MEMORY DEVICE WITH WORD LINES OF UNIFORM WIDTH AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating film on the semiconductor substrate; and forming a metal plug which penetrates through the interlayer insulating film and is coupled to the bit line in a region where the portion of the plurality of word lines was eliminated. | 07-23-2009 |
20100002517 | SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING - A semiconductor device is disclosed. The semiconductor device includes a plurality of memory cells that are provided in a matrix and that have a charge storage layer made of an insulating film that is provided on a semiconductor substrate and a plurality of word lines that are provided on the charge storage layer. A plurality of memory cells that are arranged in a single line among the plurality of memory cells arranged in the matrix are coupled to the same word line. The semiconductor device further includes an application section that when reading data from a selected memory cell selected from the plurality of memory cells, applies a voltage to a selected word line to be coupled to the selected memory cell among the plurality of word lines. The application section applies a voltage that has a polarity that is opposite to the voltage applied to the selected word line to non-selected word lines arranged on both adjacent sides of the selected word line. | 01-07-2010 |
20100052038 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device which includes two trenches formed in a semiconductor substrate, a charge storage layer as an insulator formed on each side surface of the trenches, and separated on a bottom surface thereof, and a bit line formed below the bottom surface of the trenches in the semiconductor substrate. A channel region is formed in the semiconductor substrate from a side surface of one of the two trenches to that of the other trench via an upper surface of a protruding portion between those two trenches. A method for manufacturing the semiconductor device is also provided. | 03-04-2010 |
20110156127 | FLASH MEMORY DEVICE WITH WORD LINES OF UNIFORM WIDTH AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating film on the semiconductor substrate; and forming a metal plug which penetrates through the interlayer insulating film and is coupled to the bit line in a region where the portion of the plurality of word lines was eliminated. | 06-30-2011 |
20110171819 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF - A silicon nitride film, which is a second hard mask, is dry etched to be removed completely. The silicon nitride film, which is formed on a sidewall of a silicon nitride film used as a first hard mask, has a relatively low etching rate. Therefore, if the silicon nitride film is continued etching until the corresponding portion thereof is removed, polysilicon is etched in a direction of depth in trench shape. Then, floating gates in adjacent cells are separated and a step portion of the polysilicon is formed. Consequently, a remaining portion of the silicon nitride film used as the first hard mask is removed, an ONO film is laminated on a whole surface of the poly silicon having the step portion on an edge that has been etched, and then, a polysilicon for a control gate is laminated on the ONO film. | 07-14-2011 |
20120083109 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a bit line that is provided in a semiconductor substrate, a silicide layer that has side faces and a bottom face surrounded by the bit line and is provided within the bit line, an ONO film that is provided on the semiconductor substrate, and sidewalls that are in contact with the side faces of a trapping layer in the ONO film over the portions of the bit line located on both sides of the silicide layer, the sidewalls being formed with silicon oxide films including phosphorus. | 04-05-2012 |
20120256245 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device in accordance with one embodiment of the invention can include a semiconductor substrate having a groove, a bit line, a pocket implantation region, a bottom insulating membrane, and a charge accumulation region. The bit line is formed on a side of the groove in the semiconductor substrate and acts as a source and a drain. The pocket implantation region is formed to touch (or contact) the bit line, has a similar conductivity type as the semiconductor substrate, and has a dopant concentration higher than that of the semiconductor substrate. The bottom insulating membrane is formed on and touches (or contacts) a side surface of the groove. The charge accumulation layer is formed on and touches (or contacts) a side surface of the bottom insulating membrane. | 10-11-2012 |
20130064024 | SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING - A semiconductor device is disclosed. The semiconductor device includes a plurality of memory cells provided in a matrix and having a charge storage layer, a plurality of word lines provided on the charge storage layer, and an application section. When reading data from a selected memory cell selected from the plurality of memory cells, the application section applies a voltage having an opposite polarity to the voltage applied to a selected word line to non-selected word lines arranged on both adjacent sides of the selected word line. | 03-14-2013 |
20130183819 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF - A silicon nitride film, which is a second hard mask, is dry etched to be removed completely. The silicon nitride film, which is formed on a sidewall of a silicon nitride film used as a first hard mask, has a relatively low etching rate. Therefore, if the silicon nitride film is continued etching until the corresponding portion thereof is removed, polysilicon is etched in a direction of depth in trench shape. Then, floating gates in adjacent cells are separated and a step portion of the polysilicon is formed. Consequently, a remaining portion of the silicon nitride film used as the first hard mask is removed, an ONO film is laminated on a whole surface of the poly silicon having the step portion on an edge that has been etched, and then, a polysilicon for a control gate is laminated on the ONO film. | 07-18-2013 |
20140021529 | FLASH MEMORY DEVICE WITH WORD LINES OF UNIFORM WIDTH AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating film on the semiconductor substrate; and forming a metal plug which penetrates through the interlayer insulating film and is coupled to the bit line in a region where the portion of the plurality of word lines was eliminated. | 01-23-2014 |