Patent application number | Description | Published |
20090315145 | ADJUSTABLE BIPOLAR TRANSISTORS FORMED USING A CMOS PROCESS - By providing a novel bipolar device design implementation, a standard CMOS process ( | 12-24-2009 |
20110101425 | SEMICONDUCTOR DEVICE WITH INCREASED SNAPBACK VOLTAGE - Methods and apparatus are provided for fabricating a semiconductor device structure. The semiconductor device structure comprises a buried region having a first conductivity type, a first region having a second conductivity type overlying the buried region, a source region having the first conductivity type overlying the first region, and a drain region having the first conductivity type overlying the first region. The semiconductor device structure further comprises a second region having the first conductivity type overlying the buried region, the second region abutting the buried region to form an electrical contact with the buried region, and a first resistance configured electrically in series with the second region and the buried region. The combined series resistance of the first resistance and the second region is greater than a resistance of the buried region. | 05-05-2011 |
20110147893 | BIPOLAR TRANSISTORS WITH HUMP REGIONS - By providing a novel bipolar device design implementation, a standard CMOS process can be used unchanged to fabricate useful bipolar transistors and other bipolar devices having adjustable properties by partially blocking the P or N well doping used for the transistor base. This provides a hump-shaped base region with an adjustable base width, thereby achieving, for example, higher gain than can be obtained with the unmodified CMOS process alone. By further partially blocking the source/drain doping step used to form the emitter of the bipolar transistor, the emitter shape and effective base width can be further varied to provide additional control over the bipolar device properties. The embodiments thus include prescribed modifications to the masks associated with the bipolar device that are configured to obtain desired device properties. The CMOS process steps and flow are otherwise unaltered and no additional process steps are required. | 06-23-2011 |
20110241092 | ELECTRONIC DEVICE WITH CAPCITIVELY COUPLED FLOATING BURIED LAYER - Transistors ( | 10-06-2011 |
20110309442 | LATERALLY DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR HAVING A REDUCED SURFACE FIELD STRUCTURE AND METHOD THEREFOR - An LDMOS transistor includes a substrate of semiconductor material, an insulator layer overlying the substrate, a semiconductor layer overlying the insulator layer, a RESURF region, and a gate. The semiconductor layer includes a first conductivity type well region, a second conductivity type source region in contact with the first conductivity type well region, a second conductivity type drain region. The RESURF region includes at least one first conductivity type material portion, and at least one portion of the at least one first conductivity type material portion electrically coupled to the first conductivity type well region. A semiconductor material having a second conductivity type is located below the RESURF region. The second conductivity type semiconductor material is also located over a part of the RESURF region. The gate is located over the first conductivity type well region and over the RESURF region. | 12-22-2011 |
20120061758 | SEMICONDUCTOR DEVICE AND RELATED MANUFACTURING METHOD - A semiconductor device and a related fabrication process are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type. | 03-15-2012 |
20120098096 | BIPOLAR TRANSISTOR - A bipolar transistor comprises at least first and second connected emitter-base (EB) junctions having, respectively, different first and second EB junction depths, and a buried layer (BL) collector having a greater third depth. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region overlies the second EB junction location thereby providing its shallower EB junction depth. The BL collector does not underlie the first EB junction and is laterally spaced therefrom by a variable amount to facilitate adjusting the transistor's properties. In other embodiments, the BL collector can underlie at least a portion of the second EB junction. Regions of opposite conductivity type over-lie and under-lie the BL collector, which is relatively lightly doped, thereby preserving the breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements. | 04-26-2012 |
20120125113 | PRESSURE TRANSDUCER HAVING STRUCTURE FOR MONITORING SURFACE CHARGE - A pressure transducer includes a substrate, a piezoresistive element, a first conductive element, a first terminal, and a test structure. The substrate has a surface and a cavity. A diaphragm layer is formed over the cavity and over the surface of the substrate. The piezoresistive element is formed in the diaphragm layer. The first conductive element is formed in the diaphragm layer, and has a first conductivity type. The first conductive element is coupled to the piezoresistive element. The first terminal is formed over a surface of the diaphragm layer and coupled to the first conductive element. The test structure has the first conductivity type and is formed in the diaphragm layer. The test structure has an edge spaced apart from an edge of the first conductive element by a predetermined distance. A surface charge accumulation on the diaphragm layer is detected using the test structure. | 05-24-2012 |
20120229153 | SYSTEMS AND METHODS FOR DETECTING SURFACE CHARGE - Systems and methods are provided for detecting surface charge on a semiconductor substrate having a sensing arrangement formed thereon. An exemplary sensing system includes the semiconductor substrate having the sensing arrangement formed thereon, and a module coupled to the sensing arrangement. The module obtains a first voltage output from the sensing arrangement when a first voltage is applied to the semiconductor substrate, obtains a second voltage output from the sensing arrangement when a second voltage is applied to the semiconductor substrate, and detects electric charge on the surface of the semiconductor substrate based on a difference between the first voltage output and the second voltage output. | 09-13-2012 |
20130137224 | MANUFACTURING METHODS FOR LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICES - Fabrication processes for semiconductor devices are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type. | 05-30-2013 |
20140103431 | LATERALLY DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTORS HAVING A REDUCED SURFACE FIELD STRUCTURES - An LDMOS transistor includes a substrate of semiconductor material, an insulator layer overlying the substrate, a semiconductor layer overlying the insulator layer, a RESURF region, and a gate. The semiconductor layer includes a first conductivity type well region, a second conductivity type source region in contact with the first conductivity type well region, a second conductivity type drain region. The RESURF region includes at least one first conductivity type material portion, and at least one portion of the at least one first conductivity type material portion electrically coupled to the first conductivity type well region. A semiconductor material having a second conductivity type is located below the RESURF region. The second conductivity type semiconductor material is also located over a part of the RESURF region. The gate is located over the first conductivity type well region and over the RESURF region. | 04-17-2014 |
20140308792 | METHODS OF PRODUCING BIPOLAR TRANSISTORS HAVING EMITTER-BASE JUNCTIONS OF VARYING DEPTHS AND/OR DOPING CONCENTRATIONS - Methods for producing bipolar transistors are provided. In one embodiment, the method includes producing a bipolar transistor including first and second connected emitter-base (EB) junctions of varying different depths. A buried layer (BL) collector is further produced to have a third depth greater than the depths of the EB junctions. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region may overlie the second EB junction location. The BL collector is laterally spaced from the first EB junction by a variable amount to facilitate adjustment of the transistor properties. The BL collector may or may not underlie at least a portion of the second EB junction. Regions of opposite conductivity type overlie and underlie the BL collector to preserve breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements. | 10-16-2014 |
Patent application number | Description | Published |
20120227127 | MAIZE VARIETY X4K584 - A novel maize variety designated X4K584 and seed, plants and plant parts thereof, produced by crossing Pioneer Hi-Bred International, Inc. proprietary inbred maize varieties. Methods for producing a maize plant that comprises crossing maize variety X4K584 with another maize plant. Methods for producing a maize plant containing in its genetic material one or more traits introgressed into X4K584 through backcross conversion and/or transformation, and to the maize seed, plant and plant part produced thereby. This invention relates to the maize variety X4K584, the seed, the plant produced from the seed, and variants, mutants, and minor modifications of maize variety X4K584. This invention further relates to methods for producing maize varieties derived from maize variety X4K584 and to the maize varieties derived by the use of those methods. | 09-06-2012 |
20150296733 | MAIZE HYBRID X03F667 - A novel maize variety designated X03F667 and seed, plants and plant parts thereof are produced by crossing inbred maize varieties. Methods for producing a maize plant by crossing hybrid maize variety X03F667 with another maize plant are disclosed. Methods for producing a maize plant containing in its genetic material one or more traits introgressed into X03F667 through backcross conversion and/or transformation, and to the maize seed, plant and plant part produced thereby. This invention relates to the maize variety X03F667, the seed, the plant produced from the seed, and variants, mutants, and minor modifications of maize variety X03F667. This invention further relates to methods for producing maize varieties derived from maize variety X03F667. | 10-22-2015 |
20150351353 | MAIZE HYBRID X95F581 - A novel maize variety designated X95F581 and seed, plants and plant parts thereof are produced by crossing inbred maize varieties. Methods for producing a maize plant by crossing hybrid maize variety X95F581 with another maize plant are disclosed. Methods for producing a maize plant containing in its genetic material one or more traits introgressed into X95F581 through backcross conversion and/or transformation, and to the maize seed, plant and plant part produced thereby. This invention relates to the maize variety X95F581, the seed, the plant produced from the seed, and variants, mutants, and minor modifications of maize variety X95F581. This invention further relates to methods for producing maize varieties derived from maize variety X95F581. | 12-10-2015 |
Patent application number | Description | Published |
20090288390 | SIMPLIFIED THRUST CHAMBER RECIRCULATING COOLING SYSTEM - In some implementations a propulsion system includes a thrust chamber having a gap between an inner shell and an outer shell, the inner shell and the outer shell being attached together to form the thrust chamber. In some implementations, the rocket engine also includes a recirculating cooling system operably coupled to the gap in at least two locations and operable to recirculate a convective coolant through the gap. | 11-26-2009 |
20090293448 | Simplified thrust chamber recirculating cooling system - In some aspects a propulsion system includes a thrust chamber having a gap between an inner shell and an outer shell, the inner shell and the outer shell being attached together to form the thrust chamber. The rocket engine also includes a recirculating cooling system operably coupled to the gap in at least two locations and operable to recirculate a convective coolant through the gap. | 12-03-2009 |
20110005193 | Method and apparatus for simplified thrust chamber configurations - The invention of this disclosure is methods and apparatuses improving the ease of fabrication and delivered specific impulse performance of simplified rocket engine thrust chambers. Included are a method and apparatus for a pool-boiling cooling system rocket thrust chamber. This cooling system utilizes a convective coolant flowing in a continuous or semi-continuous coolant loop. In addition the convective coolant itself is cooled in a pool-boiling heat exchanger by the evaporation of a propellant that functions as a boiling coolant. The invention also includes a method and apparatus for a shortened, simplified, conical expansion nozzle for a rocket thrust chamber that can operate with reduced specific impulse losses due to nozzle configuration and the use of film coolant in the thrust chamber. | 01-13-2011 |
20120060464 | SYSTEMS, METHODS AND APPARATUS FOR PROPULSION - In some implementations a propulsion system includes a thrust chamber comprised of a combustion chamber and an expansion nozzle. The thrust chamber has an interior and exterior surfaces and a main propellant injector mounted to the thrust chamber to inject an oxidizer and a fuel into the interior of the thrust chamber. The total fluid flowing to the rocket engine is compromised of oxidizer, fuel, internal film coolant, and external convective coolant. The internal film coolant ranges from about 1% to about 10% of the total fluid. Reduced coolant tubing circumscribes the exterior of the thrust chamber to circulate an external convective coolant, and a nozzle film coolant manifold mounted to the expansion nozzle injects the external convective coolant onto the interior wall of the expansion nozzle, the external convective coolant being about 1% to about 10% of the total fluid flow to the thrust chamber. | 03-15-2012 |
Patent application number | Description | Published |
20120214769 | Novel Antagonists of the Glucagon Receptor - The present invention provides for novel compounds of Formula (I) and pharmaceutically acceptable salts and co-crystals thereof which have glucagon receptor antagonist or inverse agonist activity. The present invention further provides for pharmaceutical compositions comprising the same as well as methods of treating, preventing, delaying the time to onset or reducing the risk for the development or progression of a disease or condition for which one or more glucagon receptor antagonist is indicated, including Type I and II diabetes, insulin resistance and hyperglycemia. The present invention also provides for processes of making the compounds of Formula I, including salts and co-crystals thereof, and pharmaceutical compositions comprising the same. | 08-23-2012 |
20130030029 | Glucagon Antagonists - Provided herein are compounds, including enantiomerically pure forms thereof, and pharmaceutically acceptable salts or co-crystals and prodrugs thereof which have glucagon receptor antagonist or inverse agonist activity. Further, provided herein are pharmaceutical compositions comprising the same as well as methods of treating, preventing, delaying the time to onset or reducing the risk for the development or progression of a disease or condition for which one or more glucagon receptor antagonist is indicated, including Type I and II diabetes, insulin resistance and hyperglycemia. Moreover, provided herein are methods of making or manufacturing compounds disclosed herein, including enantiomerically pure forms thereof, and pharmaceutically acceptable salts or Co-crystals and prodrugs thereof. Formula I | 01-31-2013 |
20140135400 | NOVEL ANTAGONISTS OF THE GLUCAGON RECEPTOR - The present invention provides for novel compounds of Formula (I) and pharmaceutically acceptable salts and co-crystals thereof which have glucagon receptor antagonist or inverse agonist activity. The present invention further provides for pharmaceutical compositions comprising the same as well as methods of treating, preventing, delaying the time to onset or reducing the risk for the development or progression of a disease or condition for which one or more glucagon receptor antagonist is indicated, including Type I and II diabetes, insulin resistance and hyperglycemia. The present invention also provides for processes of making the compounds of Formula I, including salts and co-crystals thereof, and pharmaceutical compositions comprising the same. | 05-15-2014 |
20150087680 | GLUCAGON ANTAGONISTS - Provided herein are compounds, including enantiomerically pure forms thereof, and pharmaceutically acceptable salts or co-crystals and prodrugs thereof which have glucagon receptor antagonist or inverse agonist activity. Further, provided herein are pharmaceutical compositions comprising the same as well as methods of treating, preventing, delaying the time to onset or reducing the risk for the development or progression of a disease or condition for which one or more glucagon receptor antagonist is indicated, including Type I and II diabetes, insulin resistance and hyperglycemia. Moreover, provided herein are methods of making or manufacturing compounds disclosed herein, including enantiomerically pure forms thereof, and pharmaceutically acceptable salts or Co-crystals and prodrugs thereof. Formula I | 03-26-2015 |