Patent application number | Description | Published |
20080231351 | VOLTAGE STEP-DOWN CIRCUIT - According to an aspect of the present invention, there is provided a voltage step-down circuit including: a first NMOS connected between an external and an internal power-supply voltages through a PMOS turned ON during an active state and turned OFF during a standby state; a second NMOS connected between the external and the internal power-supply voltages; and a current control circuit that sinks a current from the internal power-supply voltage to a ground level for a certain period of time after an operation state is switched from the active state to the standby state. | 09-25-2008 |
20090039944 | REFERENCE VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR STORAGE APPARATUS USING THE SAME - According to an aspect of the present invention, there is provided a reference voltage generation circuit including: a first circuit configured to generate a first voltage that is independent of a power supply voltage and that is dependent of a temperature; a second circuit configured to generate a second voltage that is independent of the power supply voltage and that is dependent of the temperature; and a third circuit configured to compare the first voltage and the second voltage and to generate a reference voltage based on a higher one therebetween. | 02-12-2009 |
20090096506 | POWER SUPPLY CIRCUIT - According to an aspect of the present invention, there is provided a power supply circuit including: a detection circuit that is connected to an external power supply voltage and that outputs a first signal indicating whether the external power supply voltage is in a dropped-state in which the external power supply voltage is dropped below a reference voltage; a control circuit that includes: a delay circuit that outputs a second signal acquired by delaying the first signal for a reference time; and a determination circuit that outputs a third signal based on the first signal and the second signal; a generation circuit that generates internal power supply voltage from the external power supply voltage and that supplies the internal power supply voltage; and an interruption circuit that interrupts the internal power supply voltage supplied from the generation circuit based on the third signal. | 04-16-2009 |
20090231903 | FERROELECTRIC MEMORY AND METHOD FOR TESTING THE SAME - A driver circuit and a precharge circuit apply, in a test mode, a fixed potential to a bit-line, while applying a second plate-line voltage to a plate-line. Then, the bit-line is switched from a first bit-line precharge potential to a floating state, and the plate-line voltage is raised from the second plate-line voltage to a plate-line voltage. | 09-17-2009 |
20100090727 | VOLTAGE DETECTION CIRCUIT AND BGR VOLTAGE DETECTION CIRCUIT - A voltage detection circuit of the present invention includes an NMOS transistor diode-connected, a gate and a drain thereof being supplied with a power supply voltage, a resistor connected between a source of the NMOS transistor and a ground potential, and a source voltage detection circuit receiving a voltage of the source, wherein an NMOS type transistor is employed as the NMOS transistor, a channel width and a channel length of the NMOS type transistor being set in such a manner that an operating point on a VG-ID curve of the NMOS type transistor may come to a certain point, at the certain point, a drain current of the NMOS type transistor being constant even if the temperature fluctuates. | 04-15-2010 |
20100091547 | SEMICONDUCTOR MEMORY DEVICE - A memory includes a memory cell array including destructive read-out type memory cells; a decoder selecting a cell; a sense amplifier configured to detect the data; and a read and write controller controlling a read operation and a write operation, wherein the read and write controller outputs a logical value of a write enable signal at the start of the read operation in a first period and makes the write enable signal invalid after the read operation starts during the first period, on the basis of the write enable signal and a restore signal keeping an activated state during the first period, the write enable signal being a signal allowing the write operation, the first period being a period from when the read operation starts to when a restore operation for writing the data back to the memory cell is completed. | 04-15-2010 |
20100149850 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device including: a memory cell array including: memory cell blocks each having series-connected memory cells; wordlines; and a bitline pair connected to the memory cell blocks, one functioning as a readout bitline, the other one functioning as a reference bitline; an amplification circuit connected to the bitline pair to amplify a signal difference therebetween; and a reference voltage generation circuit including: a dummy memory cell block that has the same configuration as the memory cell block, that has one terminal connected to a first dummy plate line and that has the other terminal connected to the reference bitline; and a paraelectric capacitor that has one terminal connected to a second dummy plate line and that has the other terminal connected to the reference bitline. | 06-17-2010 |
20100237931 | INTERNAL POWER SUPPLY VOLTAGE GENERATION CIRCUIT - An internal power supply voltage generation circuit | 09-23-2010 |
20100237933 | CURRENT SUPPLY CIRCUIT - A current supply circuit according to an embodiment of the present invention includes an operational amplifier having first and second input terminals and an output terminal, a transistor having a control terminal connected to the output terminal of the operational amplifier, and having first and second main terminals, a first resistance arranged between the first input terminal of the operational amplifier and the first main terminal of the transistor, a second resistance arranged between a predetermined node and a ground line, the predetermined node being between the first input terminal of the operational amplifier and the first resistance, first to Nth transistors, each of which has a control terminal connected to the control terminal or the second main terminal of the transistor, and has a main terminal outputting a current, where N is an integer of two or larger, and first to Nth switching transistors, each of which has a main terminal, the main terminals of the first to Nth switching transistors being respectively connected to the main terminals of the first to Nth transistors, a pulse width of a signal provided to a control terminal of the respective first to Nth switching transistors being set to be constant regardless of a pulse frequency of the signal. | 09-23-2010 |
20110007579 | INTERNAL VOLTAGE GENERATOR - An internal voltage generator according to an embodiment generates a reference voltage used for detecting data stored in a semiconductor memory. A first AD converter is configured to convert an external voltage supplied to the semiconductor memory into a first digital value. A second AD converter is configured to convert a temperature characteristic voltage that changes depending on a temperature of the semiconductor memory into a second digital value. An adder is configured to receive a reference voltage trimming address that specifies the reference voltage, the first digital value, and the second digital value, and to output a third digital value obtained by performing a weighted addition of the reference voltage trimming address, the first digital value, and the second digital value. A driver is configured to output the reference voltage responding to the third digital value. | 01-13-2011 |
20120057405 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device comprises a cell array, voltage generation circuits, and a control circuit. The cell array comprises memory cell strings. The voltage generation circuits are arranged below the cell array. Each of the memory cell strings comprises a semiconductor layer, control gates, and memory cell transistors. The semiconductor layer comprises a pair of pillar portions, and a connecting portion. The control gates intersect the pillar portion. The memory cell transistors are formed at intersections of the pillar portion and the control gates. In a write operation and a read operation, the control circuit does not drive voltage generation circuits which give noise to memory cell strings as a write target and a read target, and drives voltage generation circuits which do not give noise to the memory cell strings as the write target and the read target. | 03-08-2012 |
20120069663 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit. | 03-22-2012 |
20130314994 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit. | 11-28-2013 |
20150029791 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit. | 01-29-2015 |
20150036410 | SEMICONDUCTOR STORAGE DEVICE - A memory includes a first and second cell storing first data and second or reference-data. A first and second bit-lines connected to the first and second cells respectively correspond to a first and second sense-nodes. A first transfer-gate is inserted/connected between the first bit-line and the first sense-node. A second transfer-gate is inserted/connected between the second bit-line and the second sense-node. A sense-amplifier is inserted or connected between the first and second sense-nodes. A preamplifier includes a first and second common-transistors. The first common-transistor applies a first power-supply voltage to either the first or the second sense-node according to the first and second data or according to the first and reference-data during a data-read-operation. The second common-transistor applies a second power-supply voltage to the other sense-node out of the first and second sense-nodes according to the first and second data or according to the first and reference data. | 02-05-2015 |