Patent application number | Description | Published |
20080231333 | Spread Spectrum Clock Generator - A spread spectrum clock generator is disclosed. The spread spectrum clock generator (SSCG) bases on the structure of the phase-lock loop. The SSCG uses the voltage control oscillator with multi-phase output function for outputting clock signals of different phases. The clock signals of different phases are selectively fed back to the phase frequency detector. In this way, the frequency of the output signal is changed, which achieves spreading spectrum. | 09-25-2008 |
20090160562 | OSCILLATING DEVICE - The present invention provides an oscillating device. The oscillating device includes: a voltage regulating module, a current generating module, and an oscillating module. The voltage regulating module is utilized for generating a control voltage at an output terminal, and the voltage regulating module includes: a first operational amplifier, a first switch element, and a first voltage dividing circuit. The oscillating module includes: a plurality of switch modules connected in series, a current mirror module, and a plurality of capacitor modules. In the oscillating device of the present invention, a frequency of an oscillating signal outputted by the oscillating module will not be affected by voltage offset of an operating voltage, environment temperature variations, or semiconductor process variations. | 06-25-2009 |
20090261877 | Duty cycle correction circuit with wide-frequency working range - A duty cycle correction circuit with wide-frequency working range utilizes a pulse generator having adjustable pulse width function to adjust the width of the pulse and outputs a clock signal with the duty cycle of 50%. The pulse generator includes a NAND gate, a modulation device, and an inverter. The inverter is coupled between the second input end of the NAND gate and the modulation device. The modulation device modulates the low-level status of the input clock signal and accordingly outputs to the inverter. The first input end of the NAND gate receives the input clock signal. The NAND gate operates NAND calculation to the signals received on the input ends of the NAND gate and accordingly outputs a periodic low-level pulse signal. | 10-22-2009 |
20090262879 | DLL circuit with wide-frequency locking range and error-locking-avoiding function - A delay-locked loop (DLL) circuit. In the evaluation period, the DLL circuit adjusts needed delay period of time for a reference clock signal by adjusting the amount of the used delay units which each of has fixed delay period of time digitally and controlling the delay period of time of the voltage control delay circuit analogically. In the locking period, the DLL circuit utilizes the delay time of the delay units, which is decided in the evaluation period, along with the voltage control delay circuit, to lock phase of the reference clock signal. In this way, the stability of the delay period of time of the voltage control delay circuit increases. | 10-22-2009 |
20100019802 | Phase/Frequency Detector - PFD includes UP and DOWN signal modules, and RESET signal module. UP and DOWN signal modules transmit UP and DOWN signals according to reference and fed-back clock signals. RESET module includes UP-RESET and DOWN-RESET signal modules. UP-RESET signal module resets UP signal module according to pre-trigger fed-back signal, UP and DOWN signals. Pre-trigger fed-back signal is generated according to original fed-back clock signal and calculation of logic gates and inverting delay module. DOWN-RESET signal module resets DOWN signal module according to pre-trigger reference signal, UP and DOWN signals. Pre-trigger reference signal is generated according to original reference clock signal and calculation of logic gates and inverting delay module. | 01-28-2010 |
20100033217 | Delayed-Locked Loop with power-saving function - A DLL with power-saving function includes a VCDL, a voltage control module, a capacitor, and a phase detector. The VCDL generates a delayed clock signal according to the voltage on the capacitor and a reference clock signal. The phase detector detects phase difference between the delayed clock signal and the reference clock signal and accordingly controls the voltage controller. The voltage controller sinks or sources current to the capacitor for adjusting the voltage on the capacitor. Further, the voltage controller can turn off its charge pump according to a turned-off signal and stops sinking or sourcing current for saving power. | 02-11-2010 |
20140022023 | TEMPERATURE-INSENSITIVE RING OSCILLATORS AND INVERTER CIRCUITS - A ring oscillator includes a plurality of stages of delay cells coupled in serial. At least one delay cell includes a first inverter. The first inverter includes an input node receiving an input signal, a first transistor coupled to a first supply voltage and the input node, a second transistor coupled to a second supply voltage and the input node, an output node coupled to the first transistor and the second transistor and outputting an output signal, and at least one resistive device coupled to the capacitor, the first transistor, and the second transistor. | 01-23-2014 |