Patent application number | Description | Published |
20100052122 | WIRE BODNING PACKAGE STRUCTURE - A chip package structure employing a die pad integrated with the ground/voltage pad is provided. The die pad for carrying the chip is split into at least two separate sections for accommodating the ground and the voltage. Due to the design of the die pad, the signal fingers may be extended under the chip to be connected with vias, and thermal/ground vias may be arranged under the die pad for thermal or electrical connections. Through such arrangement, all the fingers are located closer to the die, thus decrease the length of bonding wires and reducing the package dimensions. | 03-04-2010 |
20100052156 | CHIP SCALE PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A chip scale package (CSP) structure and the packaging process thereof are described. By using a matrix of interlinked heat sink units compatible with the block substrate, the packaging process can be simplified and a plurality of packages units or chip scale packages with enhanced thermal performance can be obtained after singulation. | 03-04-2010 |
20100052186 | STACKED TYPE CHIP PACKAGE STRUCTURE - A stacked type chip package structure employs a substrate having a pseudo-cavity or a keep-out zone at one side or both sides thereof. Through the pattern arrangement of the wiring layer and the solder mask layer, the thickness of the entire stacked type chip package structure is effectively reduced as lower wire loops and a thinner mold-cap can be achieved by mounting the chip within the depressed keep-out zone. In particular, the double-sided chip package structures are suitable for package on package structures adopted by mobile applications. | 03-04-2010 |
20100055392 | METHOD OF FABRICATING MULTI-LAYERED SUBSTRATE AND THE SUBSTRATE THEREOF - The present invention directs to fabrication methods of single-sided or double-sided multi-layered substrate by providing a lamination structure having at least a core structure and first and second laminate structures stacked over both surfaces of the core structure. The core structure functions as the temporary carrier for carrying the first and second laminate structures through the double-sided processing procedures. By way of the fabrication methods, the production yield can be greatly improved without increasing the production costs. | 03-04-2010 |
20100288541 | SUBSTRATE HAVING SINGLE PATTERNED METAL LAYER, AND PACKAGE APPLIED WITH THE SUBSTRATE , AND METHODS OF MANUFACTURING OF THE SUBSTRATE AND PACKAGE - A substrate having single patterned metal layer includes a patterned base having at least a plurality of apertures, the patterned metal layer disposed on the patterned base, and a first surface finish layer. Parts of the lower surface of the patterned metal layer are exposed by the apertures of the patterned base to form a plurality of first contact pads for downward electrical connection externally, and parts of the upper surface of the patterned metal layer function as a plurality of second contact pads for upward electrical connection externally. The first surface finish layer is disposed at least on one or more surfaces of the second contact pads, and the first surface finish layer is wider than the second contact pad beneath. A package applied with the substrate disclosed herein further comprises at least a die conductively connected to the second contact pads of the substrate. | 11-18-2010 |
20100320610 | SEMICONDUCTOR PACKAGE WITH SUBSTRATE HAVING SINGLE METAL LAYER AND MANUFACTURING METHODS THEREOF - A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die. | 12-23-2010 |
20110057301 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and has openings exposing at least a portion of the patterned metal foil to form joints for external electrical connection. The chip is disposed on the first surface. The adhesive layer is disposed between the chip and the patterned metal foil. The wires respectively connect the chip and the patterned metal foil. The patterned dielectric layer is located below intersections between the wires and the patterned metal foil. The patterned dielectric layer, the wires, and the patterned metal foil overlap with one another on a plane. The molding compound is disposed on the first surface and covers the chip and the wires. | 03-10-2011 |
20110169150 | Semiconductor Package with Single Sided Substrate Design and Manufacturing Methods Thereof - A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity. | 07-14-2011 |
20110278713 | EMBEDDED COMPONENT SUBSTRATE, SEMICONDUCTOR PACKAGE STRUCTURE USING THE SAME AND FABRICATION METHODS THEREOF - An embedded electronic component semiconductor package structure and a packaging process thereof are provided. By providing two or more preformed building blocks, the electronic component can be assembled to the joined building blocks to obtain the embedded component semiconductor package structure. | 11-17-2011 |
20120033394 | METHOD OF FABRICATING EMBEDDED COMPONENT PACKAGE STRUCTURE AND THE PACKAGE STRUCTURE THEREOF - The present invention directs to fabrication methods of the embedded component package structures by providing preformed lamination structures, joining or stacking the preformed laminate structures and mounting at least one electronic component to the joined structures. By way of the fabrication methods, the production yield can be greatly improved with lower cycle time. | 02-09-2012 |
20120073871 | MULTI-LAYERED SUBSTRATE - The present invention directs to double-sided multi-layered substrate a base, at least a through-hole passing through the base, patterned first and second metal layers formed on the two opposite surfaces of the base, and first and second plating layers. The first plating layer covers a sidewall of the through-hole and the bottom surface surrounding a bottom opening of the through hole. The second plating layer covers the first plating layer and the top surface surrounding a top opening of the through hole. | 03-29-2012 |
20120091569 | LEADFRAME PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The package structure includes a metal sheet having a first central block, a plurality of first metal blocks, a second central block and a plurality of second metal blocks, a first finish layer and a second finish layer, at least a chip disposed on the metal sheet and a package body encapsulating the chip. The package structure may further include at least an area block for wire routing. | 04-19-2012 |
20120235309 | Semiconductor Package with Embedded Die and Manufacturing Methods Thereof - A semiconductor package includes a conductive base, a die disposed adjacent to an upper surface of the conductive base, a patterned conductive layer, and a dielectric layer encapsulating the die. The dielectric layer defines an opening through which the patterned conductive layer is electrically connected to the upper surface of the conductive base. The conductive base has a lateral surface including a first portion adjacent to the upper surface of the conductive base and a second portion adjacent to a lower surface of the conductive base, where the second portion is sloped inwardly with respect to the lower surface of the conductive base. | 09-20-2012 |
20120261689 | SEMICONDUCTOR DEVICE PACKAGES AND RELATED METHODS - The packages include a plurality of spaced conductive standoffs electrically coupling the semiconductor die to, variously, a substrate and bottom package contacts. The conductive standoffs may be pillars or posts. The substrate includes at least one electrically isolated portion, which has exposed sidewalls. | 10-18-2012 |
20140021636 | SEMICONDUCTOR PACKAGE WITH SINGLE SIDED SUBSTRATE DESIGN AND MANUFACTURING METHODS THEREOF - A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer. | 01-23-2014 |
20140346670 | SEMICONDUCTOR PACKAGE WITH SINGLE SIDED SUBSTRATE DESIGN AND MANUFACTURING METHODS THEREOF - A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer. | 11-27-2014 |