Patent application number | Description | Published |
20080231249 | Integrated circuit current reference - An IC current reference includes a reference voltage V | 09-25-2008 |
20080237630 | Semiconductor switch - A semiconductor switch comprises a PNPN structure arranged to provide an SCR-like functionality, and a MOS gate structure, preferably integrated on a common substrate. The switch includes ohmic contacts for the MOS gate, and for the cathode and gate regions of the PNPN structure; the anode contact is intrinsic. A fixed voltage is typically applied to an external node. The MOS gate structure allows current to be conducted between the external node and the intrinsic anode when on, and the PNPN structure conducts the current from the anode to the cathode when an appropriate voltage is applied to the gate contact. Regenerative feedback keeps the switch on once it begins to conduct. The MOS gate inhibits the flow of current between the external node and anode—and thereby turns off the switch—when off. When on, the MOS gate's channel resistance serves as a ballast resistor. | 10-02-2008 |
20100188902 | Differential, level-shifted EEPROM structures - Memory embodiments are provided to operate in memory systems which are configured to have a system ground and a system substrate that are biased at different voltages. At least one of these embodiments includes a memory cell and write and read circuits in which the memory cell is coupled to the system substrate and the write and read circuits are coupled to the system ground. The memory cell preferably has a cross-coupled pair of transistors which can be set in first and second states. The write circuit is arranged and level shifted to drive the cross-coupled pair into either selected one of the states and the read circuit is arranged and level shifted to provide a data signal indicative of the selected state. | 07-29-2010 |
20110063764 | APPARATUSES AND METHODS FOR A SCR-BASED CLAMPED ELECTROSTATIC DISCHARGE PROTECTION DEVICE - A SCR-based based electrostatic discharge protection device with a shunt path is provided. The shunt path operates at a low resistance when an enabling signal of the shunt path is asserted and a high resistance when the enabling signal is negated. The shunt path connects the cathode and the gate of the silicon-controlled rectifier, and provides a conductive path for displacement current from a parasitic capacitance when the shunt path is enabled, such as when power is provided to the device, and further allows the SCR to enter a low-resistance state when the shunt path is not enabled, such as when power is not provided to the device. A threshold trigger circuit is operably coupled between the anode and the cathode of the silicon-controlled rectifier and is configured to provide a current path when the anode voltage reaches a predetermined value lower than a breakdown voltage of the silicon-controlled rectifier. | 03-17-2011 |
20110115541 | APPARATUSES AND METHODS FOR A LEVEL SHIFTER WITH REDUCED SHOOT-THROUGH CURRENT - A level shifting circuit with reduced shoot-through current includes an output circuit comprising high-voltage devices with a pull up circuit configured for pulling up a voltage on an output signal to a high voltage responsive to a high-side control signal. The output circuit may also include a pull down circuit configured for pulling down the voltage on the output signal to a low voltage in responsive to a low-side control signal. The level shifting circuit can also include a high-side inverting buffer operably coupled between an edge-controlled signal and the high-side control signal, and a low-side buffer configured for driving the low-side control signal responsive to an input signal. The level shifting circuit may also include an edge-control buffer operably coupled between the input signal and the high-side inverting buffer and configured to generate the edge-controlled signal with a slow rise time relative to a fall time. | 05-19-2011 |
20110210879 | APPARATUSES AND METHODS FOR PHYSICAL LAYOUTS OF ANALOG-TO-DIGITAL CONVERTERS - Physical layouts of integrated circuits are provided, which may include an analog-to-digital converter including a plurality of comparators. Individual transistors of each comparator of the plurality are arranged in a one-dimensional row in a first direction. Neighboring comparators of the plurality of comparators are positioned relative each other in an abutting configuration in a second direction orthogonal to the first direction. The plurality of comparators may include multiple, inter-coupled, outputs. Such an ADC may be called a Benorion Analog-to-Digital Converter. A method for fabricating an integrated circuit is also provided. The method comprises arranging transistors of a first comparator in a one-dimensional row in a first direction, arranging transistors of at least one additional comparator in the one-dimensional row in the first direction, and arranging transistors of the first comparator and the at least one additional comparator relative to each other in a second direction orthogonal to the first direction. | 09-01-2011 |
20120001672 | Apparatuses and methods for a voltage level shifting - Level shifting circuits and a related method are disclosed herein. An embodiment of the present invention includes a voltage level shifter, comprising a first pull up transistor coupled to a high voltage signal and a first pull down transistor coupled between the first pull up transistor and a low voltage signal and controlled by an input signal. The voltage level shifter further includes a first bias transistor serially coupled between the first pull up transistor and the first bias transistor. A gate of the first bias transistor is coupled with a bias voltage signal. The voltage level shifter further includes a first additional pull up path coupled with the high voltage signal and a first node between the first pull up transistor and the first pull down transistor, and an output signal associated with the first node. The output signal is a level shifted voltage responsive to the input signal. | 01-05-2012 |
20120098597 | SWITCH FOR USE IN A PROGRAMMABLE GAIN AMPLIFIER - A switch circuit is provided. The switch circuit may include a first transistor having a source terminal to accept an input signal, a drain terminal to provide an output signal, and a gate; a power supply providing a gate voltage. The switch circuit may also include a circuit to couple a switch signal to the gate, wherein the circuit turns the first transistor ‘off’ for all values of the input signal when the switch signal is ‘low.’ A programmable gain amplifier (PGA) is also provided. The PGA may include an input stage having an input node to couple an input signal, and an output node to provide a gate signal, at least a first gain stage including a resistor and a switch circuit as above. A differential gain amplifier may be included to provide an output signal from the gain signal. | 04-26-2012 |
20120146688 | VOLTAGE LEVEL SHIFTING APPARATUSES AND METHODS - Level shifting circuits and related methods are disclosed herein. The level shifting circuit includes a cross-coupled pull-up circuit coupled to a higher supply voltage, an output signal, and an inverted output signal. An input signal transitions between a ground and a lower supply voltage and an inverted input signal transitions in a direction opposite from the input signal between the ground and the lower supply voltage. A first n-channel transistor has a gate coupled to the lower supply voltage, a drain coupled to the output signal, and a source coupled to the inverted input signal. A second n-channel transistor has a gate coupled to the lower supply voltage, a drain coupled to the inverted output signal, and a source coupled to the input signal. The level shifting circuit may be included in an IC with core logic in a first voltage domain and input/output logic in a second voltage domain. | 06-14-2012 |
20130257402 | APPARATUSES AND METHODS RESPONSIVE TO OUTPUT VARIATIONS IN VOLTAGE REGULATORS - A voltage regulator includes an amplifier to generate a difference voltage responsive to a comparison of a reference voltage and a feedback voltage. An output driver is coupled to the amplifier and drives a regulated output voltage responsive to the difference voltage. An impedance circuit is coupled between the output driver and a low power source and establishes the feedback voltage responsive to a current through the impedance circuit. A variation detector is operably coupled between the regulated output voltage and the difference voltage and is configured to modify the difference voltage. In some embodiments, the difference voltage is modified responsive to a rapid change of the regulated output voltage capacitively coupled to the variation detector. In other embodiments, the difference voltage is modified responsive to a rapid change of the feedback voltage capacitively coupled to the variation detector. | 10-03-2013 |
20130300487 | SEMICONDUCTOR SWITCH - A semiconductor switch comprises a PNPN structure arranged to provide an SCR-like functionality, and a MOS gate structure, preferably integrated on a common substrate. The switch includes ohmic contacts for the MOS gate, and for the cathode and gate regions of the PNPN structure; the anode contact is intrinsic. A fixed voltage is typically applied to an external node. The MOS gate structure allows current to be conducted between the external node and the intrinsic anode when on, and the PNPN structure conducts the current from the anode to the cathode when an appropriate voltage is applied to the gate contact. Regenerative feedback keeps the switch on once it begins to conduct. The MOS gate inhibits the flow of current between the external node and anode—and thereby turns off the switch—when off. When on, the MOS gate's channel resistance serves as a ballast resistor. | 11-14-2013 |
Patent application number | Description | Published |
20100013548 | POWER EFFICIENT CHARGE PUMP WITH CONTROLLED PEAK CURRENTS - A charge pump which uses a current limit resistor to limit in-rush current and peak currents. An additional advantage of such a charge pump is that, when being coupled to a boost converter or other switching converter utilizing an inductive energy storage element, it may avoid unnecessary power dissipation caused by the current limit resistor. | 01-21-2010 |
20100109740 | Clamp networks to insure operation of integrated circuit chips - Clamp networks are provided to insure successful operation of a variety of electronic circuits that are realized in the form of integrated circuit chips. These networks are especially suited for use in chips in which on-chip circuits generate a voltage to bias the chip substrate relative to the chip ground. The clamp networks are configured to drive a current between the chip ground and the chip substrate whenever the chip substrate begins to rise above the chip ground during turn on of the chip input voltage. The clamp networks thus insure that the chip substrate is properly biased when the input voltage has been established and that the chip, therefore, functions as intended. | 05-06-2010 |
20100156871 | Temperature-compensation networks - Temperature-compensation network embodiments are provided to generate compensation signals which may be useful in improving the performance of a variety of important systems. An embodiment includes a limit current mirror configured to provide a limit current, a current generator to provide a slope current whose magnitude varies with temperature, and an output current mirror positioned to receive the limit current and the slope current and configured to provide a compensation current. In addition, a floating voltage reference is provided for use in various networks which include the temperature-compensation networks. The temperature-compensation networks may be used to improve performance in systems such as a panel driver which provides turn-on and turn-off gate voltages to transistors in liquid crystal displays. | 06-24-2010 |
20100182085 | Error amplifier structures - Error amplifier structures are provided to generate an error signal in response to the difference between an input signal (e.g., a feedback current) and a reference signal (e.g., a bias current). Amplifier embodiments generally include a reference generator and a differencing amplifier. In at least one embodiment, the error generator is arranged to generate first and second bias voltages that correspond to the bias current. In at least one embodiment, the differencing amplifier is configured to provide a reference current to an output node in response to the first bias voltage, provide a feedback current to the output node in response to the second bias voltage, and generate an error current in response to a voltage at the output node. The error amplifier structures are suited for use in various systems such as negative switching regulators. | 07-22-2010 |
20110210878 | APPARATUSES AND METHODS FOR MULTIPLE-OUTPUT COMPARATORS AND ANALOG-TO-DIGITAL CONVERTERS - An analog-to-digital converter with comparators with multiple, inter-coupled, outputs is provided, which may be also called a Benorion Analog-to-Digital Converter (ADC) or a Benorion Converter. The analog-to-digital converter includes a plurality of comparators operably coupled for receiving an analog input signal and configured for comparing the analog input signal with a plurality of voltage reference signals. Each comparator of the plurality is configured for generating a plurality of comparator outputs comprising a primary comparator output, and at least one additional comparator output selected from the group consisting of positive comparator outputs and negative comparator. The analog-to-digital converter further includes a plurality of composite outputs, each composite output of the plurality comprising a combination of the primary comparator output from a corresponding comparator of the plurality and at least one additional comparator output from at least one additional comparator of the plurality of comparators. Other comparators and methods are provided. | 09-01-2011 |
20120223647 | APPARATUSES AND METHODS FOR REDUCING POWER IN DRIVING DISPLAY PANELS - Energy sharing circuits and related methods are disclosed herein. A high voltage can be selectively coupled to a first source line and a low voltage can be selectively coupled to a second source line during a first time period. During a subsequent time period, a first coupling switch is activated to inductively couple the first source line to the second source line and diode block the second source line from the first source line. During a subsequent time period, the low voltage is selectively coupled to the first source line and the high voltage is selectively coupled to the second source line. During a subsequent time period, a second coupling switch is activated to inductively couple the second source line to the first source line and diode block the first source line from the second source line. | 09-06-2012 |
20120235241 | LOW ON-RESISTANCE POWER TRANSISTOR, POWER CONVERTER, AND RELATED METHOD - A power transistor and a power converter are disclosed that may improve the on-resistance and corresponding silicon area of a power transistor. The power transistor may comprise a drain, a source, and a channel therebetween divided into a plurality of transistor stripes, the plurality of transistor stripes being grouped in a plurality of different groups. The power transistor may further comprise a first top metal associated with one of the drain and the source, and a second top metal associated with the other of the drain and the source. The second top metal includes at least one portion that is coupled to different groups of transistor stripes. A related method for determining a layout topology of a power transistor is also disclosed. | 09-20-2012 |
20120235846 | APPARATUSES AND METHODS FOR REDUCING ERRORS IN ANALOG TO DIGITAL CONVERTERS - Successive approximation Analog-to-digital converters (ADCs) and related methods are disclosed. A successive approximation ADC includes a comparator with a comparator output and inputs coupled to a common model signal and a compare input. Control logic generates one or more control signals responsive to the comparator output. A capacitor array includes first sides of capacitors operably coupled to an array output. The capacitor arrays selectively couples each of second sides of the capacitors to an analog input signal and one or more input reference signals responsive to the one or more control signals. A voltage limiter is operably coupled between the array output and the compare input of the comparator and limits a voltage on the compare input to within a predefined range relative to the array output. The successive approximation ADC may also be configured differentially with a second comparator and a second voltage limiter. | 09-20-2012 |