Patent application number | Description | Published |
20100049414 | CONTROL APPARATUS FOR ELECTRIC VEHICLE - The present invention provides a control apparatus for an electric vehicle which improves safety in an electric vehicle capable of traveling using creep torque. The electric vehicle includes a motor/generator for driving vehicle wheels. In a low vehicle speed region during startup or the like, creep torque is output from the motor/generator even when an accelerator pedal has not been operated, and therefore the electric vehicle can be started gently. The electric vehicle is also provided with a friction brake system for applying vehicle braking through frictional force. When an EV control unit for setting a target creep torque of the motor/generator determines that an abnormality has occurred in the friction brake system (step S20), the target creep torque is set lower than normal (step S30). Therefore, when an abnormality that may cause a reduction in a braking force occurs in the friction brake system, a propulsive force of the electric vehicle can be reduced, and as a result, the safety of the electric vehicle can be improved. | 02-25-2010 |
20100235043 | CONTROL APPARATUS FOR ELECTRIC VEHICLE - A creep travel capability of an electric vehicle is secured when an abnormality occurs in a brake sensor. When an accelerator operation amount reaches 0% in a low vehicle speed region, a target creep torque is set, whereupon a motor-generator is controlled toward the target creep torque. The target creep torque is reduced as a brake pedal is depressed in order to suppress heat generation and the like in the motor-generator during vehicle braking. Hence, in an electric vehicle in which the target creep torque is varied in accordance with the brake operation amount, when an abnormality occurs (step S | 09-16-2010 |
20110202220 | CONTROL DEVICE FOR ELECTRIC VEHICLE - A control device for an electric vehicle where a threshold storing unit is provided which stores two large and small thresholds and (first threshold>second threshold), and a drive state switching unit is provided which reduces torque output of a drive motor, while allowing accessories to operate, when a remaining energy capacity SOC from a remaining energy capacity detecting unit fails below the first threshold, and stops power supply to the drive motor, while allowing the accessories to operate, when the remaining energy capacity SOC from a remaining energy capacity detecting unit falls below the second threshold. | 08-18-2011 |
20110234159 | CHARGING DEVICE - When a battery of an electric vehicle charged with an external power source (AC 100 V), the electric vehicle and the external power source are connected with each other by the intermediary of a charging cable. Upon this charging, it is determined whether or not an input voltage from the external power source is 95 V or more. When the input voltage is less than 95 V, that is, a decline of the voltage in the charging cable is large, since a wiring resistance in the charging cable possibly increases, an upper limit of an output power to the battery is reduced. Consequently, the electric power delivered from the external power source can be limited, and thereby excessive heat generation is inhibited and safety is ensured. Furthermore, since the output power is caused to be limited when the wiring resistance possibly increases, the battery can be charged continuously. | 09-29-2011 |
20150106002 | DISPLAY DEVICE FOR VEHICLE - A vehicle speed acquisition unit acquires speed information indicating a vehicle speed. An output acquisition unit acquires output information indicating an output of a drive unit that drives the vehicle. An output rate derivation unit derives an output rate indicating a ratio of the output to a rated output of the vehicle at the current vehicle speed. A waste derivation unit derives waste information indicating a degree of waste of energy consumed by the vehicle. A display unit displays a waste status of the energy. When the speed is within a predetermined speed range and the output rate is within a preset first output range, the waste derivation unit derives the waste information indicating that the waste of energy when the speed is high is less than when the speed is low, even when the output rate is the same. | 04-16-2015 |
Patent application number | Description | Published |
20090258493 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A substance to be polished made of a silicon oxide film formed on a semiconductor substrate is chemically and mechanically polished and planarized by bringing the substance to be polished into contact with a polishing pad having a modulus of elasticity within a range of 400 to 600 megapascals and by relatively sliding the substance to be polished and the polishing pad, in a condition that a polishing pressure is within a range of 50 to 200 hectopascals and that a rotation number of the polishing pad is within a range of 10 to 80 rpm, and in a state that a polishing slurry containing cerium oxide particles and an anionic surfactant is supplied to the polishing pad. | 10-15-2009 |
20100240285 | POLISHING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A polishing apparatus includes: a wafer polishing unit including a polishing surface plate, an abrasive supply part supplying an abrasive to a polishing pad placed on the polishing surface plate, and a wafer holding part holding a semiconductor wafer; and a dressing unit including a dresser. The dresser has a pellet-shaped grindstone with abrasive particles fixed to a surface thereof. The pellet-shaped grindstone is divided into a first region along an outer peripheral portion thereof and a second region located inside the first region. A chipping preventing portion for the abrasive particles is provided in the first region. | 09-23-2010 |
20110070745 | POLISHING METHOD, POLISHING APPARATUS, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A polishing method includes performing conditioning process of injecting a conditioning agent onto a surface of a non-foam polishing pad arranged on a polishing table at a predetermined pressure, and polishing a surface of a polishing target while supplying a polishing slurry containing oxide particles and a surfactant onto the polishing pad, wherein an average of a residual cerium amount is equal to or smaller than 0.35 at % when a plurality of measurement regions, each 200 μm□ in area including the surface of the polishing pad, in a cross section of the polishing pad are measured after the conditioning process. | 03-24-2011 |
20110076833 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device for planarizing a silicon oxide film with chemical mechanical polishing using a silicon film formed on a semiconductor substrate as a stopper film, a surface modification film for hydrophilizing the surface of the silicon film is formed on an upper layer of the polysilicon film, and slurry for the chemical mechanical polishing contains cerium oxide particles, a surface active agent, and resin particles having a cationic or anionic functional group. | 03-31-2011 |
Patent application number | Description | Published |
20110205257 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - A semiconductor device includes: an LCD controller configured to output a plurality of image signals in parallel; a plurality of signal lines respectively corresponding to the plurality of image signals to be outputted in parallel; a plurality of terminal portions respectively connected to the plurality of signal lines; and delay circuits configured to delay a plurality of image signals, which are divided into a plurality of groups to the extent that the sum of each value of a current flowing through each signal line does not exceed a predetermined current value and outputted from a plurality of terminal portions, by a predetermined delay time from each other among the plurality of groups. | 08-25-2011 |
20110298127 | Semiconductor Device - A semiconductor device has a semiconductor substrate which has a plurality of pad electrodes provided on a top surface thereof and has an approximately rectangular shape; a rewiring layer which is provided with a plurality of contact wiring lines connected to the plurality of pad electrodes, is disposed on the semiconductor substrate through an insulating film, and has an approximately rectangular shape; and a plurality of ball electrodes which are provided on the rewiring layer. A plurality of first pad electrodes among the plurality of pad electrodes are arranged on an outer circumference of the semiconductor substrate to be along a first side of the semiconductor substrate, a plurality of first ball electrodes among the plurality of ball electrodes are arranged on an outer circumference of the rewiring layer to be along the first side, and any one of the plurality of first ball electrodes is connected to the first pad electrode positioned below the corresponding ball electrode through the contact wiring lines, and the first pad electrodes are not disposed on the lower side of the first ball electrodes positioned at an end of the first side. | 12-08-2011 |
20120025377 | SEMICONDUCTOR DEVICE AND METHOD OF DESIGNING A WIRING OF A SEMICONDUCTOR DEVICE - A semiconductor device has an LSI chip including a semiconductor substrate, an LSI core section provided at a center portion of the semiconductor substrate and serving as a multilayered wiring layer of the semiconductor substrate, a first rewiring layer provided adjacent to an outer periphery of the LSI core section on the semiconductor substrate and including a plurality of wiring layers, a first pad electrode disposed at an outer periphery of the first rewiring layer, and an insulation layer covering the first pad electrode. The semiconductor device includes a second rewiring layer provided on the LSI chip and including a rewiring connected to the first pad electrode. The semiconductor device includes a plurality of ball electrodes provided on the second rewiring layer. The first rewiring layer is electrically connected to the LSI core section and the first pad electrode. | 02-02-2012 |
20120242402 | SEMICONDUCTOR DEVICE AND WAFER - A semiconductor device has a semiconductor substrate. The semiconductor device has a plurality of LSI regions that are formed on the semiconductor substrate and are provided with a first power supply wiring layer including a first power supply wire. The semiconductor device has a first power supply terminal formed on the semiconductor substrate. The semiconductor device has a second power supply wiring layer including a second power supply wire that electrically connects the first power supply wire and the first power supply terminal, the second power supply wiring layer is formed in a dicing region between the LSI regions along a dicing line that separates the LSI regions and the dicing line region. A first barrier metal film is formed at least in the LSI regions at a boundary between the first power supply wire and the second power supply wire. | 09-27-2012 |
20130256886 | SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor substrate which has a plurality of pad electrodes provided on a top surface thereof and has an approximately rectangular shape; a rewiring layer which is provided with a plurality of contact wiring lines connected to the plurality of pad electrodes, is disposed on the semiconductor substrate through an insulating film, and has an approximately rectangular shape; and a plurality of ball electrodes which are provided on the rewiring layer. | 10-03-2013 |
20140071567 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a plurality of pads, a plurality of ESD protection circuits, each one of the ESD protection circuits being connected to a corresponding one of the plurality of pads, and an I/O circuit which is connected to a connection portion connecting output terminals of the plurality of ESD protection circuits to each other and which receives at least one input signal inputted into the plurality of pads. | 03-13-2014 |
20140284745 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes a pixel chip, a logic chip and one or more shielding layers. The one or more shielding layers are arranged between or within the pixel chip and/or the logic chip to shield or reduce the effect of electromagnetic interference, radiation generated noise, or electromagnetic waves generated in one portion of the solid-state imaging device from affecting another portion of the solid-state imaging device. | 09-25-2014 |
20150070538 | SOLID-STATE IMAGING APPARATUS - A solid-state imaging device according to an embodiment is a solid-state imaging device in which a plurality of pixel regions are formed into a two-dimensional array isolating the pixel regions from each other by element isolation regions, including a plurality of microlenses, a plurality of color filters arranged below the plurality of microlenses, a plurality of photoelectrical conversion sections arranged below the plurality of color filters and a magnetic field generating section provided on the element isolation regions between the plurality of microlenses and the plurality of photoelectrical conversion sections. | 03-12-2015 |