Patent application number | Description | Published |
20090267505 | Ligth emitting device package and method of manufacturing the same - The present invention relates to a light emitting device package and a method of manufacturing the same. There is provided a light emitting device package including a metal core; an insulating layer formed on the metal core; a metal layer formed on the insulating layer; a first cavity formed by removing parts of the metal layer and the insulating layer to expose a top surface of the metal core; and a light emitting device directly mounted on the top surface of the metal core in the first cavity and further there is provided a method of manufacturing the light emitting device package. | 10-29-2009 |
20110045668 | Method of manufacturing wafer level device package - There is provided a method of manufacturing a wafer level device package, the method including: forming a conductive pad on at least one area of a substrate; forming a first insulation layer on the substrate, the first insulation layer having an opening allowing the conductive pad to be exposed; forming a wiring layer connected to the conductive pad on the first insulation layer; forming a conductive diffusion barrier layer on the wiring layer to seal the wiring layer; forming a second insulation layer on the diffusion barrier layer, the second insulation layer having a contact hole allowing a part of diffusion barrier layer to be exposed; and forming a bump pad in the contact hole. This method allows for a reduction in processing time and costs by substituting a simple electroless plating process for a complicated photolithography process in the formation of the bump pad and the diffusion barrier layer. | 02-24-2011 |
20110061911 | Interposer and method for manufacturing the same - An interposer includes: an insulation plate where a via is formed, the insulation plate including a resin or a ceramic; a first upper redistribution layer electrically connected to the via along a circuit pattern designed on the top surface of the insulation plate; a first upper protection layer laminated to expose a portion of the first upper redistribution layer and protecting the first upper redistribution layer; a second upper redistribution layer electrically connected to the first upper redistribution layer and laminated along a designed circuit pattern designed; a second upper protection layer laminated to expose a portion of the second upper redistribution layer and protecting the second upper redistribution layer; and an under bump metallization (UBM) formed at the exposed portion of the second upper redistribution layer. | 03-17-2011 |
20110062533 | Device package substrate and method of manufacturing the same - A device package substrate includes: a substrate having a cavity formed on a top surface thereof, the cavity having a chip mounting region; a first interconnection layer formed to extend to the inside of the cavity; a second interconnection layer formed to be spaced apart from the first interconnection layer; a chip positioned in the chip mounting region so as to be connected to the first and second interconnection layers; an insulating layer formed to cover the first and second interconnection layers and the chip and having a contact hole exposing a part of the second interconnection layer; and a bump pad formed in the contact hole so as to be connected to external elements. | 03-17-2011 |
20120261816 | DEVICE PACKAGE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A device package substrate includes: a substrate having a cavity formed on a top surface thereof, the cavity having a chip mounting region; a first interconnection layer formed to extend to the inside of the cavity; a second interconnection layer formed to be spaced apart from the first interconnection layer; a chip positioned in the chip mounting region so as to be connected to the first and second interconnection layers; an insulating layer formed to cover the first and second interconnection layers and the chip and having a contact hole exposing a part of the second interconnection layer; and a bump pad formed in the contact hole so as to be connected to external elements. | 10-18-2012 |
20130026901 | LIGHT EMITTING DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a light emitting device package and a method of manufacturing the same. There is provided a light emitting device package including a metal core; an insulating layer formed on the metal core; a metal layer formed on the insulating layer; a first cavity formed by removing parts of the metal layer and the insulating layer to expose a top surface of the metal core; and a light emitting device directly mounted on the top surface of the metal core in the first cavity and further there is provided a method of manufacturing the light emitting device package. | 01-31-2013 |
20130029031 | METHOD FOR MANUFACTURING INTERPOSER - A method for manufacturing an interposer includes forming a via hole in an insulation plate including a resin or a ceramic; simultaneously forming resists for a first upper redistribution layer on the top surface of the insulation plate, and a resistor for a lower redistribution layer on the bottom surface of the insulation plate; plating copper to fill the via hole and simultaneously forming the first upper redistribution layer and the lower redistribution layer along a designed circuit pattern; and forming a first upper protection layer and a lower protection layer to expose a portion of the first upper redistribution layer and a portion of the lower redistribution layer. | 01-31-2013 |
Patent application number | Description | Published |
20090087951 | Method of manufacturing wafer level package - A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased. | 04-02-2009 |
20090253259 | Solder ball attachment jig and method for manufacturing semiconductor device using the same - Disclosed are a solder attachment jig and a method of manufacturing a semiconductor device using the same. The solder ball attachment jig, which arranges a solder ball to be aligned with a conductive post of a semiconductor wafer, can include a body and a receiving hole, which is formed on the body to hold the solder ball. Internal walls of the receiving hole that face each other are symmetrically inclined. Using the solder ball attachment jig in accordance with an embodiment of the present invention, the alignment of the solder ball can be improved while reducing the cost and simplifying the processes. | 10-08-2009 |
20090309216 | WAFER LEVEL PACKAGE AND MANUFACTURING METHOD THEREOF - A wafer level package and a manufacturing method thereof capable of reducing stress between an under bump metal and a bump. The wafer level package includes a substrate provided with a plurality of chip pads on a top surface; a first passivation layer to expose the chip pads; vias connected to the chip pads by passing through the first passivation layer; a metal wiring layer formed on the first passivation layer and connected to the vias; an under bump metal formed on the first passivation layer to be connected to the metal wiring layer and having a buffer pattern separated through a trench on a center; a second passivation layer formed on the first passivation layer to expose the under bump metal; a first bump formed on the buffer pattern; and a second bump filling the trench and formed on the first bump and the under bump metal. | 12-17-2009 |
20100117218 | Stacked wafer level package and method of manufacturing the same - The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost. | 05-13-2010 |
20100144152 | Method of manufacturing semiconductor package - The present invention relates to a method of manufacturing a semiconductor package capable of simplifying a process and remarkably reducing a production cost by including the steps of: preparing a different bonded panel including at least one metal layer; forming a pad unit electrically connected to the metal layer; mounting a semiconductor chip over the different bonded panel to be electrically connected to the pad unit; sealing the semiconductor chip; forming a rearrangement wiring layer by etching the metal layer; and forming an external connection unit electrically connected to the rearrangement wiring layer. | 06-10-2010 |
20100149770 | Semiconductor stack package - The present invention relates to a semiconductor stack package including: a printed circuit board; a first semiconductor chip mounted on the printed circuit board; a second semiconductor chip mounted on the printed circuit board in parallel with the first semiconductor chip; a first rearrangement wiring layer positioned on the first semiconductor chip; a second rearrangement wiring layer which constitutes one circuit together with the first rearrangement wiring layer and is positioned on the second semiconductor chip; and a third semiconductor chip which is electrically connected to the first and second rearrangement wiring layers and of which both ends are separately positioned on the first and second semiconductor chips. | 06-17-2010 |
20100159646 | Method of manufacturing wafer level package - The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units. | 06-24-2010 |
20110201156 | Method of manufacturing wafer level package including coating resin over the dicing lines - A method of manufacturing a wafer level package including: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant and cutting a wafer level package along the dicing lines coated with the resin into units. | 08-18-2011 |
Patent application number | Description | Published |
20090302468 | Printed circuit board comprising semiconductor chip and method of manufacturing the same - Disclosed is a printed circuit board including a semiconductor chip, which includes a semiconductor chip having a connection pad, which is exposed, on the upper surface thereof, a first solder ball formed on the connection pad and having a first melting point, a printed circuit board having an external connection terminal formed at the outermost circuit layer thereof, and a second solder ball formed on the external connection terminal, connected to the first solder ball, and having a second melting point higher than the first melting point. In the printed circuit board including a semiconductor chip, the distance between the printed circuit board and the semiconductor chip is increased, thus realizing high resistance to flexure due to the difference in thermal expansion coefficient between the printed circuit board and the semiconductor chip. | 12-10-2009 |
20120012378 | PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - Disclosed is a printed circuit board, including a base member, an insulating layer formed on each of both surfaces of the base member so that the surfaces of the base member are flattened, a circuit layer formed on the insulating layer, and a via for connecting the circuit layer formed on one surface of the base member with the circuit layer formed on the other surface of the base member. A method of manufacturing the printed circuit board is also provided. | 01-19-2012 |
20120073870 | PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - Disclosed is a printed circuit board, including a base member, an insulating layer formed on each of both surfaces of the base member so that the surfaces of the base member are flattened, a circuit layer formed on the insulating layer, and a via for connecting the circuit layer formed on one surface of the base member with the circuit layer formed on the other surface of the base member. A method of manufacturing the printed circuit board is also provided. | 03-29-2012 |
20130149437 | METHOD FOR MANUFACTURING PRINTED CIRCUIT BOARD - Disclosed herein is a method for manufacturing a printed circuit board. | 06-13-2013 |
20130153275 | PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a printed circuit board and a method for manufacturing the same. According to a preferred embodiment of the present invention, the printed circuit board includes: a base substrate; circuit patterns formed in a circuit region on the base substrate; dummy patterns formed in a dummy region on the base substrate; and an insulating layer formed above the circuit patterns and the dummy patterns by a slit die coating method. | 06-20-2013 |
20140042604 | THREE-DIMENSIONAL (3D) SEMICONDUCTOR PACKAGE - Disclosed herein is a three-dimensional (3D) semiconductor package. The 3D semiconductor package includes a printed circuit board, a main interposer that is formed on the printed circuit board, a semiconductor device that is formed on the main interposer, and a support interposer that is disposed on the same plane as a plane of the semiconductor device, or disposed between the main interposer and the semiconductor device. Here, each of the main interposer, the semiconductor device, and the support interposer may include a through-via formed based on a thickness direction of the printed circuit board. | 02-13-2014 |