Patent application number | Description | Published |
20080296657 | Non-Volatile Memory Devices and Methods of Manufacturing Non-Volatile Memory Devices - A non-volatile memory device includes a substrate and a tunnel insulation layer pattern, such that each portion of the tunnel insulation pattern extends along a first direction and adjacent portions of the tunnel insulation layer pattern may be separated in a second direction that is substantially perpendicular to the first direction. A non-volatile memory device may include a gate structure formed on the tunnel insulation layer pattern. The gate structure may include a floating gate formed on the tunnel insulation layer pattern along the second direction, a first conductive layer pattern formed on the floating gate in the second direction, a dielectric layer pattern formed on the first conductive layer pattern along the second direction, and a control gate formed on the dielectric layer pattern in the second direction. | 12-04-2008 |
20080310238 | Methods of Programming Data in a Non-Volatile Memory Device and Methods of Operating a Nand Flash Memory Device Using the Same - Methods of programming data in a non-volatile memory cell are provided. A memory cell according to some embodiments may include a gate structure that includes a tunnel oxide layer pattern, a floating gate, a dielectric layer and a control gate sequentially stacked on a substrate, impurity regions that are formed in the substrate at both sides of the gate structure, and a conductive layer pattern that is arranged spaced apart from and facing the floating gate. Embodiments of such methods may include applying a programming voltage to the control gate, grounding the impurity regions and applying a fringe voltage to the conductive layer pattern to generate a fringe field in the floating gate. | 12-18-2008 |
20090127633 | NON-VOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME - In one embodiment, a semiconductor memory device includes a substrate having first and second active regions. The first active region includes a first source and drain regions and the second active region includes a second source and drain regions. A first interlayer dielectric is located over the substrate. A first conductive structure extends through the first interlayer dielectric. A first bit line is on the first interlayer dielectric. A second interlayer dielectric is on the first interlayer dielectric. A contact hole extends through the second and first interlayer dielectrics. The device includes a second conductive structure within the contact hole and extending through the first and second interlayer dielectrics. A second bit line is on the second interlayer dielectric. A width of the contact hole at a bottom of the second interlayer dielectric is less than or substantially equal to a width at a top of the second interlayer dielectric. | 05-21-2009 |
20090309154 | SELECTION TRANSISTOR - Provided are a selection transistor and a method of fabricating the same. A selection transistor can be formed on an active region in a semiconductor substrate to include a gate electrode that includes recessed portions of a sidewall of the gate electrode which are recessed inward adjacent lower portions of the gate electrode to define a T-shaped cross section of the gate electrode. A tunnel insulating layer can be located between the gate electrode and the active region. | 12-17-2009 |
20110095377 | SEMICONDUCTOR MEMORY DEVICES - In some embodiments, a semiconductor memory device includes a substrate that includes a cell array region and a peripheral circuit region. The semiconductor memory device further includes a device isolation pattern on the substrate. The device isolation pattern defines a first active region and a second active region within the cell array region and a third active region in the peripheral circuit region. The semiconductor memory device further includes a first common source region, a plurality of first source/drain regions, and a first drain region in the first active region. The semiconductor memory device further includes a second common source region, a plurality of second source/drain regions, and a second drain region in the second active region. The semiconductor memory device further includes a third source/drain region in the third active region. The semiconductor memory device further includes a common source line contacting the first and second common source regions. | 04-28-2011 |
20110170356 | Methods of Programming Data in a Non-Volatile Memory Device and Methods of Operating a Nand Flash Memory Device Using the Same - Methods of programming data in a non-volatile memory cell are provided. A memory cell according to some embodiments may include a gate structure that includes a tunnel oxide layer pattern, a floating gate, a dielectric layer and a control gate sequentially stacked on a substrate, impurity regions that are formed in the substrate at both sides of the gate structure, and a conductive layer pattern that is arranged spaced apart from and facing the floating gate. Embodiments of such methods may include applying a programming voltage to the control gate, grounding the impurity regions and applying a fringe voltage to the conductive layer pattern to generate a fringe field in the floating gate. | 07-14-2011 |
Patent application number | Description | Published |
20090233399 | METHOD OF MANUFACTURING PHOTOELECTRIC DEVICE - In a method of manufacturing a photoelectric device, a transparent conductive layer is formed on a substrate, and the transparent conductive layer is partially etched using an etching solution including hydrofluoric acid. Thus, a transparent electrode having a concavo-convex pattern on its surface is formed. When the transparent conductive layer is partially etched, a haze of the transparent electrode may be controlled by adjusting an etching time of the transparent conductive layer. Also, since the etching solution is sprayed to the transparent conductive layer to etch the transparent conductive layer, the concavo-convex pattern on the surface of the transparent electrode may be easily formed even though the size of the substrate increases. | 09-17-2009 |
20100154869 | PHOTOELECTRIC CONVERSION DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed herein is a photoelectric conversion device having a semiconductor substrate including a front side and back side, a protective layer formed on the front side of the semiconductor substrate, a first non-single crystalline semiconductor layer formed on the back side of the semiconductor substrate, a first conductive layer including a first impurity formed on a first portion of a back side of the first non-single crystalline semiconductor layer, and a second conductive layer including the first impurity and a second impurity formed on a second portion of the back side of the first non-single crystalline semiconductor layer. | 06-24-2010 |
20120112542 | METHOD OF TRIMMING A SOLAR ENERGY ASSEMBLY - A method of electrically eliminating defective solar cell units that are disposed within an integrated solar cells module and a method of trimming an output voltage of the integrated solar cells module are provided, where the solar cells module has a large number (e.g., 50 or more) of solar cell units integrally disposed therein and initially connected in series one to the next. The method includes providing a corresponding plurality of repair pads, each integrally extending from a respective electrode layer of the solar cell units, and providing a bypass conductor integrated within the module and extending adjacent to the repair pads. Pad-to-pad spacings and pad-to-bypass spacings are such that pad-to-pad connecting bridges may be selectively created between adjacent ones of the repair pads and such that pad-to-bypass connecting bridges may be selectively created between the repair pads and the adjacently extending bypass conductor. | 05-10-2012 |
20120129295 | METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - Disclosed herein is a photoelectric conversion device having a semiconductor substrate including a front side and back side, a protective layer formed on the front side of the semiconductor substrate, a first non-single crystalline semiconductor layer formed on the back side of the semiconductor substrate, a first conductive layer including a first impurity formed on a first portion of a back side of the first non-single crystalline semiconductor layer, and a second conductive layer including the first impurity and a second impurity formed on a second portion of the back side of the first non-single crystalline semiconductor layer. | 05-24-2012 |
Patent application number | Description | Published |
20090035906 | Method of manufacturing a non-volatile semiconductor device - Example embodiments relate to methods of fabricating a non-volatile memory device. According to example embodiments, a method of fabricating a non-volatile memory device may include forming at least one gate structure on an upper face of a substrate. The at least one gate structure may include a tunnel insulation layer pattern, a charge storing layer pattern, a dielectric layer pattern and a control gate. According to example embodiments, a method of fabricating a non-volatile memory device may also include forming a silicon nitride layer on the upper face of the substrate to cover the at least one gate structure, forming an insulating interlayer on the silicon nitride layer on the upper face of the substrate, and providing an annealing gas toward the upper face of the substrate and a lower face of the substrate to cure defects of the tunnel insulation layer pattern. | 02-05-2009 |
20090166714 | Non-volatile memory device - A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers. | 07-02-2009 |
20090190398 | Method of programming data in a NAND flash memory device and method of reading data in the NAND flash memory device - A method of programming data in a NAND flash memory device including at least one even bitline and at least one odd bitline, the method including programming N-bit data into first cells coupled to the at least one even bitline or the at least one odd bitline and programming M-bit data into second cells coupled to the other of the at least one even bitline and the at least one odd bitline, where N is a natural number greater than one and M is a natural number greater than N. | 07-30-2009 |
20090221138 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device, including forming a plurality of gate structures on a substrate, the gate structures each including a hard mask pattern stacked on a gate conductive pattern, forming an insulating layer pattern between the gate structures at least partially exposing a top surface of the hard mask pattern, forming a trench that exposes at least a top surface of the gate conductive pattern by selectively removing the hard mask pattern, and forming a silicide layer on the exposed gate conductive pattern. | 09-03-2009 |
20100128522 | Flash memory device and programming/erasing method of the same - A flash memory device includes a bulk region, first through nth memory cell transistors arranged in a row on the bulk region, first through nth word lines respectively connected to gates of the first through nth memory cell transistors, a first dummy cell transistor connected to the first memory cell transistor, a first dummy word line connected to a gate of the first dummy cell transistor, a first selection transistor connected to the first dummy cell transistor, a first selection line connected to a gate of the first selection transistor, and a voltage control unit connected to the first selection line, the voltage control unit being adapted to output to the first selection line a voltage lower than a voltage applied to the bulk region, in an erasing mode for erasing the first through nth memory cell transistors. | 05-27-2010 |
20120015512 | METHOD OF MANUFACTURING NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers. | 01-19-2012 |