Patent application number | Description | Published |
20080286966 | METHOD OF FORMING A DIELECTRIC CAP LAYER FOR A COPPER METALLIZATION BY USING A HYDROGEN BASED THERMAL-CHEMICAL TREATMENT - A new technique is disclosed in which a barrier/cap layer for a copper based metal line is formed by using a thermal-chemical treatment based on hydrogen with a surface modification on the basis of a silicon-containing precursor followed by an in situ plasma based deposition of silicon based dielectric barrier material. The thermal-chemical cleaning process is performed in the absence of any plasma ambient. | 11-20-2008 |
20100055899 | PARTICLE REDUCTION IN PECVD PROCESSES FOR DEPOSITING LOW-K MATERIAL BY USING A PLASMA ASSISTED POST-DEPOSITION STEP - When forming dielectric materials of reduced dielectric constant in sophisticated metallization systems, the creation of defect particles on the dielectric material may be reduced during a plasma enhanced deposition process by inserting an inert plasma step after the actual deposition step. | 03-04-2010 |
20110027989 | INCREASED DENSITY OF LOW-K DIELECTRIC MATERIALS IN SEMICONDUCTOR DEVICES BY APPLYING A UV TREATMENT - A silicon-based low-k dielectric material is formed on the basis of a single precursor material, such as OMTCS, without incorporating a porogen species. To this end, the initial deposition of the low-k dielectric material may be formed on the basis of a reduced process temperature, while a subsequent treatment, such as a UV treatment, may allow the adjustment of the final material characteristics without causing undue out-gassing of volatile organic components. | 02-03-2011 |
20110053294 | UV IRRADIANCE MONITORING IN SEMICONDUCTOR PROCESSING USING A TEMPERATURE DEPENDENT SIGNAL - In a UV process tool for semiconductor processing, a temperature-dependent signal may be used as a monitor signal for determining the momentary irradiance of the UV radiation source. Consequently, a fast and reliable monitoring and/or controlling of the irradiance of UV process tools may be accomplished. | 03-03-2011 |
20120235304 | ULTRAVIOLET (UV)-REFLECTING FILM FOR BEOL PROCESSING - Semiconductor devices are formed with a dielectric stack by forming an UV reflecting layer between cured and uncured ULK layers during BEOL processing. Embodiments include forming a first ultra low-k (ULK) layer on a semiconductor element, curing the first ULK layer, forming an ultraviolet (UV) reflecting layer on the first ULK layer, forming a second ULK layer on the UV reflecting layer, and irradiating the second ULK layer with UV light. | 09-20-2012 |
Patent application number | Description | Published |
20090113212 | Multiprocessor electronic circuit including a plurality of processors and electronic data processing system - A multiprocessor electronic circuit and an electronic data processing system comprising such circuit are disclosed for reducing the power consumption and the chip area consumption of a multiprocessor system having cryptographic functionality. In one embodiment, the multiprocessor electronic circuit comprises a plurality of processors, a single cryptographic processing unit that comprises a plurality of input/output buffer pairs and two cryptographic engines, a cipher engine and a hash engine, and associated control logic. | 04-30-2009 |
20090204793 | RAW Hazard Detection and Resolution for Implicitly Used Registers - The present invention provides a system, apparatus, and method for detecting and resolving read-after-write hazards encountered in processors following the dispatch of instructions requiring one or more implicit reads in a processor. | 08-13-2009 |
20110320743 | MEMORY ORDERED STORE SYSTEM IN A MULTIPROCESSOR COMPUTER SYSTEM - A system and computer implemented method for storing of data in the memory of a computer system in order at a fast rate is provided. The method includes launching a first store to memory. A wait counter is initiated. A second store to memory is speculatively launched when the wait counter expires. The second store to memory is cancelled when the second store achieves coherency prior to the first store to memory. | 12-29-2011 |
20130332716 | BRANCH TARGET BUFFER PRELOAD TABLE - Embodiments relate to using a branch target buffer preload table. An aspect includes receiving a search request to locate branch prediction information associated with a branch instruction. Searching is performed for an entry corresponding to the search request in a branch target buffer and a branch target buffer preload table in parallel. Based on locating a matching entry in the branch target buffer preload table corresponding to the search request and failing to locate the matching entry in the branch target buffer, a victim entry is selected to overwrite in the branch target buffer. Branch prediction information of the matching entry is received from the branch target buffer preload table at the branch target buffer. The victim entry in the branch target buffer is overwritten with the branch prediction information of the matching entry. | 12-12-2013 |
20130339683 | INSTRUCTION FILTERING - Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text. | 12-19-2013 |
20130339693 | SECOND-LEVEL BRANCH TARGET BUFFER BULK TRANSFER FILTERING - Embodiments relate to second-level branch target buffer bulk transfer filtering. An aspect includes a system for second-level branch target buffer bulk transfer filtering. The system includes a first-level branch target buffer and a second-level branch target buffer coupled to a processing circuit. The processing circuit is configured to perform a method. The method includes receiving branch target buffer miss indicators, receiving instruction cache miss indicators, and recording information about the branch target buffer miss indicators and the instruction cache miss indicators in search trackers. Based on detecting, by the processing circuit, a search tracker representing a correlated pair of the branch target buffer miss indicators and the instruction cache miss indicators, the search tracker is activated by the processing circuit to perform a bulk transfer from the second-level branch target buffer to the first-level branch target buffer. | 12-19-2013 |
20130339694 | SEMI-EXCLUSIVE SECOND-LEVEL BRANCH TARGET BUFFER - Embodiments relate to a semi-exclusive second-level branch target buffer. An aspect includes a system for a semi-exclusive second-level branch target buffer. The system includes a first-level branch target buffer (BTB1), a branch target buffer preload table (BTBP), and a second-level branch target buffer (BTB2) coupled to a processing circuit. The processing circuit is configured to perform a method. The method includes performing a search to locate entries in the BTB2 having a memory region corresponding to a search request. Based on locating entries in the BTB2, a bulk transfer of located entries is performed from the BTB2 to the BTBP. A state associated with the located entries is updated to encourage exclusivity between the BTB1 and the BTB2. Based on transferring a BTBP entry from the BTBP to the BTB1, a BTB1 entry is evicted from the BTB1. The evicted BTB1 entry is transferred from the BTB1 to the BTB2. | 12-19-2013 |
20130339695 | ASYNCHRONOUS LOOKAHEAD SECOND LEVEL BRANCH TARGET BUFFER - Embodiments relate to asynchronous lookahead hierarchical branch prediction. An aspect includes a system for asynchronous lookahead hierarchical branch prediction. The system includes a first-level branch target buffer and a second-level branch target buffer coupled to a processing circuit. The processing circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with a search address, and searching for an entry corresponding to the search request in the first-level branch target buffer. Based on failing to locate a matching entry in the first-level branch target buffer corresponding to the search request, a secondary search is initiated to locate entries in the second-level branch target buffer having a memory region corresponding to the search request. Based on locating the entries in the second-level branch target buffer, a bulk transfer of the entries is performed from the second-level branch target buffer. | 12-19-2013 |
20130339696 | SELECTIVELY BLOCKING BRANCH INSTRUCTION PREDICTION - Embodiments relate to selectively blocking branch instruction predictions. An aspect includes a computer system for performing selective branch prediction. The system includes memory and a processor, and the system is configured to perform a method. The method includes detecting a branch-prediction blocking instruction in a stream of instructions and blocking branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction. | 12-19-2013 |
20130339698 | SELECTIVELY BLOCKING BRANCH INSTRUCTION PREDICTION - Embodiments relate to selectively blocking branch instruction predictions. An aspect includes computer implemented method for performing selective branch prediction. The method includes detecting, by a processor, a branch-prediction blocking instruction in a stream of instructions and blocking, by the processor, branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction. | 12-19-2013 |
20140082337 | BRANCH TARGET BUFFER PRELOAD TABLE - Embodiments relate to using a branch target buffer preload table. An aspect includes receiving a search request to locate branch prediction information associated with a branch instruction. Searching is performed for an entry corresponding to the search request in a branch target buffer and a branch target buffer preload table in parallel. Based on locating a matching entry in the branch target buffer preload table corresponding to the search request and failing to locate the matching entry in the branch target buffer, a victim entry is selected to overwrite in the branch target buffer. Branch prediction information of the matching entry is received from the branch target buffer preload table at the branch target buffer. The victim entry in the branch target buffer is overwritten with the branch prediction information of the matching entry. | 03-20-2014 |
20140082338 | INSTRUCTION FILTERING - Embodiments relate to instruction filtering. An aspect includes a computer-implemented method for instruction filtering. The method includes detecting, by a processor, a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in a tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. The method further includes marking, by the processor, instruction text of the subsequently fetched instruction to indicate that the subsequently fetched instruction is a previously executed tracked instruction based on the indication of the tracked instruction from the tracking array. The method additionally includes preventing an action of a tracked instruction logic block based on detecting the marked instruction text. | 03-20-2014 |
20150019848 | ASYNCHRONOUS LOOKAHEAD HIERARCHICAL BRANCH PREDICTION - Embodiments relate to asynchronous lookahead hierarchical branch prediction. An aspect includes a computer-implemented method for asynchronous lookahead hierarchical branch prediction using a second-level branch target buffer. The method includes receiving a search request to locate branch prediction information associated with a search address. The method further includes searching, by a processing circuit, for an entry corresponding to the search request in a first-level branch target buffer. The method also includes, based on failing to locate a matching entry in the first-level branch target buffer corresponding to the search request, initiating, by the processing circuit, a secondary search to locate entries in the second-level branch target buffer having a memory region corresponding to the search request. The method additionally includes, based on locating the entries in the second-level branch target buffer, performing a bulk transfer of the entries from the second-level branch target buffer. | 01-15-2015 |
20150019849 | SEMI-EXCLUSIVE SECOND-LEVEL BRANCH TARGET BUFFER - Embodiments relate to a semi-exclusive second-level branch target buffer. An aspect includes a computer-implemented method for a semi-exclusive second-level branch target buffer. The method includes performing a search to locate entries in a BTB | 01-15-2015 |