Patent application number | Description | Published |
20080246142 | Heat dissipation unit and a semiconductor package that has the heat dissipation unit - A heat dissipation unit and a semiconductor package having the same are disclosed. The semiconductor package includes a carrier; an electronic component mounted on and electrically connected to the carrier; a heat dissipation unit, which includes a flat section attached to the electronic component, extension sections connected to the flat section, and a heat dissipation section connected to the extension sections; and an encapsulant encapsulating the electronic component and the heat dissipation unit, wherein stress releasing sections are at least disposed at intersectional corners between the extension sections and the flat section so as to prevent projections from being formed by concentrated stresses in a punching process of the heat dissipation unit, thereby maintaining flatness of the flat section and further preventing circuits of the electronic component from being damaged due to a contact point produced between the electronic component and the flat section in a molding process. | 10-09-2008 |
20080277786 | Semiconductor package substrate - A semiconductor package substrate includes a body having an upper surface and a lower surface opposite to one another, a plurality of circuit layers formed in the body, a plurality of solder pads formed on the upper surface of the body, and a plurality of solder ball pads formed on the lower surface of the body. Each of the solder pads is electrically connected to one of the solder ball pads via the circuit layers and conductive structures disposed between the circuit layers, wherein the circuit layers and conductive structures are configured to expand outwardly in a fan-out manner so as to provide more space between the circuit layers closer to the lower surface of the body such that part of the solder pad-solder ball pad electrical connections can comprise a plurality of parallel connected conductive structures formed in the space, thereby enhancing the heat conducting passageway and the effect of heat-dissipation without having to dispose more solder pads on surface of the substrate. | 11-13-2008 |
20080303134 | Semiconductor package and method for fabricating the same - A semiconductor package and a method for fabricating the same are disclosed, which includes: providing a carrier board, forming a plurality of metal bumps on the carrier board, forming a metal layer on the carrier board to encapsulate the metal bumps, having at least one semiconductor chip electrically connected to the metal layer, then forming an encapsulant on the carrier board to encapsulate the semiconductor chip, and next removing the carrier board and the metal bumps to correspondingly form a plurality of grooves on surface of the encapsulant, wherein bottom and sides of the grooves are covered with the metal layer to allow electroconductive components to be effectively positioned in the grooves and completely bonded with the metal layer. | 12-11-2008 |
20090008801 | Semiconductor device and method for fabricating the same - This invention discloses a semiconductor device and a method for fabricating the same. The method includes providing a flexible carrier board having a first surface and a second surface opposite thereto; forming a metal lead layer and a first heat dissipating metal layer on the first surface of the flexible carrier board, and forming a second heat dissipating metal layer on the second surface of the flexible carrier board; providing a chip having an active surface and an opposed non-active surface, wherein a plurality of solder pads are formed on the active surface of the chip, each of the solder pads has a metal bump formed thereon and corresponding in position to the metal lead layer, and heat dissipating bumps are formed between the metal bumps corresponding in position to the first heat dissipating metal layer. | 01-08-2009 |
20090283303 | PACKAGE SUBSTRATE HAVING LANDLESS CONDUCTIVE TRACES - A package substrate having landless conductive traces is proposed, which includes a core layer with a plurality of plated through holes formed therein, and a plurality of conductive traces formed on at least a surface of the core layer. Each of the conductive traces has a connection end, a bond pad end, and a base body connecting the connection end and the bond pad end, the conductive trace is electrically connected to a corresponding one of the plated through holes through the connection end, and the connection end has a width greater than that of the base body but not greater than the diameter of the plated through hole, thereby increasing the contact area between the conductive trace and the plated through hole and preventing the contact surface of the conductive trace with the plated through hole from cracking. | 11-19-2009 |
Patent application number | Description | Published |
20140008787 | CONDUCTIVE BUMP STRUCTURE AND METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE - A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate. | 01-09-2014 |
20140008819 | SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE AND METHODS OF FABRICATING THE SAME - A substrate structure is provided, including a substrate and a strengthening member bonded to a surface of the substrate. The strengthening member has a CTE (Coefficient of Thermal Expansion) less than that of the substrate so as to effectively prevent warpage from occurring to the substrate structure. | 01-09-2014 |
20140027926 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element. | 01-30-2014 |
20140070424 | SEMICONDUCTOR PACKAGE, METHOD OF FABRICATING THE SEMICONDUCTOR PACKAGE, AND INTERPOSER STRUCTURE OF THE SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers. | 03-13-2014 |
20140073087 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package is provided, including: providing a substrate having opposite first and second surfaces and a plurality of conductive through holes penetrating the first and second surfaces, disposing the substrate on a first carrier through the second surface thereof, and keeping the first carrier flat and free of warpage; attaching at least a first semiconductor chip to the first surface of the substrate and electrically connecting the first semiconductor chip and the substrate; removing the first carrier; and attaching the substrate to a packaging substrate through the second surface thereof and electrically connecting the substrate and the packaging substrate, thereby preventing the semiconductor package from warpage, increasing product yield, reducing fabrication cost, and improving thermal dissipation. | 03-13-2014 |
20140077387 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package is provided, which includes the steps of: cutting a substrate into a plurality of interposers; disposing the interposers on a carrier, wherein the interposers are spaced from one another by a distance; disposing at least a semiconductor element on each of the interposers; forming an encapsulant to encapsulate the interposers and the semiconductor elements; and removing the carrier. Therefore, by cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers. | 03-20-2014 |
20140084484 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top surface of the interposer; a redistribution layer formed on the encapsulant and the top surface of the interposer; and at least a semiconductor element disposed on the redistribution layer. The top surface of the interposer is flush with a surface of the encapsulant so as for the redistribution layer to have a planar surface for disposing the semiconductor element, thereby preventing warpage of the interposer and improving the reliability of electrical connection between the redistribution layer and the semiconductor element. | 03-27-2014 |
20140118019 | METHOD OF TESTING A SEMICONDUCTOR STRUCTURE - A method of testing a semiconductor structure is provided, including providing at least a semiconductor structure having an interposer and a semiconductor element disposed on the interposer; disposing the semiconductor structure on a carrier having a supporting portion, with the interposer being supported by the supporting portion; and performing a test process. The semiconductor structure has been tested for its electrical performance prior to packaging, thereby eliminating the necessity for a conductive pathway to pass through an inner circuit of an package substrate. Therefore, the testing process is accelerated and the time is save. | 05-01-2014 |
20140127838 | METHOD OF TESTING A SEMICONDUCTOR PACKAGE - A method of testing a semiconductor package is provided, including: disposing at least an interposer on a top surface of an adhesive layer, the interposer having a first surface and a second surface opposite to the first surface, a plurality of conductive elements disposed between the second surface of the interposer and the adhesive layer; disposing at least a semiconductor chip on the first surface of the interposer, and performing an electrical test on the semiconductor chip via the conductive elements, wherein if there are a plurality of semiconductor chips that are disposed on the first surface of the interposer, the step of disposing the semiconductor chip and performing the electrical test on the semiconductor chip is iterated; and removing the adhesive layer. By using the method, the fabrication cost and equipment cost of the semiconductor package are reduced, and product yield is increased. | 05-08-2014 |
20140127864 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package is provided, including providing an interposer having a plurality of conductive elements, disposing the interposer on a carrier having a plurality of recessed portions for the conductive elements to be received therein such that the interposer is coupled to the carrier, attaching the semiconductor element to the interposer, and removing the carrier. Coupling the interposer to the carrier prevents the conductive elements from displacement under pressure. Therefore, the conductive elements will not be in poor or no electrical contact with the interposer. | 05-08-2014 |
20140138791 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly. | 05-22-2014 |
20140191386 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided. The semiconductor package includes a substrate; a semiconductor element having opposite active and inactive surfaces and disposed on the substrate via the active surface thereof, wherein the inactive surface of the semiconductor element is roughened; a thermally conductive layer bonded to the inactive surface of the semiconductor element; and a heat sink disposed on the thermally conductive layer. The roughened inactive surface facilitates the bonding between the semiconductor element and the thermally conductive layer so as to eliminate the need to perform a gold coating process and the use of a flux and consequently reduce the formation of voids in the thermally conductive layer. | 07-10-2014 |
20140264928 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an interposer; forming a first encapsulant on the interposer for encapsulating the first semiconductor elements; disposing a plurality of second semiconductor elements on the first semiconductor elements; forming a second encapsulant on the first semiconductor elements and the first encapsulant for encapsulating the second semiconductor elements; and thinning the interposer, thereby reducing the overall stack thickness and preventing warpage of the interposer. | 09-18-2014 |