Patent application number | Description | Published |
20080230925 | SOLDER-BUMPING STRUCTURES PRODUCED BY A SOLDER BUMPING METHOD - A method for solder bumping provides a substrate and forms a film on the substrate. The film has openings therethrough. A stencil is aligned on the film. The stencil has openings therethrough over the openings through the film. Solder paste is printed onto the substrate and into the openings through the stencil and the openings through the film. The solder paste is reflowed to form solder balls therefrom. The stencil and the film are then removed. | 09-25-2008 |
20080272368 | Extended Redistribution Layers Bumped Wafer - A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad. | 11-06-2008 |
20080272464 | Semiconductor Wafer Having Through-Hole Vias on Saw Streets with Backside Redistribution Layer - A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. The metal vias are surrounded by organic material. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. The RDL and THV provide expanded interconnect flexibility to adjacent die. Repassivation layers are formed between the RDL on the second surface of the die for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The RDL provide electrical interconnect to the adjacent die. Bond wires and solder bumps also provide electrical connection to the semiconductor die. | 11-06-2008 |
20080272465 | Semiconductor Die with Through-Hole Via on Saw Streets and Through-Hole Via in Active Area of Die - A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. Metal vias are also formed through the contact pads on the active area of the die. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. Repassivation layers are formed between the RDL for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The vias through the saw streets and vias through the active area of the die, as well as the RDL, provide electrical interconnect to the adjacent die. | 11-06-2008 |
20080272470 | Same Size Through-Hole Via Die Stacked Package - A semiconductor package includes a substrate or leadframe structure. A plurality of interconnected dies, each incorporating a plurality of through-hole vias (THVs) disposed along peripheral surfaces of the plurality of dies, are disposed over the substrate or leadframe structure. The plurality of THVs are coupled to a plurality of bond pads through a plurality of a metal traces. A top surface of a first THV is coupled to a bottom surface of a second THV. An encapsulant is formed over a portion of the substrate or leadframe structure and the plurality of dies. | 11-06-2008 |
20080272476 | Through-Hole Via On Saw Streets - A semiconductor device is manufactured by, first, providing a wafer designated with a saw street guide. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A plurality of via holes is formed in the organic material. Each of the plurality of via holes is patterned to each of a plurality of bond pad locations on the plurality of dies. A conductive material is deposited in each of the plurality of via holes. | 11-06-2008 |
20080272477 | Package-on-Package Using Through-Hole Via Die on Saw Streets - A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure. An encapsulant is formed over a portion of the first die and the first semiconductor package. | 11-06-2008 |
20080272504 | Package-in-Package Using Through-Hole via Die on Saw Streets - A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die. | 11-06-2008 |
20080274603 | Semiconductor Package Having Through-Hole Via on Saw Streets Formed with Partial Saw - A method of forming through-hole vias in a semiconductor wafer involves forming a semiconductor wafer with many die having contact pads disposed on each die. The semiconductor wafer has saw street guides between each die. A trench is formed in the saw streets. The trench extends partially but not completely through the wafer. The uncut portion of the saw street guides below the trench along a backside of the wafer maintains structural support for the semiconductor wafer. The trench is filled with organic material. Via holes are formed in the organic material. Traces are formed between the contact pads and via holes. Conductive material is deposited in the via holes to form metal vias. The uncut portion of the saw streets below the trench along the backside of the semiconductor wafer portion is removed. The semiconductor wafer is singulated along the saw street guides to separate the die. | 11-06-2008 |
20090001531 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRAL INNER LEAD AND PADDLE - An integrated circuit package system includes: fabricating a lead frame including: providing inner leads having an inner lead pitch of progressive length, forming a lead shoulder, on the inner leads, having a shoulder height of a progressive height, and forming outer leads coupled to the lead shoulder and the inner leads; mounting an integrated circuit die on the lead frame; and molding a package body on the lead frame and the integrated circuit die. | 01-01-2009 |
20090001593 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OVERHANGING CONNECTION STACK - An integrated circuit package system comprising: providing a first conductive line adjacent to a second conductive line; forming a first connection stack over the first conductive line with the first connection stack overhanging the second conductive line; connecting an integrated circuit device and the first connection stack; and encapsulating the integrated circuit device and the first connection stack. | 01-01-2009 |
20090032932 | INTEGRATED CIRCUIT PACKAGING SYSTEM FOR FINE PITCH SUBSTRATES - An integrated circuit packaging system comprising: forming a substrate including; patterning a bonding pad on the substrate, patterning a first signal trace coupled to the bonding pad, patterning a second signal trace on the substrate, and connecting a pedestal on the second signal trace; mounting an integrated circuit on the substrate; and coupling an electrical interconnect between the integrated circuit, the bonding pad, the pedestal, or a combination thereof. | 02-05-2009 |
20090032975 | Semiconductor Device and Method of Providing Common Voltage Bus and Wire Bondable Redistribution - A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer. | 02-05-2009 |
20090079049 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WARP-FREE CHIP - An integrated circuit package system includes: providing an integrated circuit wafer having an active side and a backside; forming a stress-relieving layer on the backside; forming an adhesion layer on the stress-relieving layer; dicing the integrated circuit wafer into a semiconductor chip with the stress-relieving layer and the adhesion layer on the backside of the semiconductor chip; and mounting the semiconductor chip over electrical interconnects. | 03-26-2009 |
20090091042 | INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING DIE HAVING RELIEVED ACTIVE REGION - An integrated circuit package system includes: providing a substrate; attaching a base die to the substrate, the base die having a relief region with a shaped cross-section; and connecting a bond wire between an active base surface of the base die and the substrate, the bond wire extending through the shaped cross-section of the relief region. | 04-09-2009 |
20090127680 | INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH WIRE-IN-FILM ENCAPSULANT - A multiple encapsulation integrated circuit package-in-package system includes: dicing a top integrated circuit wafer having a bottom encapsulant thereon to form a top integrated circuit die with the bottom encapsulant; positioning internal leadfingers adjacent and connected to a bottom integrated circuit die; pressing the bottom encapsulant on to the bottom integrated circuit die; connecting the top integrated circuit die to external leadfingers adjacent the internal leadfingers; and forming a top encapsulant over the top integrated circuit die. | 05-21-2009 |
20090127683 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INSULATOR - An integrated circuit package system includes: providing a connection array; attaching a base integrated circuit adjacent the connection array; attaching a package integrated circuit over the base integrated circuit; attaching a package die connector to the package integrated circuit and the connection array; and applying a wire-in-film insulator over the package integrated circuit, the package die connector, the base integrated circuit, and the connection array, wherein the connection array is partially exposed. | 05-21-2009 |
20090127720 | DROP-MOLD CONFORMABLE MATERIAL AS AN ENCAPSULATION FOR AN INTEGRATED CIRCUIT PACKAGE SYSTEM - An integrated circuit package system includes: providing an integrated circuit; mounting a lead on the periphery of the integrated circuit; connecting the integrated circuit to the lead with an interconnect; and forming a conformable material by pressing the conformable material on the integrated circuit, the lead, and the interconnect. | 05-21-2009 |
20090142883 | Leaded Stacked Packages Having Elevated Die Paddle - A semiconductor package includes a leadframe, an elevated die paddle disposed above the leadframe, a first die attached to a lower surface of the elevated die paddle to support the first die within the semiconductor package, and a second die attached to the first die. A method of manufacturing a semiconductor package includes providing a leadframe having a lower lead and an elevated die paddle structure, attaching a first die to the elevated die paddle structure with a die adhesive (DA) for supporting the first die within the semiconductor package, and wire bonding the first die to the lower lead. | 06-04-2009 |
20090146268 | INTEGRATED CIRCUIT PACKAGE SYSTEM FOR ELECTROMAGNETIC ISOLATION - An integrated circuit package system comprising: providing a lead frame; forming an integrated circuit package including the lead frame; providing a selectively exposed area on the lead frame; and coating a conductive shielding layer on the integrated circuit package for coupling the selectively exposed area. | 06-11-2009 |
20090146269 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SHIELD - An integrated circuit package system includes: forming a first lead and a second lead; connecting an integrated circuit die with the first lead; forming an encapsulation over the integrated circuit die, the first lead, and the second lead with a portion of a top side of the second lead exposed; and forming a shield over the encapsulation, the first lead, and the second lead with the shield not in contact with the first lead. | 06-11-2009 |
20090152688 | INTEGRATED CIRCUIT PACKAGE SYSTEM FOR SHIELDING ELECTROMAGNETIC INTERFERENCE - An integrated circuit package system comprising: providing a substrate; coupling an integrated circuit to the substrate; mounting a shielding element around the integrated circuit; applying a conductive shielding layer on the shielding element; and coupling a system interconnect to the shielding element. | 06-18-2009 |
20090166823 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEAD LOCKING STRUCTURE - A mountable integrated circuit package system includes: providing a base; depositing a photoresist on the base; patterning the photoresist with an opening; filling the opening with a metal; depositing a further metal on the metal to form a lead pad; removing the photoresist; attaching a die over the base; bonding wires between the die and the lead pad; encapsulating the die and the lead pad in an encapsulation formed into a lead pad lock adjacent the lead pad; and removing the base. | 07-02-2009 |
20090166824 | LEADLESS PACKAGE SYSTEM HAVING EXTERNAL CONTACTS - A leadless package system includes: providing a chip carrier having indentations defining a pattern for a protrusion for external contact terminals; placing an external coating layer in the indentations in the chip carrier; layering a conductive layer on top of the external coating layer; depositing an internal coating layer on the conductive layer; patterning the internal coating layer and the conductive layer to define external contact terminals with a T-shape profile; connecting an integrated circuit die to the external contact terminals; encapsulating the integrated circuit die and external contact terminals; and separating the chip carrier from the external coating layer. | 07-02-2009 |
20090212401 | PACKAGE SYSTEM FOR SHIELDING SEMICONDUCTOR DIES FROM ELECTROMAGNETIC INTERFERENCE - The present invention provides a package system including: providing a semiconductor die with a contact pad and a ground pad, mounting the semiconductor die on a package substrate using and adhesive layer, forming a vertical conductive structure on top of the ground pad in the semiconductor die, encapsulating at least portions of the semiconductor die, the vertical conductive structure, and the package substrate using an encapsulant, covering at least portions of the encapsulant and the vertical conductive structure with a shielding layer to place the vertical conductive structure in electrical contact with the shielding layer, and connecting the shielding layer to the package substrate. | 08-27-2009 |
20090212429 | Semiconductor Device and Method of Supporting a Wafer During Backgrinding and Reflow of Solder Bumps - A semiconductor device is made by providing a semiconductor wafer having an active surface, forming an under bump metallization layer on the active surface of the semiconductor wafer, forming a first photosensitive layer on the active surface of the semiconductor wafer, exposing a selected portion of the first photosensitive layer over the under bump metallization layer to light, removing a portion of a backside of the semiconductor wafer, opposite to the active surface, prior to developing the exposed portion of the first photosensitive layer, developing the exposed portion of the first photosensitive layer after removing the portion of the backside of the semiconductor wafer, and depositing solder material over the under bump metallization layer to form solder bumps. The remaining portion of the first photosensitive layer is then removed. A second photosensitive layer or metal stencil can be formed over the first photosensitive layer. | 08-27-2009 |
20090224402 | Semiconductor Package Having Semiconductor Die with Internal Vertical Interconnect Structure and Method Therefor - A semiconductor wafer is made by forming a first conductive layer over a sacrificial substrate, mounting a semiconductor die to the sacrificial substrate, depositing an insulating layer over the semiconductor die and first conductive layer, exposing the first conductive layer and contact pad on the semiconductor die, forming a second conductive layer over the insulating layer between the first conductive layer and contact pad, forming solder bumps on the second conductive layer, depositing an encapsulant over the semiconductor die, first conductive layer, and interconnect structure, and removing the sacrificial substrate after forming the encapsulant to expose the conductive layer and semiconductor die. A portion of the encapsulant is removed to expose a portion of the solder bumps. The solder bumps are sized so that each extends the same outside the encapsulant. The semiconductor die are stacked by electrically connecting the solder bumps. | 09-10-2009 |
20090230531 | Semiconductor Package with Penetrable Encapsulant Joining Semiconductor Die and Method Thereof - A semiconductor device is made by mounting a first semiconductor die to a first substrate, forming a first encapsulant over the first semiconductor die, and forming a second encapsulant over the first encapsulant. The second encapsulant is penetrable, thermally conductive material. A second semiconductor die is mounted to the second substrate. A bond wire electrically connects the second semiconductor die to the second substrate. A passive circuit element is mounted to the second substrate. Leading with the second encapsulant, the first substrate is pressed onto the second substrate so that the second encapsulant completely covers the second semiconductor die, bond wire, and passive circuit element. The second encapsulant is then cured. A third encapsulant is formed over the first and second substrates. A shield can be disposed over the second semiconductor die with openings for the second encapsulant to flow through when pressed onto the second substrate. | 09-17-2009 |
20090243045 | Through Hole Vias at Saw Streets Including Protrusions or Recesses for Interconnection - A semiconductor package includes a semiconductor die having a contact pad formed over a top surface of the semiconductor die. The semiconductor die may include an optical device. In one embodiment, a second semiconductor die is deposited over the semiconductor die. The package includes an insulating material deposited around a portion of the semiconductor die. In one embodiment, the insulating material includes an organic material. A first through hole via (THV) is formed in the insulating material using a conductive material. The first THV may form a protrusion extending beyond a bottom surface of the semiconductor die opposite the top surface and be connected to a first semiconductor device. A redistribution layer (RDL) may be deposited over the semiconductor die. The RDL forms an electrical connection between the contact pad of the semiconductor die and the first THV. | 10-01-2009 |
20090250813 | INTEGRATED CIRCUIT SOLDER BUMPING SYSTEM - An integrated circuit solder bumping system provides a substrate and forms a redistribution layer on the substrate. An insulation layer is formed on the redistribution layer. The insulation layer has a plurality of openings therethrough. A first UBM layer of titanium is deposited on the insulation layer and in the openings therethrough. A second UBM layer of chromium/copper alloy is deposited on the first UBM layer. A third UBM layer of copper is deposited on the second UBM layer. UBM pads of at least two different sizes are formed from the UBM layers. Solder paste is printed over at least some of the UBM pads. The solder paste is reflowed to form at least smaller solder bumps on at least some of the UBM pads. Bigger solder bumps are formed on at least some of the UBM pads. | 10-08-2009 |
20090261466 | Semiconductor Device and Method of Forming Vertical Interconnect Structure Using Stud Bumps - A semiconductor device is made by forming a conductive layer over a temporary carrier. The conductive layer includes a wettable pad. A stud bump is formed over the wettable pad. The stud bump can be a stud bump or stacked bumps. A semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the stud bump. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure includes a first IPD and is electrically connected to the stud bump. The carrier is removed. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The second interconnect structure includes a second IPD. The first or second IPD includes a capacitor, resistor, or inductor. The semiconductor devices are stackable and electrically connected through the stud bump. | 10-22-2009 |
20090267236 | Through-Hole Via on Saw Streets - A semiconductor device is manufactured by, first, providing a wafer designated with a saw street guide. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A plurality of via holes is formed in the organic material. Each of the plurality of via holes is patterned to each of a plurality of bond pad locations on the plurality of dies. A conductive material is deposited in each of the plurality of via holes. | 10-29-2009 |
20090283870 | Semiconductor Device and Method of Conforming Conductive Vias Between Insulating Layers in Saw Streets - A semiconductor device is made by disposing a plurality of semiconductor die on a carrier and creating a gap between each of the semiconductor die. A first insulating material is deposited in the gap. A portion of the first insulating material is removed. A conductive layer is formed over the semiconductor die. A conductive lining is conformally formed on the remaining portion of the first insulating material to form conductive via within the gap. The conductive vias can be tapered or vertical. The conductive via is electrically connected to a contact pad on the semiconductor die. A second insulating material is deposited in the gap over the conductive lining. A portion of the conductive via may extend outside the first and second insulating materials. The semiconductor die are singulated through the gap. The semiconductor die can be stacked and interconnected through the conductive vias. | 11-19-2009 |
20090283893 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SLOTTED DIE PADDLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system including: providing a selective slot die paddle having selective slots and edge pieces around the perimeter; providing extended leads protruding into the selective slots; mounting an integrated circuit die on the selective slot die paddle; and coupling bond wires between the integrated circuit die, the edge pieces, the extended leads, or a combination thereof. | 11-19-2009 |
20090291526 | Semiconductor Package Having Through-Hole Vias on Saw Streets Formed with Partial Saw - A method of forming through-hole vias in a semiconductor wafer involves forming a semiconductor wafer having a plurality of die with contact pads disposed on a surface of each die. The semiconductor wafer has a saw street between each die. A trench is cut in the saw street without using support material to support the wafer. The trench extends only partially through the wafer. The uncut portion of the saw street below the trench along a backside of the wafer providing structural support for the wafer without support material during formation a plurality of conductive vias in the saw streets adjacent to the contact pads, and electrical connection of the conductive vias to the contact pads. The uncut portion of the saw street below the trench along the backside of the wafer portion is removed. The semiconductor wafer is singulated along the saw street to separate the die. | 11-26-2009 |
20090291527 | Semiconductor Package Having Through-Hole Vias on Saw Streets Formed with Partial Saw - A method of forming through-hole vias in a semiconductor wafer involves forming a semiconductor wafer having a plurality of die with contact pads disposed on a surface of each die. The semiconductor wafer has a saw street between each die. A trench is formed in the saw street without using support material to support the semiconductor wafer. The trench extends only partially through the semiconductor wafer. The portion of the saw street below the trench along a backside of the semiconductor wafer has sufficient thickness to maintain structural support for the semiconductor wafer without support material during formation of conductive vias between the die, and electrically connection of the conductive vias to the contact pads. The portion of the saw street below the trench along the backside of the semiconductor wafer is removed. The semiconductor wafer is singulated along the saw street to separate the die. | 11-26-2009 |
20090291528 | Semiconductor Package Having Through-Hole Vias on Saw Streets Formed with Partial Saw - A method of forming through-hole vias in a semiconductor wafer involves forming a semiconductor wafer having a plurality of die. A trench is formed between the semiconductor die. The trench extending partially through the semiconductor wafer. The portion of the semiconductor wafer below the trench along a backside of the wafer maintaining structural support for the wafer during the processing steps of forming a plurality of conductive vias between the die, and forming traces to electrically connect the conductive vias to contact pads on the die. The portion of the semiconductor wafer below the trench along the backside of the wafer is removed. The semiconductor wafer is singulated to separate the die. The singulation can be performed through the conductive vias to make half conductive vias or between the conductive vias to make full conductive vias. The die can be stacked and electrically connected through the conductive vias. | 11-26-2009 |
20090294899 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING EMBEDDED PASSIVE CIRCUIT ELEMENTS INTERCONNECTED TO THROUGH HOLE VIAS - A semiconductor die has a first insulating material disposed around a periphery of the die. A portion of the first insulating material is removed to form a through hole via (THV). Conductive material is deposited in the THV. A second insulating layer is formed over an active surface of the die. A first passive circuit element is formed over the second insulating layer. A first passive via is formed over the THV. The first passive via is electrically connected to the conductive material in the THV. The first passive circuit element is electrically connected to the first passive via. A third insulating layer is formed over the first passive circuit element. A second passive circuit element is formed over the third insulating layer. A fourth insulating layer is formed over the second passive circuit element. A plurality of semiconductor die is stacked and electrically interconnected by the conductive via. | 12-03-2009 |
20090294911 | Semiconductor Device and Method of Forming Double-Sided Through Vias in Saw Streets - A semiconductor device is made by creating a gap between semiconductor die on a wafer. An insulating material is deposited in the gap. A first portion of the insulating material is removed from a first side of the semiconductor wafer to form a first notch. The first notch is less than a thickness of the semiconductor die. A conductive material is deposited into the first notch to form a first portion of the conductive via within the gap. A second portion of the insulating material is removed from a second side of the semiconductor wafer to form a second notch. The second notch extends through the insulating material to the first notch. A conductive material is deposited into the second notch to form a second portion of the conductive via within the gap. The semiconductor wafer is singulated through the gap to separate the semiconductor die. | 12-03-2009 |
20090294914 | Semiconductor Device and Method of Forming Through Vias with Reflowed Conductive Material - A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die. | 12-03-2009 |
20090302435 | Semiconductor Device and Method of Shielding Semiconductor Die from Inter-Device Interference - A plurality of stacked semiconductor wafers each contain a plurality of semiconductor die. The semiconductor die each have a conductive via formed through the die. A gap is created between the semiconductor die. A conductive material is deposited in a bottom portion of the gap. An insulating material is deposited in the gap and over the semiconductor die. A portion of the insulating material in the gap is removed to form a recess between each semiconductor die extending to the conductive material. A shielding layer is formed over the insulating material and in the recess to contact the conductive material. The shielding layer isolates the semiconductor die from inter-device interference. A substrate is formed as a build-up structure on the semiconductor die adjacent to the conductive material. The conductive material electrically connects to a ground point in the substrate. The gap is singulating to separate the semiconductor die. | 12-10-2009 |
20090302439 | Semiconductor Device Having Electrical Devices Mounted to IPD Structure and Method of Shielding Electromagnetic Interference - A semiconductor device is made by forming an integrated passive device (IPD) structure on a substrate, mounting first and second electrical devices to a first surface of the IPD structure, depositing encapsulant over the first and second electrical devices and IPD structure, forming a shielding layer over the encapsulant, and electrically connecting the shielding layer to a conductive channel in the IPD structure. The conductive channel is connected to ground potential to isolate the first and second electrical devices from external interference. A recess can be formed in the encapsulant material between the first and second electrical devices. The shielding layer extends into the recess. An interconnect structure is formed on a second surface of the IPD structure. The interconnect structure is electrically connected to the first and second electrical devices and IPD structure. A shielding cage can be formed over the first electrical device prior to depositing encapsulant. | 12-10-2009 |
20090302445 | Method and Apparatus for Thermally Enhanced Semiconductor Package - A semiconductor package includes a semiconductor die. Encapsulant is flowed around a portion of the semiconductor die. The encapsulant is etched and a conductive material is deposited into the etched portion of the encapsulant to form a thermally conductive structure. In one embodiment, a trench is etched into the encapsulant and a thermally conductive material is deposited into the trench to form a thermal channel. In alternative embodiments, thermally conductive through hole vias (THVs) are formed in the encapsulant. A thermally conductive pad may be formed over the semiconductor die to facilitate removal of heat energy from the hot spots of the semiconductor die. A thermally conductive trace is formed to interconnect the thermal channel and the thermally conductive pad. A heat sink may be deposited over the semiconductor package. The packages are singulated by cutting through the encapsulant or the thermal channel. | 12-10-2009 |
20090302478 | Semiconductor device and method of forming recessed conductive vias in saw streets - A semiconductor die has an insulating material disposed in a peripheral region around the die. A blind via is formed through the gap. A conductive material is deposited in the blind via to form a conductive via. A conductive layer is formed between the conductive via and contact pad on the semiconductor die. A protective layer is formed over the front side of the semiconductor die. A portion of the insulating material and conductive via is removed from a backside of the semiconductor die opposite the front side of the semiconductor die so that a thickness of the conductive via is less than a thickness of the semiconductor wafer. The insulating material and conductive via are tapered. The wafer is singulated through the gap to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically interconnected through the conductive vias. | 12-10-2009 |
20090321898 | CONFORMAL SHIELDING INTEGRATED CIRCUIT PACKAGE SYSTEM - An integrated circuit package system includes: providing a substrate with an integrated circuit mounted thereover; mounting a structure, having ground pads, over the integrated circuit; encapsulating the integrated circuit with an encapsulation while leaving the structure partially exposed; and attaching a conformal shielding to the encapsulation and electrically connected to the grounding pads. | 12-31-2009 |
20090321899 | INTEGRATED CIRCUIT PACKAGE SYSTEM STACKABLE DEVICES - An integrated circuit package system includes: providing a finger lead having a side with an outward exposed area and an inward exposed area separated by a lead cavity; positioning a chip adjacent the finger lead and connected to the finger lead; and a stack encapsulant encapsulating the chip and the finger lead with the outward exposed area and the inward exposed area of the finger lead substantially exposed. | 12-31-2009 |
20100001391 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORTED STACKED DIE - An integrated circuit package system provides a leadframe having a short lead finger, a long lead finger, and a support bar. A first die is placed in the leadframe. An adhesive is attached to the first die, the long lead finger, and the support bar. A second die is offset from the first die. The offset second die is attached to the adhesive. The first die is electrically connected to the short lead finger. The second die is electrically connected to at least the long lead finger or the short lead finger. At least portions of the leadframe, the first die, and the second die are encapsulated in an encapsulant. | 01-07-2010 |
20100007029 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING STEPPED-DOWN RDL AND RECESSED THV IN PERIPHERAL REGION OF THE DEVICE - A semiconductor die has a peripheral region around the die. An insulating layer is formed over the semiconductor die. A portion of the insulating layer and peripheral is removed to form a recess around the semiconductor die. A conductive layer is deposited over the insulating layer and recess. The conductive layer is electrically connected to contact pads on the semiconductor die and conforms to a step into the recess. A gap is created through the conductive layer and peripheral region around the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. The conductive THV is recessed with respect to a surface of the semiconductor die. The conductive THV is electrically connected to the conductive layer. | 01-14-2010 |
20100009468 | METHOD OF MANUFACTURE FOR SEMICONDUCTOR PACKAGE WITH FLOW CONTROLLER - A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate or semiconductor package at one or more various locations. Flow controllers can control or direct the flow of the molding compound during the encapsulation process. Flow controllers can be sized, shaped, and positioned in order to smooth out the flow of the molding compound, such that the speed of the flow is substantially equivalent over areas of the substrate containing dies and over areas of the substrate without dies. In this manner, defects such as voids in the encapsulation, wire sweeping, and wire shorts can be substantially avoided during encapsulation. | 01-14-2010 |
20100019359 | Semiconductor Device and Method of Forming Shielding Along a Profile Disposed in Peripheral Region Around the Device - A semiconductor device has a semiconductor die with a peripheral region around the die. A first insulating material is deposited in the peripheral region. A conductive via is formed through the first insulating material. A conductive layer is formed over the semiconductor die. The conductive layer is electrically connected between the conductive via and a contact pad of the semiconductor die. A second insulating layer is deposited over the first insulating layer, conductive layer, and semiconductor die. A profile is formed in the first and second insulating layers in the peripheral region. The profile is tapered, V-shaped, truncated V-shape, flat, or vertical. A shielding layer is formed over the first and second insulating layers to isolate the semiconductor die from inter-device interference. The shielding layer conforms to the profile in the peripheral region and electrically connects the shielding layer to the conductive via. | 01-28-2010 |
20100025833 | RDL PATTERNING WITH PACKAGE ON PACKAGE SYSTEM - An integrated circuit package system includes: providing an internal device; encapsulating the internal device with an encapsulation having an outer surface; and forming a redistribution line having connection points on the outer surface of the encapsulation. | 02-04-2010 |
20100032821 | TRIPLE TIER PACKAGE ON PACKAGE SYSTEM - An integrated circuit package system includes: providing a first package having a first interposer mounted over a first integrated circuit and the first integrated circuit encapsulated by a first encapsulation; and connecting a second package over the first interposer and on the first encapsulation, the second package including a second integrated circuit having a wire-in-film adhesive thereover, a second interposer mounted on the wire-in-film adhesive and encapsulated by a second encapsulation encapsulating the second integrated circuit, the second interposer including an interconnection pad for connecting a third package to the top thereof. | 02-11-2010 |
20100033941 | EXPOSED INTERCONNECT FOR A PACKAGE ON PACKAGE SYSTEM - An integrated circuit package system includes: providing a substrate; mounting an integrated circuit above the substrate; connecting an interposer to the integrated circuit with a wire-in-film adhesive; connecting an exposed interconnect having an upper surface to the substrate; and encapsulating the integrated circuit with an encapsulation. | 02-11-2010 |
20100072570 | Semiconductor Device and Method of Forming Embedded Passive Circuit Elements Interconnected to Through Hole Vias - A semiconductor die has a first insulating material disposed around a periphery of the die. A portion of the first insulating material is removed to form a through hole via (THV). Conductive material is deposited in the THV. A second insulating layer is formed over an active surface of the die. A first passive circuit element is formed over the second insulating layer. A first passive via is formed over the THV. The first passive via is electrically connected to the conductive material in the THV. The first passive circuit element is electrically connected to the first passive via. A third insulating layer is formed over the first passive circuit element. A second passive circuit element is formed over the third insulating layer. A fourth insulating layer is formed over the second passive circuit element. A plurality of semiconductor die is stacked and electrically interconnected by the conductive via. | 03-25-2010 |
20100072596 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING PLANAR INTERCONNECT - An integrated circuit package system includes: mounting an integrated circuit, having a planar interconnect, over a carrier with the planar interconnect at a non-active side of the integrated circuit and an active side of the integrated circuit facing the carrier; connecting the integrated circuit and the carrier; connecting the planar interconnect and the carrier; and forming an encapsulation over the integrated circuit, the carrier, and the planar interconnect. | 03-25-2010 |
20100072630 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ADHESIVE SEGMENT SPACER - An integrated circuit package system includes attaching an adhesive segment spacer to an interposer assembly; mounting an integrated circuit over a carrier; mounting the interposer assembly over the integrated circuit with the adhesive segment spacer exposing an inner region of the integrated circuit and covering a periphery of the integrated circuit; and forming an encapsulation over the integrated circuit, the interposer assembly, and the adhesive segment spacer with the interposer assembly exposed with a recess in the encapsulation. | 03-25-2010 |
20100096731 | Semiconductor Device and Method of Forming Stepped-Down RDL and Recessed THV in Peripheral Region of the Device - A semiconductor die has a peripheral region around the die. An insulating layer is formed over the semiconductor die. A portion of the insulating layer and peripheral is removed to form a recess around the semiconductor die. A conductive layer is deposited over the insulating layer and recess. The conductive layer is electrically connected to contact pads on the semiconductor die and conforms to a step into the recess. A gap is created through the conductive layer and peripheral region around the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. The conductive THV is recessed with respect to a surface of the semiconductor die. The conductive THV is electrically connected to the conductive layer. | 04-22-2010 |
20100102456 | Semiconductor Device and Method of Forming Double-Sided Through Vias in Saw Streets - A semiconductor device is made by creating a gap between semiconductor die on a wafer. An insulating material is deposited in the gap. A first portion of the insulating material is removed from a first side of the semiconductor wafer to form a first notch. The first notch is less than a thickness of the semiconductor die. A conductive material is deposited into the first notch to form a first portion of the conductive via within the gap. A second portion of the insulating material is removed from a second side of the semiconductor wafer to form a second notch. The second notch extends through the insulating material to the first notch. A conductive material is deposited into the second notch to form a second portion of the conductive via within the gap. The semiconductor wafer is singulated through the gap to separate the semiconductor die. | 04-29-2010 |
20100117205 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes forming a paddle having a paddle top surface, the paddle top surface having a depression provided therein, forming an external interconnect having a lead tip and a lead body with the lead body having a first recess segment along a length-wise dimension of the lead body, connecting a device over the paddle top surface and the external interconnect, and filling a substantially electrically nonconductive material in the depression. | 05-13-2010 |
20100133534 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND FLIP CHIP AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an interposer having a first side and a second side with the first side having a device contact and an interconnect contact and with the second side having a test pad; mounting an integrated circuit over the device contact; and applying an underfill between the integrated circuit and the interposer. | 06-03-2010 |
20100140770 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING ASYMMETRIC ENCAPSULATION STRUCTURES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a first internal integrated circuit structure and a second internal integrated circuit structure over the substrate; connecting the first internal integrated circuit structure and the second internal integrated circuit structure to the substrate with internal interconnects; forming asymmetric encapsulation structures above the first internal integrated circuit structure and the second internal integrated circuit structure; and encapsulating the first internal integrated circuit structure and the internal interconnects with an encapsulation. | 06-10-2010 |
20100140783 | Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area Around the Device for Electrical Interconnection to Other Devices - A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps. | 06-10-2010 |
20100140795 | Semiconductor Device and Method of Forming Conductive Pillars in Recessed Region of Peripheral Area Around the Device for Electrical Interconnection to Other Devices - A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A first insulating layer is formed over the die. A recessed region with angled sidewall is formed in the peripheral area. A first conductive layer is formed over the first insulating layer outside the recessed region and further into the recessed region. A conductive pillar is formed over the first conductive layer within the recessed region. A second insulating layer is formed over the first insulating layer, conductive pillar, and first conductive layer such that the conductive pillar is exposed from the second insulating layer. A dicing channel partially through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the conductive pillar. | 06-10-2010 |
20100140799 | Extended Redistribution Layers Bumped Wafer - A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad. | 06-10-2010 |
20100140813 | INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes providing an integrated circuit having an active side and a non-active side; forming a channel through the integrated circuit; forming an indent, having a flange and an indent side, from a peripheral region of the non-active side; and forming a conformal interconnect, having an offset segment, a sloped segment, and a flange segment, under the indent. | 06-10-2010 |
20100142174 | INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes providing an integrated circuit having an active side and a non-active side; forming an indent, having a flange and an indent side, from a peripheral region of the active side; and forming a conformal interconnect, having an elevated segment, a slope segment, and a flange segment, over the indent. | 06-10-2010 |
20100148336 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING THROUGH SILICON VIAS WITH PARTIAL DEPTH METAL FILL REGIONS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a silicon substrate having a circuitry layer; creating a partial via through the circuitry layer; filling the partial via with a plug having a bottom surface; creating a recess that is angled outward and exposes the bottom surface of the plug; and coating the recess with a recess-insulation-layer while leaving the bottom surface of the plug exposed. | 06-17-2010 |
20100148355 | INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING WAFER LEVEL CHIP SCALE PACKAGING - An integrated circuit package system that includes: providing a substrate with a protective coating; attaching a labeling film to a support member in a separate process; joining the protective coating and the labeling film; and dicing the substrate, the protective coating, and the labeling film to form the integrated circuit package system. | 06-17-2010 |
20100155922 | Semiconductor Device and Method of Forming Recessed Conductive Vias in Saw Streets - A semiconductor die has an insulating material disposed in a peripheral region around the die. A blind via is formed through the gap. A conductive material is deposited in the blind via to form a conductive via. A conductive layer is formed between the conductive via and contact pad on the semiconductor die. A protective layer is formed over the front side of the semiconductor die. A portion of the insulating material and conductive via is removed from a backside of the semiconductor die opposite the front side of the semiconductor die so that a thickness of the conductive via is less than a thickness of the semiconductor wafer. The insulating material and conductive via are tapered. The wafer is singulated through the gap to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically interconnected through the conductive vias. | 06-24-2010 |
20100155926 | INTEGRATED CIRCUIT PACKAGING SYSTEM FOR FINE PITCH SUBSTRATES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a substrate including: patterning a bonding pad on the substrate, patterning a first signal trace coupled to the bonding pad, patterning a second signal trace on the substrate, and connecting a pedestal on the second signal trace; mounting an integrated circuit on the substrate; and coupling an electrical interconnect between the integrated circuit, the bonding pad, the pedestal, or a combination thereof. | 06-24-2010 |
20100193926 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKED DIE - An integrated circuit package system provides a leadframe having a short lead finger and a long lead finger, and the long lead finger and the short lead finger reside substantially within the same horizontal plane. A first die is placed in the leadframe. A second die is offset from the first die. The offset second die is attached over the first die and the long lead finger with an adhesive. The first die is electrically connected to the short lead finger. The second die is electrically connected to at least the long lead finger or the short lead finger. At least portions of the leadframe, the first die, and the second die are encapsulated in an encapsulant. | 08-05-2010 |
20100193931 | Package-on-Package Using Through-Hole Via Die on Saw Streets - A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure. An encapsulant is formed over a portion of the first die and the first semiconductor package. | 08-05-2010 |
20100213618 | Semiconductor Device and Method of Forming Through Vias with Reflowed Conductive Material - A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die. | 08-26-2010 |
20100216281 | Semiconductor Device and Method of Forming Through Vias with Reflowed Conductive Material - A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die. | 08-26-2010 |
20100225007 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED DIE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a flip chip die, having a backside protrusion; mounting a wire bond die on the flip chip die, adjacent to the backside protrusion; and mounting an internal stacking module over the backside protrusion and the wire bond die. | 09-09-2010 |
20100230822 | Semiconductor Die and Method of Forming Noise Absorbing Regions Between THVS in Peripheral Region of the Die - A semiconductor wafer has a plurality of semiconductor die. A peripheral region is formed around the die. An insulating material is formed in the peripheral region. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. A conductive layer is formed between the conductive THV and contact pads of the semiconductor die. A noise absorbing material is deposited in the peripheral region between the conductive THV to isolate the semiconductor die from intra-device interference. The noise absorbing material extends through the peripheral region from a first side of the semiconductor die to a second side of the semiconductor die. The noise absorbing material has an angular, semi-circular, or rectangular shape. The noise absorbing material can be dispersed in the peripheral region between the conductive THV. | 09-16-2010 |
20100233852 | Semiconductor Device and Method of Stacking Same Size Semiconductor Die Electrically Connected Through Conductive Via Formed Around Periphery of the Die - A semiconductor device has a plurality of similar sized semiconductor die each with a plurality of bond pads formed over a surface of the semiconductor die. An insulating layer is formed around a periphery of each semiconductor die. A plurality of conductive THVs is formed through the insulating layer. A plurality of conductive traces is formed over the surface of the semiconductor die electrically connected between the bond pads and conductive THVs. The semiconductor die are stacked to electrically connect the conductive THVs between adjacent semiconductor die. The stacked semiconductor die are mounted within an integrated cavity of a substrate or leadframe structure. An encapsulant is deposited over the substrate or leadframe structure and the semiconductor die. A thermally conductive lid is formed over a surface of the substrate or leadframe structure. The stacked semiconductor die are attached to the thermally conductive lid. | 09-16-2010 |
20100237471 | Semiconductor Die and Method of Forming Through Organic Vias Having Varying Width in Peripheral Region of the Die - A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating material of the peripheral region to a first depth. A second opening is formed in the insulating material of the peripheral region centered over the first opening to a second depth less than the first depth. The first and second openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first opening and a second width in a vertical region of the second opening. The second width is different than the first width. A conductive material is deposited in the composite TOV to form a conductive TOV. An organic solderability preservative (OSP) coating is formed over a contact surface of the conductive TOV. | 09-23-2010 |
20100237477 | Semiconductor Device and Method of Mounting Pre-Fabricated Shielding Frame over Semiconductor Die - A semiconductor device includes a pre-fabricated shielding frame mounted over a sacrificial substrate and semiconductor die. An encapsulant is deposited through an opening in the shielding frame around the semiconductor die. A first portion of the shielding frame to expose the encapsulant. Removing the first portion also leaves a second portion of the shielding frame over the semiconductor die as shielding from interference. A third portion of the shielding frame around the semiconductor die provides a conductive pillar. A first interconnect structure is formed over a first side of the encapsulant, shielding frame, and semiconductor die. The sacrificial substrate is removed. A second interconnect structure over the semiconductor die and a second side of the encapsulant. The shielding frame can be connected to low-impedance ground point through the interconnect structures or TSV in the semiconductor die to isolate the die from EMI and RFI, and other inter-device interference. | 09-23-2010 |
20100237495 | Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core - A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar. | 09-23-2010 |
20100244024 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an interposer having device contacts, interconnect contacts, and test pads including the interconnect contacts along an interconnect perimeter region of the interposer, the device contacts at a device perimeter region of the interposer with the device perimeter region within the interior of the interconnect perimeter region, and the test pads at a test perimeter region of the interposer with the test perimeter region encompassing the device perimeter region; and mounting an integrated circuit over the device contacts. | 09-30-2010 |
20100244208 | Semiconductor Device and Method of Forming a Shielding Layer Between Stacked Semiconductor Die - A semiconductor device has a first semiconductor die with a shielding layer formed over its back surface. The first semiconductor die is mounted to a carrier. A first insulating layer is formed over the shielding layer. A second semiconductor die is mounted over the first semiconductor die separated by the shielding layer and first insulating layer. A second insulating layer is deposited over the first and second semiconductor die. A first interconnect structure is formed over the second semiconductor die and second insulating layer. A second interconnect structure is formed over the first semiconductor die and second insulating layer. The shielding layer is electrically connected to a low-impedance ground point through a bond wire, RDL, or TSV. The second semiconductor die may also have a shielding layer formed on its back surface. The semiconductor die are bonded through the metal-to-metal shielding layers. | 09-30-2010 |
20100244219 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming an encapsulation surrounding an integrated circuit having an inactive side and an active side exposed; forming a hole through the encapsulation with the hole not exposing the integrated circuit; forming a through conductor in the hole; and mounting a substrate with the integrated circuit surrounded by the encapsulation with the active side facing the substrate. | 09-30-2010 |
20100244232 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH Z-INTERCONNECTS HAVING TRACES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a carrier; mounting an integrated circuit on the carrier; mounting a z-interconnect on the carrier, the z-interconnect for supporting a trace cantilevered over the integrated circuit; encapsulating the integrated circuit with an encapsulation; removing the carrier; and depositing a substrate below the integrated circuit. | 09-30-2010 |
20100270656 | Semiconductor Device and Method of Forming Conductive Pillars in Recessed Region of Peripheral Area Around the Device for Electrical Interconnection to Other Devices - A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A first insulating layer is formed over the die. A recessed region with angled sidewall is formed in the peripheral area. A first conductive layer is formed over the first insulating layer outside the recessed region and further into the recessed region. A conductive pillar is formed over the first conductive layer within the recessed region. A second insulating layer is formed over the first insulating layer, conductive pillar, and first conductive layer such that the conductive pillar is exposed from the second insulating layer. A dicing channel partially through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the conductive pillar. | 10-28-2010 |
20100270661 | Semiconductor Device Having Electrical Devices Mounted to IPD Structure and Method of Shielding Electromagnetic Interference - A semiconductor device has an IPD structure formed over a substrate. First and second electrical devices are mounted to a first surface of the IPD structure. An encapsulant is deposited over the first and second electrical devices and IPD structure. A shielding layer is formed over the encapsulant and electrically connected to a conductive channel in the IPD structure. The conductive channel is connected to ground potential to isolate the first and second electrical devices from external interference. A recess can be formed in the encapsulant material between the first and second electrical devices. The shielding layer extends into the recess. An interconnect structure is formed on a second surface of the IPD structure. The interconnect structure is electrically connected to the first and second electrical devices and IPD structure. A shielding cage can be formed over the first electrical device prior to depositing encapsulant. | 10-28-2010 |
20100317153 | Semiconductor Device and Method of Forming Conductive Vias with Trench in Saw Street - A semiconductor wafer has a plurality of semiconductor die separated by a peripheral region. A trench is formed in the peripheral region of the wafer. A via is formed the die. The trench extends to and is continuous with the via. A first conductive layer is deposited in the trench and via to form conductive TSV. The first conductive layer is conformally applied or completely fills the trench and via. The trench has a larger area than the vias which accelerates formation of the first conductive layer. A second conductive layer is deposited over a front surface of the die. The second conductive layer is electrically connected to the first conductive layer. The first and second conductive layers can be formed simultaneously. A portion of a back surface of the wafer is removed to expose the first conductive layer. The die can be stacked and electrically interconnected through the TSVs. | 12-16-2010 |
20100320582 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INWARD AND OUTWARD INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base circuit assembly having an integrated circuit device; mounting a pre-formed conductive frame having an outer interconnect and an inner interconnect shorter than the outer interconnect over the base circuit assembly, the inner interconnect over the integrated circuit device and the outer interconnect around the integrated circuit device; applying an encapsulant over the inner interconnect and the outer interconnect; and removing a portion of the pre-formed conductive frame exposing an end of the inner interconnect and an end of the outer interconnect. | 12-23-2010 |
20100320601 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THROUGH VIA DIE HAVING PEDESTAL AND RECESS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a structure having a via filled with conductive material completely through the structure, a recess, and a pedestal portion bordering the recess; mounting a semiconductor device inside the recess in the structure; and encapsulating the structure and the semiconductor device in an encapsulation. | 12-23-2010 |
20110014746 | Semiconductor Device and Method of Forming Conductive TSV in Peripheral Region of Die Prior to Wafer Singulaton - A semiconductor device is made by providing a semiconductor wafer having semiconductor die separated by a peripheral region. An opening is formed in the peripheral region having a depth less than a thickness of the wafer. A conductive material is deposited in the opening of the peripheral region of the wafer to form a conductive via extending partially through the wafer. The wafer is singulated through the conductive via in the peripheral region to provide a plurality of semiconductor die each having the conductive via. A semiconductor die is mounted on a sacrificial carrier. An encapsulant is deposited over the carrier around the semiconductor die. A portion of the encapsulant and semiconductor die is removed to expose the conductive via. A first and second interconnect structure are formed over the encapsulant and semiconductor die. The first and second interconnect structures are electrically connected to the conductive via. | 01-20-2011 |
20110018114 | Semiconductor Device and Method of Embedding Thermally Conductive Layer in Interconnect Structure for Heat Dissipation - A semiconductor device is made by forming a first thermally conductive layer over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer. | 01-27-2011 |
20110037152 | DROP-MOLD CONFORMABLE MATERIAL AS AN ENCAPSULATION FOR AN INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: providing an integrated circuit; mounting a lead on the periphery of the integrated circuit; connecting the integrated circuit to the lead with an interconnect; and forming a conformable material by pressing the conformable material on the integrated circuit, the lead, and the interconnect. | 02-17-2011 |
20110042798 | Semiconductor Device and Method of Stacking Die on Leadframe Electrically Connected by Conductive Pillars - A semiconductor device has a first semiconductor die mounted to a first contact pad on a leadframe or substrate with bumps. A conductive pillar is formed over a second semiconductor die. The second die is mounted over the first die by electrically connecting the conductive pillar to a second contact pad on the substrate with bumps. The second die is larger than the first die. An encapsulant is deposited over the first and second die. Alternatively, the conductive pillars are formed over the substrate around the first die. A heat sink is formed over the second die, and a thermal interface material is formed between the first and second die. An underfill material is deposited under the first semiconductor die. A shielding layer is formed between the first and second die. An interconnect structure can be formed over the second contact pad of the substrate. | 02-24-2011 |
20110068478 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming an encapsulation surrounding an integrated circuit having an inactive side and an active side exposed; forming a hole through the encapsulation with the hole not exposing the integrated circuit; forming a through conductor in the hole; and mounting a substrate with the integrated circuit surrounded by the encapsulation with the active side facing the substrate. | 03-24-2011 |
20110108969 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a die paddle, having paddle projections along a paddle peripheral side; forming a lead terminal having a lead extension with the lead extension extending towards the paddle peripheral side and between the paddle projections; mounting an integrated circuit over the die paddle; connecting the integrated circuit and the lead extension; and forming an encapsulation over the die paddle and covering the integrated circuit and lead extension. | 05-12-2011 |
20110111591 | Semiconductor Wafer Having Through-Hole Vias on Saw Streets With Backside Redistribution Layer - A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. The metal vias are surrounded by organic material. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. The RDL and THV provide expanded interconnect flexibility to adjacent die. Repassivation layers are formed between the RDL on the second surface of the die for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The RDL provide electrical interconnect to the adjacent die. Bond wires and solder bumps also provide electrical connection to the semiconductor die. | 05-12-2011 |
20110121295 | Structure for Bumped Wafer Test - A semiconductor device includes a substrate having a first conductive layer disposed on a top surface of the substrate. A first insulation layer is formed over the substrate and contacts a sidewall of the first conductive layer. A second conductive layer is formed over the first insulation layer. The second conductive layer includes a first portion disposed over the first conductive layer and a second portion that extends beyond an end of the first conductive layer. A second insulation layer is formed over the second conductive layer. A first opening in the second insulation layer exposes the first portion of the second conductive layer. A second opening in the second insulation layer away from the first opening exposes the second portion of the second conductive layer. The second insulation layer is maintained around the first opening. A conductive bump is formed over the first portion of the second conductive layer. | 05-26-2011 |
20110121466 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WARP-FREE CHIP - An integrated circuit package system includes: a semiconductor chip; a stress-relieving layer on the semiconductor chip; an adhesion layer on the stress relieving layer; and electrical interconnects bonded to the adhesion layer. | 05-26-2011 |
20110124156 | Method of Fabricating Semiconductor Die with Through-Hole Via on Saw Streets and Through-Hole Via in Active Area of Die - A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. Metal vias are also formed through the contact pads on the active area of the die. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. Repassivation layers are formed between the RDL for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The vias through the saw streets and vias through the active area of the die, as well as the RDL, provide electrical interconnect to the adjacent die. | 05-26-2011 |
20110133316 | INTEGRATED CIRCUIT PACKAGE SYSTEM FOR ELECTROMAGNETIC ISOLATION AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: providing a lead frame; forming an integrated circuit package including the lead frame; providing a selectively exposed area on the lead frame; and coating a conductive shielding layer on the integrated circuit package for coupling the selectively exposed area. | 06-09-2011 |
20110140258 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system including: fabricating a base package substrate having component pads and stacking pads; coupling a base integrated circuit die to the component pads; forming a penetrable encapsulation material for enclosing the base integrated circuit die and the component pads on the base package substrate; and coupling stacked interconnects on the stacking pads adjacent to and not contacting the penetrable encapsulation material. | 06-16-2011 |
20110156275 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING PLANAR INTERCONNECT AND METHOD FOR MANUFACTURE THEREOF - A method for manufacture of an integrated circuit packaging system includes: mounting an integrated circuit, having a planar interconnect, over a carrier with the planar interconnect at a non-active side of the integrated circuit and an active side of the integrated circuit facing the carrier; connecting the integrated circuit and the carrier; connecting the planar interconnect and the carrier; and forming an encapsulation over the integrated circuit, the carrier, and the planar interconnect. | 06-30-2011 |
20110180914 | INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH WIRE-IN-FILM ENCAPSULANT AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing a multiple encapsulation integrated circuit package-in-package system includes: dicing a top integrated circuit wafer having a bottom encapsulant thereon to form a top integrated circuit die with the bottom encapsulant; positioning internal leadfingers adjacent and connected to a bottom integrated circuit die; pressing the bottom encapsulant on to the bottom integrated circuit die; connecting the top integrated circuit die to external leadfingers adjacent the internal leadfingers; and forming a top encapsulant over the top integrated circuit die. | 07-28-2011 |
20110187005 | Semiconductor Device and Method of Forming Cavity Adjacent to Sensitive Region of Semiconductor Die Using Wafer-Level Underfill Material - A semiconductor wafer has a plurality of first semiconductor die with a stress sensitive region. A masking layer or screen is disposed over the stress sensitive region. An underfill material is deposited over the wafer. The masking layer or screen prevents formation of the underfill material adjacent to the sensitive region. The masking layer or screen is removed leaving a cavity in the underfill material adjacent to the sensitive region. The semiconductor wafer is singulated into the first die. The first die can be mounted to a build-up interconnect structure or to a second semiconductor die with the cavity separating the sensitive region and build-up interconnect structure or second die. A bond wire is formed between the first and second die and an encapsulant is deposited over the first and second die and bond wire. A conductive via can be formed through the first or second die. | 08-04-2011 |
20110201153 | INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit having an active side and a non-active side; forming a channel through the integrated circuit; forming an indent, having a flange and an indent side, from a peripheral region of the non-active side; and forming a conformal interconnect, having an offset segment, a sloped segment, and a flange segment, under the indent. | 08-18-2011 |
20110254173 | Semiconductor Device and Method of Forming Conductive Vias with Trench in Saw Street - A semiconductor wafer has a plurality of semiconductor die separated by a peripheral region. A trench is formed in the peripheral region of the wafer. A via is formed on the die. The trench extends to and is continuous with the via. A first conductive layer is deposited in the trench and via to form conductive TSV. The first conductive layer is conformally applied or completely fills the trench and via. The trench has a larger area than the vias which accelerates formation of the first conductive layer. A second conductive layer is deposited over a front surface of the die. The second conductive layer is electrically connected to the first conductive layer. The first and second conductive layers can be formed simultaneously. A portion of a back surface of the wafer is removed to expose the first conductive layer. The die can be stacked and electrically interconnected through the TSVs. | 10-20-2011 |
20110256664 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOUNTABLE INWARD AND OUTWARD INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base circuit assembly having an integrated circuit device; mounting a pre-formed conductive frame having an outer interconnect and an inner interconnect over the base circuit assembly, the inner interconnect on the integrated circuit device and the outer interconnect around the integrated circuit device; applying an encapsulant over the inner interconnect and the outer interconnect; and removing a portion of the pre-formed conductive frame exposing an end of the inner interconnect and the outer interconnect. | 10-20-2011 |
20110266652 | Semiconductor Package with Penetrable Encapsulant Joining Semiconductor Die and Method Thereof - A semiconductor device includes a first substrate. A first semiconductor die is mounted to the first substrate. A bond wire electrically connects the first semiconductor die to the first substrate. A first encapsulant is deposited over the first semiconductor die, bond wire, and first substrate. The first encapsulant includes a penetrable, thermally conductive material. In one embodiment, the first encapsulant includes a viscous gel. A second substrate is mounted over a first surface of the first substrate. A second semiconductor die is mounted to the second substrate. The second semiconductor die is electrically connected to the first substrate. The first substrate is electrically connected to the second substrate. A second encapsulant is deposited over the first semiconductor die and second semiconductor die. An interconnect structure is formed on a second surface of the first substrate, opposite the first surface of the first substrate. | 11-03-2011 |
20110278741 | Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant - A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die. | 11-17-2011 |
20110284998 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKED DIE - An integrated circuit package system provides a leadframe having a short lead finger and a long lead finger, and the long lead finger and the short lead finger reside substantially within the same horizontal plane. A first die is placed in the leadframe. A second die is offset from the first die. The offset second die is attached over the first die and the long lead finger with an adhesive. The first die is electrically connected to the short lead finger. The second die is electrically connected to at least the long lead finger or the short lead finger. At least portions of the leadframe, the first die, and the second die are encapsulated in an encapsulant. | 11-24-2011 |
20110285002 | LEADLESS PACKAGE SYSTEM HAVING EXTERNAL CONTACTS - A leadless package system includes: an integrated circuit die having contact pads; external contact terminals with a conductive layer and an external coating layer; connections between contact pads in the integrated circuit die and the external contact terminals; and an encapsulant encapsulates the integrated circuit die and the external contact terminals including the external coating layer. | 11-24-2011 |
20110298108 | NON-LEADED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE GROUND SITES - A non-leaded integrated circuit package system includes: a die paddle of a lead frame; a dual row of terminals including an outer terminal and an inner terminal; and an inner terminal and an adjacent inner terminal to form a fused lead. | 12-08-2011 |
20110298120 | Apparatus for Thermally Enhanced Semiconductor Package - A semiconductor package includes a semiconductor die having contact pads. An encapsulant is disposed around the semiconductor die, and conductive vias are disposed in the encapsulant. Electrically conductive traces are disposed between the contact pads and conductive vias, a thermally conductive channel is disposed in the encapsulant separate from the conductive vias, and a thermally conductive layer is disposed over an area of heat generation of the semiconductor die. A thermally conductive trace is disposed between the thermally conductive layer and thermally conductive channel. The thermally conductive layer, thermally conductive trace, and thermally conductive channel are electrically isolated from the contact pads of the semiconductor die and the electrically conductive traces. The semiconductor package further comprises broad thermal traces disposed over the encapsulant, and a thermally conductive material interconnecting the broad thermal traces and the thermally conductive layer. | 12-08-2011 |
20110316133 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE STAND-OFF AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes: providing a penetrable layer; partially immersing leads in the penetrable layer; coupling an integrated circuit die to the leads; molding a package body on the integrated circuit die, the leads, and the penetrable layer; and exposing stand-off leads from the leads by removing the penetrable layer including establishing a stand-off height between a bottom of the package body and the bottom of the stand-off leads. | 12-29-2011 |
20110316163 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device; forming package interconnects adjacent the integrated circuit device, the package interconnects having an internal interconnect side with a lock structure; applying an encapsulation over the integrated circuit device and the package interconnects, the lock structure conformally filled with the encapsulation; and forming a base cavity with sides formed by the encapsulation and an external interconnect side of each of an adjacent pair of package interconnects facing one another, the base cavity having a cross-sectional length at least two times a cross-sectional width. | 12-29-2011 |
20120018866 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISLAND TERMINALS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having an upper hole below a paddle top side, the upper hole bounded by an upper non-horizontal side with a curve surface; forming a terminal adjacent the package paddle; mounting an integrated circuit on the paddle top side; and forming an encapsulation within the upper hole. | 01-26-2012 |
20120018899 | Semiconductor Device and Method of Conforming Conductive Vias Between Insulating Layers in Saw Streets - A semiconductor device is made by disposing a plurality of semiconductor die on a carrier and creating a gap between each of the semiconductor die. A first insulating material is deposited in the gap. A portion of the first insulating material is removed. A conductive layer is formed over the semiconductor die. A conductive lining is conformally formed on the remaining portion of the first insulating material to form conductive via within the gap. The conductive vias can be tapered or vertical. The conductive via is electrically connected to a contact pad on the semiconductor die. A second insulating material is deposited in the gap over the conductive lining. A portion of the conductive via may extend outside the first and second insulating materials. The semiconductor die are singulated through the gap. The semiconductor die can be stacked and interconnected through the conductive vias. | 01-26-2012 |
20120018900 | Semiconductor Device and Method of Conforming Conductive Vias Between Insulating Layers in Saw Streets - A semiconductor device is made by disposing a plurality of semiconductor die on a carrier and creating a gap between each of the semiconductor die. A first insulating material is deposited in the gap. A portion of the first insulating material is removed. A conductive layer is formed over the semiconductor die. A conductive lining is conformally formed on the remaining portion of the first insulating material to form conductive via within the gap. The conductive vias can be tapered or vertical. The conductive via is electrically connected to a contact pad on the semiconductor die. A second insulating material is deposited in the gap over the conductive lining. A portion of the conductive via may extend outside the first and second insulating materials. The semiconductor die are singulated through the gap. The semiconductor die can be stacked and interconnected through the conductive vias. | 01-26-2012 |
20120032315 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DIE PADDLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having a single integral structure with a paddle central portion surrounded by a paddle peripheral portion; forming a terminal adjacent the package paddle; mounting an integrated circuit over the paddle central portion; and forming an encapsulation over the integrated circuit and the terminal, the encapsulation free of delamination with the encapsulation directly on the paddle peripheral portion. | 02-09-2012 |
20120034777 | Through Hole Vias at Saw Streets Including Protrusions or Recesses for Interconnection - A semiconductor package includes a semiconductor wafer having a plurality of semiconductor die. A contact pad is formed over and electrically connected to an active surface of the semiconductor die. A gap is formed between the semiconductor die. An insulating material is deposited in the gap between the semiconductor die. An adhesive layer is formed over a surface of the semiconductor die and the insulating material. A via is formed in the insulating material and the adhesive layer. A conductive material is deposited in the via to form a through hole via (THV). A conductive layer is formed over the contact pad and the THV to electrically connect the contact pad and the THV. The plurality of semiconductor die is singulated. The insulating material can include an organic material. The active surface of the semiconductor die can include an optical device. | 02-09-2012 |
20120038047 | Semiconductor Device and Method of Forming B-Stage Conductive Polymer Over Contact Pads of Semiconductor Die in FO-WLCSP - A semiconductor wafer contains a plurality of semiconductor die with bumps formed over contact pads on an active surface of the semiconductor die. A b-stage conductive polymer is deposited over the contact pads on the semiconductor wafer. The semiconductor wafer is singulated to separate the die. An insulating layer is formed over a carrier with openings formed in the insulating layer. The die is mounted to the carrier with the conductive polymer disposed in the openings of the insulating layer. The conductive polymer is heated to a glass transition temperature to liquefy the conductive polymer to an electrically conductive state. An encapsulant is deposited over the die and insulating layer. The carrier is removed to expose the conductive polymer. An interconnect structure is formed over the die, encapsulant, and conductive polymer. The interconnect structure is electrically connected through the conductive polymer to the contact pads on the die. | 02-16-2012 |
20120061855 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a substrate bottom side and a substrate top side opposite the substrate bottom side; mounting an integrated circuit over the package substrate, the integrated circuit having an inactive side and an active side opposite the inactive side; connecting stack connectors to the substrate top side; applying a multi-layer film over the substrate top side, the integrated circuit, and the stack connectors, the multi-layer film having a base film layer, a penetrable film layer, and a penetrable adhesive; removing the base film layer and the penetrable film layer to expose the penetrable adhesive and exposed portions of the stack connectors; and forming an adhesive film layer by hardening the penetrable adhesive. | 03-15-2012 |
20120068313 | Semiconductor device and method of forming conductive TSV with insulating annular ring - A semiconductor wafer has an insulating layer formed over an active surface of the wafer. A conductive layer is formed over the insulating layer. A first via is formed from a back surface of the semiconductor wafer through the semiconductor wafer and insulating layer to the conductive layer. A conductive material is deposited in the first via to form a conductive TSV. An insulating material can be deposited in the first via to form an insulating core within the conductive via. After forming the conductive TSV, a second via is formed around the conductive TSV from the back surface of the semiconductor wafer through the semiconductor wafer and insulating layer to the conductive layer. An insulating material is deposited in the second via to form an insulating annular ring. The conductive via can be recessed within or extend above a surface of the semiconductor die. | 03-22-2012 |
20120074547 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent the package paddle, the lead having a hole in a lead body top side and a lead ridge protruding from a lead non-horizontal side; mounting an integrated circuit over the package paddle; connecting an electrical connector to the lead and the integrated circuit; and forming a fill layer within the hole. | 03-29-2012 |
20120091567 | Semiconductor Die and Method of Forming Noise Absorbing Regions Between THVs in Peripheral Region of the Die - A semiconductor wafer has a plurality of semiconductor die. A peripheral region is formed around the die. An insulating material is formed in the peripheral region. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. A conductive layer is formed between the conductive THV and contact pads of the semiconductor die. A noise absorbing material is deposited in the peripheral region between the conductive THV to isolate the semiconductor die from intra-device interference. The noise absorbing material extends through the peripheral region from a first side of the semiconductor die to a second side of the semiconductor die. The noise absorbing material has an angular, semi-circular, or rectangular shape. The noise absorbing material can be dispersed in the peripheral region between the conductive THV. | 04-19-2012 |
20120094444 | Semiconductor Package Having Semiconductor Die with Internal Vertical Interconnect Structure and Method Therefor - A semiconductor wafer is made by forming a first conductive layer over a sacrificial substrate, mounting a semiconductor die to the sacrificial substrate, depositing an insulating layer over the semiconductor die and first conductive layer, exposing the first conductive layer and contact pad on the semiconductor die, forming a second conductive layer over the insulating layer between the first conductive layer and contact pad, forming solder bumps on the second conductive layer, depositing an encapsulant over the semiconductor die, first conductive layer, and interconnect structure, and removing the sacrificial substrate after forming the encapsulant to expose the conductive layer and semiconductor die. A portion of the encapsulant is removed to expose a portion of the solder bumps. The solder bumps are sized so that each extends the same outside the encapsulant. The semiconductor die are stacked by electrically connecting the solder bumps. | 04-19-2012 |
20120104562 | Semiconductor Device and Method of Forming Stepped Interconnect Layer for Stacked Semiconductor Die - A semiconductor die has a first semiconductor die mounted to a carrier. A plurality of conductive pillars is formed over the carrier around the first die. An encapsulant is deposited over the first die and conductive pillars. A first stepped interconnect layer is formed over a first surface of the encapsulant and first die. The first stepped interconnect layer has a first opening. A second stepped interconnect layer is formed over the first stepped interconnect layer. The second stepped interconnect layer has a second opening. The carrier is removed. A build-up interconnect structure is formed over a second surface of the encapsulant and first die. A second semiconductor die over the first semiconductor die and partially within the first opening. A third semiconductor die is mounted over the second die and partially within the second opening. A fourth semiconductor die is mounted over the second stepped interconnect layer. | 05-03-2012 |
20120104573 | Semiconductor Device and Method of Shielding Semiconductor Die from Inter-Device Interference - A plurality of stacked semiconductor wafers each contain a plurality of semiconductor die. The semiconductor die each have a conductive via formed through the die. A gap is created between the semiconductor die. A conductive material is deposited in a bottom portion of the gap. An insulating material is deposited in the gap and over the semiconductor die. A portion of the insulating material in the gap is removed to form a recess between each semiconductor die extending to the conductive material. A shielding layer is formed over the insulating material and in the recess to contact the conductive material. The shielding layer isolates the semiconductor die from inter-device interference. A substrate is formed as a build-up structure on the semiconductor die adjacent to the conductive material. The conductive material electrically connects to a ground point in the substrate. The gap is singulating to separate the semiconductor die. | 05-03-2012 |
20120104579 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK - An integrated circuit package system includes an external interconnect having a lead tip and a lead body, including a recess in the lead body including a first recess segment, having an orientation substantially parallel to the lengthwise dimension of the lead body, and a second recess segment intersecting and perpendicular to the first recess segment along a lead body top surface of the lead body, the first recess segment at a bottom portion of the second recess segment; an internal interconnect between an integrated circuit die and the external interconnect; and an encapsulation to cover the external interconnect with the recess filled. | 05-03-2012 |
20120104590 | Semiconductor Device and Method of Forming Penetrable Film Encapsulant Around Semiconductor Die and Interconnect Structure - A semiconductor device has a plurality of bumps formed over a carrier. A semiconductor die is mounted to the carrier between the bumps. A penetrable film encapsulant layer having a base layer, first adhesive layer, and second adhesive layer is placed over the semiconductor die and bumps. The penetrable film encapsulant layer is pressed over the semiconductor die and bumps to embed the semiconductor die and bumps within the first and second adhesive layers. The first adhesive layer and second adhesive layer are separated to remove the base layer and first adhesive layer and leave the second adhesive layer around the semiconductor die and bumps. The bumps are exposed from the second adhesive layer. The carrier is removed. An interconnect structure is formed over the semiconductor die and second adhesive layer. A conductive layer is formed over the second adhesive layer electrically connected to the bumps. | 05-03-2012 |
20120104599 | Semiconductor Package Having Semiconductor Die with Internal Vertical Interconnect Structure and Method Therefor - A semiconductor wafer is made by forming a first conductive layer over a sacrificial substrate, mounting a semiconductor die to the sacrificial substrate, depositing an insulating layer over the semiconductor die and first conductive layer, exposing the first conductive layer and contact pad on the semiconductor die, forming a second conductive layer over the insulating layer between the first conductive layer and contact pad, forming solder bumps on the second conductive layer, depositing an encapsulant over the semiconductor die, first conductive layer, and interconnect structure, and removing the sacrificial substrate after forming the encapsulant to expose the conductive layer and semiconductor die. A portion of the encapsulant is removed to expose a portion of the solder bumps. The solder bumps are sized so that each extends the same outside the encapsulant. The semiconductor die are stacked by electrically connecting the solder bumps. | 05-03-2012 |
20120112328 | Semiconductor Device and Method of Mounting Pre-Fabricated Shielding Frame over Semiconductor Die - A semiconductor device includes a pre-fabricated shielding frame mounted over a sacrificial substrate and semiconductor die. An encapsulant is deposited through an opening in the shielding frame around the semiconductor die. A first portion of the shielding frame to expose the encapsulant. Removing the first portion also leaves a second portion of the shielding frame over the semiconductor die as shielding from interference. A third portion of the shielding frame around the semiconductor die provides a conductive pillar. A first interconnect structure is formed over a first side of the encapsulant, shielding frame, and semiconductor die. The sacrificial substrate is removed. A second interconnect structure over the semiconductor die and a second side of the encapsulant. The shielding frame can be connected to low-impedance ground point through the interconnect structures or TSV in the semiconductor die to isolate the die from EMI and RFI, and other inter-device interference. | 05-10-2012 |
20120112355 | Semiconductor Device and Method of Forming Stepped Interconnect Layer for Stacked Semiconductor Die - A semiconductor die has a first semiconductor die mounted to a carrier. A plurality of conductive pillars is formed over the carrier around the first die. An encapsulant is deposited over the first die and conductive pillars. A first stepped interconnect layer is formed over a first surface of the encapsulant and first die. The first stepped interconnect layer has a first opening. A second stepped interconnect layer is formed over the first stepped interconnect layer. The second stepped interconnect layer has a second opening. The carrier is removed. A build-up interconnect structure is formed over a second surface of the encapsulant and first die. A second semiconductor die over the first semiconductor die and partially within the first opening. A third semiconductor die is mounted over the second die and partially within the second opening. A fourth semiconductor die is mounted over the second stepped interconnect layer. | 05-10-2012 |
20120126429 | Semiconductor Device and Method of Forming Base Substrate with Recesses for Capturing Bumped Semiconductor Die - A semiconductor device has a base substrate with recesses formed in a first surface of the base substrate. A first conductive layer is formed over the first surface and into the recesses. A second conductive layer is formed over a second surface of the base substrate. A first semiconductor die is mounted to the base substrate with bumps partially disposed within the recesses over the first conductive layer. A second semiconductor die is mounted to the first semiconductor die. Bond wires are formed between the second semiconductor die and the first conductive layer over the first surface of the base substrate. An encapsulant is deposited over the first and second semiconductor die and base substrate. A portion of the base substrate is removed from the second surface between the second conductive layer down to the recesses to form electrically isolated base leads for the bumps and bond wires. | 05-24-2012 |
20120146192 | INTEGRATED CIRCUIT MOUNTING SYSTEM WITH PADDLE INTERLOCK AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit mounting system includes: providing a die paddle with a component side having a die mount area and a recess with more than one geometric shape; applying an adhesive on the die mount area and in a portion of the recess; and mounting an integrated circuit device with an inactive side directly on the adhesive. | 06-14-2012 |
20120153472 | Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core - A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar. | 06-21-2012 |
20120175770 | Semiconductor Device and Method of Forming Conductive Pillars in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices - A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A first insulating layer is formed over the die. A recessed region with angled sidewall is formed in the peripheral area. A first conductive layer is formed over the first insulating layer outside the recessed region and further into the recessed region. A conductive pillar is formed over the first conductive layer within the recessed region. A second insulating layer is formed over the first insulating layer, conductive pillar, and first conductive layer such that the conductive pillar is exposed from the second insulating layer. A dicing channel partially through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the conductive pillar. | 07-12-2012 |
20120181673 | Semiconductor Device and Method of Stacking Die on Leadframe Electrically Connected by Conductive Pillars - A semiconductor device has a first semiconductor die mounted to a first contact pad on a leadframe or substrate with bumps. A conductive pillar is formed over a second semiconductor die. The second die is mounted over the first die by electrically connecting the conductive pillar to a second contact pad on the substrate with bumps. The second die is larger than the first die. An encapsulant is deposited over the first and second die. Alternatively, the conductive pillars are formed over the substrate around the first die. A heat sink is formed over the second die, and a thermal interface material is formed between the first and second die. An underfill material is deposited under the first semiconductor die. A shielding layer is formed between the first and second die. An interconnect structure can be formed over the second contact pad of the substrate. | 07-19-2012 |
20120181689 | Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices - A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps. | 07-19-2012 |
20120187580 | Semiconductor Device and Method of Forming B-Stage Conductive Polymer over Contact Pads of Semiconductor Die in Fo-WLCSP - A semiconductor wafer contains a plurality of semiconductor die with bumps formed over contact pads on an active surface of the semiconductor die. A b-stage conductive polymer is deposited over the contact pads on the semiconductor wafer. The semiconductor wafer is singulated to separate the die. An insulating layer is formed over a carrier with openings formed in the insulating layer. The die is mounted to the carrier with the conductive polymer disposed in the openings of the insulating layer. The conductive polymer is heated to a glass transition temperature to liquefy the conductive polymer to an electrically conductive state. An encapsulant is deposited over the die and insulating layer. The carrier is removed to expose the conductive polymer. An interconnect structure is formed over the die, encapsulant, and conductive polymer. The interconnect structure is electrically connected through the conductive polymer to the contact pads on the die. | 07-26-2012 |
20120199963 | Package-on-Package Using Through-Hole Via Die on Saw Streets - A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure. An encapsulant is formed over a portion of the first die and the first semiconductor package. | 08-09-2012 |
20120199972 | Semiconductor Device and Method of Forming Vertical Interconnect Structure Using Stud Bumps - A semiconductor device is made by forming a conductive layer over a temporary carrier. The conductive layer includes a wettable pad. A stud bump is formed over the wettable pad. The stud bump can be a stud bump or stacked bumps. A semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the stud bump. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure includes a first IPD and is electrically connected to the stud bump. The carrier is removed. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The second interconnect structure includes a second IPD. The first or second IPD includes a capacitor, resistor, or inductor. The semiconductor devices are stackable and electrically connected through the stud bump. | 08-09-2012 |
20120205811 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TERMINAL LOCKS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a cornered dimple formed therein as a simple concave polygon; mounting an integrated circuit above and coupled to the terminal; and forming an encapsulation encapsulating the integrated circuit and portions of the terminal. | 08-16-2012 |
20120217643 | Semiconductor Device and Method of Forming Bond Wires Between Semiconductor Die Contact Pads and Conductive TOV in Peripheral Area Around Semiconductor Die - A semiconductor wafer has a plurality of semiconductor die with contact pads. An organic material is deposited in a peripheral region around the semiconductor die. A portion of the organic material is removed to form a plurality of vias. A conductive material is deposited in the vias to form conductive TOV. The conductive TOV can be recessed with respect to a surface of the semiconductor die. Bond wires are formed between the contact pads and conductive TOV. The bond wires can be bridged in multiple sections across the semiconductor die between the conductive TOV and contact pads. An insulating layer is formed over the bond wires and semiconductor die. The semiconductor wafer is singulated through the conductive TOV or organic material between the conductive TOV to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically connected through the bond wires and conductive TOV. | 08-30-2012 |
20120241939 | Apparatus for Thermally Enhanced Semiconductor Package - A semiconductor package includes a semiconductor die having contact pads. An encapsulant is disposed around the semiconductor die, and conductive vias are disposed in the encapsulant. Electrically conductive traces are disposed between the contact pads and conductive vias, a thermally conductive channel is disposed in the encapsulant separate from the conductive vias, and a thermally conductive layer is disposed over an area of heat generation of the semiconductor die. A thermally conductive trace is disposed between the thermally conductive layer and thermally conductive channel. The thermally conductive layer, thermally conductive trace, and thermally conductive channel are electrically isolated from the contact pads of the semiconductor die and the electrically conductive traces. The semiconductor package further comprises broad thermal traces disposed over the encapsulant, and a thermally conductive material interconnecting the broad thermal traces and the thermally conductive layer. | 09-27-2012 |
20120241940 | Semiconductor Device and Method of Embedding Thermally Conductive Layer in Interconnect Structure for Heat Dissipation - A semiconductor device has a first thermally conductive layer formed over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer. | 09-27-2012 |
20120241973 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILLED VIAS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a via hole in the substrate, the via hole having a top end and a bottom end with the bottom end is larger than the top end; forming a pad on the substrate, the pad encloses the top end of the via hole; and reflowing a conductive filler having higher volume than the via hole over the via hole, the conductive filler having a protrusion extending from the bottom end and the bottom end entirely overlaps at least one surface of the protrusion. | 09-27-2012 |
20120244661 | Method of Fabricating Semiconductor Die with Through-Hole Via on Saw Streets and Through-Hole Via in Active Area of Die - A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. Metal vias are also formed through the contact pads on the active area of the die. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. Repassivation layers are formed between the RDL for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The vias through the saw streets and vias through the active area of the die, as well as the RDL, provide electrical interconnect to the adjacent die. | 09-27-2012 |
20120261817 | Semiconductor Device and Method of Providing Common Voltage Bus and Wire Bondable Redistribution - A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer. | 10-18-2012 |
20120273967 | Semiconductor Wafer Having Through-Hole Vias on Saw Streets with Backside Redistribution Layer - A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. The metal vias are surrounded by organic material. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. The RDL and through-hole vias (THV) provide expanded interconnect flexibility to adjacent die. Repassivation layers are formed between the RDL on the second surface of the die for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The RDL provide electrical interconnect to the adjacent die. Bond wires and solder bumps also provide electrical connection to the semiconductor die. | 11-01-2012 |
20120280376 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, a peripheral lead horizontal ridge, and a peripheral lead conductive plate, the peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a central lead adjacent to the peripheral lead; forming a first top distribution layer on the peripheral lead top side; connecting an integrated circuit to the first top distribution layer; applying an insulation layer directly on a bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge; and attaching a heatsink to the central lead under the integrated circuit. | 11-08-2012 |
20120280377 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, a peripheral lead horizontal ridge, and a peripheral lead conductive plate, the peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a first top distribution layer on the peripheral lead top side, the first top distribution layer having a first top terminal; connecting an integrated circuit to the first top distribution layer, the integrated circuit having a central portion directly over a plurality of the first top terminal; and applying an insulation layer directly on a bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge. | 11-08-2012 |
20120280390 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTED CIRCUIT LEAD ARRAY AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a top with a depression; applying a dielectric material in the depression, the dielectric material having a gap formed therein and exposing a portion of the top therefrom; forming a trace within the gap and in direct contact with the top, the trace extending laterally over an upper surface of the dielectric material; and connecting an integrated circuit to the terminal through the trace. | 11-08-2012 |
20120280402 | Semiconductor Die and Method of Forming through Organic Vias having Varying Width in Peripheral Region of the Die - A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating material of the peripheral region to a first depth. A second opening is formed in the insulating material of the peripheral region centered over the first opening to a second depth less than the first depth. The first and second openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first opening and a second width in a vertical region of the second opening. The second width is different than the first width. A conductive material is deposited in the composite TOV to form a conductive TOV. An organic solderability preservative (OSP) coating is formed over a contact surface of the conductive TOV. | 11-08-2012 |
20120280403 | Semiconductor Die and Method of Forming through Organic Vias having Varying Width in Peripheral Region of the Die - A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating material of the peripheral region to a first depth. A second opening is formed in the insulating material of the peripheral region centered over the first opening to a second depth less than the first depth. The first and second openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first opening and a second width in a vertical region of the second opening. The second width is different than the first width. A conductive material is deposited in the composite TOV to form a conductive TOV. An organic solderability preservative (OSP) coating is formed over a contact surface of the conductive TOV. | 11-08-2012 |
20120280407 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ELECTRICAL INTERFACE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion, the contact protrusion having a lower protrusion surface, an upper protrusion surface, and a protrusion sidewall; forming a die paddle, adjacent to the isolated contact, having a die paddle protrusion, the die paddle protrusion having a lower die protrusion surface, an upper die protrusion surface, and a die protrusion sidewall; depositing a contact pad on the contact protrusion; depositing a die paddle pad on the die paddle protrusion; coupling an integrated circuit die to the contact protrusion; and molding an encapsulation on the integrated circuit die. | 11-08-2012 |
20120280408 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a die paddle having an internal portion with a trench along a perimeter of the die paddle; forming an interconnect having a concave indentation and an upper portion, the upper portion, opposite the concave indentation, aligned horizontally to the internal portion; | 11-08-2012 |
20120286432 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base carrier; providing a first integrated circuit having a first integrated circuit inactive side and a first integrated circuit active side; coupling a second integrated circuit, having a second integrated circuit inactive side and a second integrated circuit active side, to the first integrated circuit in an active-to-active configuration; attaching the first integrated circuit over the base carrier; attaching a redistribution structure over the first integrated circuit; and forming a base encapsulation over the redistribution structure, the base encapsulation having a recess partially exposing the redistribution structure. | 11-15-2012 |
20120306078 | EXPOSED INTERCONNECT FOR A PACKAGE ON PACKAGE SYSTEM - An integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit above the substrate; connecting an interposer to the integrated circuit with a wire-in-film adhesive; connecting an exposed interconnect having an upper surface to the substrate; and encapsulating the integrated circuit with an encapsulation. | 12-06-2012 |
20120326284 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL EMISSION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead array having an innermost space with an innermost lead having an inner lead profile different around an inner non-horizontal side of the innermost lead; forming a middle lead having a middle lead profile the same around a lead side of the middle lead; placing an integrated circuit in the innermost space adjacent to the innermost lead; and forming a package encapsulation over the integrated circuit, the innermost lead, and the middle lead. | 12-27-2012 |
20130056867 | Semiconductor device and method of forming FO-WLCSP with recessed interconnect area in peripheralregion of semiconductor die - A semiconductor device has a temporary layer, such as a dam material or adhesive layer, formed over a carrier. A plurality of recesses is formed in the temporary layer. A first semiconductor die is mounted within the recesses of the temporary layer. An encapsulant is deposited over the first semiconductor die and temporary layer. The encapsulant extends into the recesses in the temporary layer. The carrier and temporary layer are removed to form recessed interconnect areas around the first semiconductor die. Alternatively, the recessed interconnect areas can be formed the carrier or encapsulant. Multiple steps can be formed in the recesses of the temporary layer. A conductive layer is formed over the first semiconductor die and encapsulant and into the recessed interconnect areas. A second semiconductor die can be mounted on the first semiconductor die. The semiconductor device can be integrated into PiP and Fi-PoP arrangements. | 03-07-2013 |
20130075889 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SHIELD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: mounting a device mounting structure over a bottom substrate; mounting a heat spreader having an opening formed by a single integral structure with a dam and a flange, the dam having a dam height greater than a flange height of the flange; and forming a package encapsulation over the device mounting structure and the bottom substrate with the device mounting structure exposed within the opening. | 03-28-2013 |
20130087897 | Semiconductor Device and Method of Forming a Shielding Layer Between Stacked Semiconductor Die - A semiconductor device has a first semiconductor die with a shielding layer formed over its back surface. The first semiconductor die is mounted to a carrier. A first insulating layer is formed over the shielding layer. A second semiconductor die is mounted over the first semiconductor die separated by the shielding layer and first insulating layer. A second insulating layer is deposited over the first and second semiconductor die. A first interconnect structure is formed over the second semiconductor die and second insulating layer. A second interconnect structure is formed over the first semiconductor die and second insulating layer. The shielding layer is electrically connected to a low-impedance ground point through a bond wire, RDL, or TSV. The second semiconductor die may also have a shielding layer formed on its back surface. The semiconductor die are bonded through the metal-to-metal shielding layers. | 04-11-2013 |
20130087902 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL STRUCTURES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a thermal attach cluster includes: forming a heat collector having a heat dissipation surface, forming a cluster bridge, having a thermal surface, connected to the heat collector, forming a cluster pad, having an attachment surface, connected to the end of the cluster bridge opposite the heat collector; connecting an integrated circuit to the thermal attach cluster; and forming an encapsulation over the thermal attach cluster with the heat dissipation surface, the thermal surface, and the attachment surface exposed from and coplanar with the encapsulation. | 04-11-2013 |
20130087928 | Semiconductor Device and Method of Forming Conductive TSV With Insulating Annular Ring - A semiconductor wafer has an insulating layer formed over an active surface of the wafer. A conductive layer is formed over the insulating layer. A first via is formed from a back surface of the semiconductor wafer through the semiconductor wafer and insulating layer to the conductive layer. A conductive material is deposited in the first via to form a conductive TSV. An insulating material can be deposited in the first via to form an insulating core within the conductive via. After forming the conductive TSV, a second via is formed around the conductive TSV from the back surface of the semiconductor wafer through the semiconductor wafer and insulating layer to the conductive layer. An insulating material is deposited in the second via to form an insulating annular ring. The conductive via can be recessed within or extend above a surface of the semiconductor die. | 04-11-2013 |
20130099365 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADFRAME LEAD ARRAY ROUTING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a leadframe with a grid lead and a support pad; connecting a redistribution layer to the grid lead, the redistribution layer over the support pad; mounting an integrated circuit over the redistribution layer; applying an encapsulation on the redistribution layer, the redistribution layer in an interior area of the leadframe and the interior area under the integrated circuit; forming a support pad residue on the bottom surface of the redistribution layer by removing the support pad under the encapsulation and the interior redistribution layer; and forming an insulation layer on the support pad residue and the grid lead. | 04-25-2013 |
20130099367 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PLANARITY CONTROL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a partially removed portion including: a conductive pattern having a lower surface on a top frame surface of the leadframe, a contact protrusion and a support lead on the lower surface of the conductive pattern, the support lead for supporting the partially removed portion of the leadframe during an encapsulation process, and a contact pad on a bottom surface of the contact protrusion; mounting an integrated circuit die above the conductive pattern; applying an encapsulation on the integrated circuit die and the conductive pattern, the lower surface of the conductive pattern exposed from the encapsulation; and removing at least a portion of the leadframe to form a contact lead and expose a bottom surface of the encapsulation. | 04-25-2013 |
20130154072 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, and a peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a first top distribution layer on the peripheral lead top side; connecting an integrated circuit to the first top distribution layer; and applying an insulation layer directly on a distribution layer bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge with a cavity in the portion of the insulation layer directly below the integrated circuit. | 06-20-2013 |
20130154080 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead; forming an interior conductive layer having an interior top side and an interior bottom side, the interior bottom side directly on the lead; mounting an integrated circuit over the lead, the integrated circuit having an inactive side and an active side; forming an encapsulation directly on the inactive side and the interior top side; and forming an insulation layer directly on the active side and a portion of the interior bottom side. | 06-20-2013 |
20130154105 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE TRACE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing routable traces including a first routable trace with a top plate and a second routable trace; mounting an integrated circuit partially over a second routable trace; forming an encapsulation over and around the first routable trace and the integrated circuit; forming a hole through the encapsulation to the top plate; and forming a protective coat directly on the encapsulation with the first routable trace between and in contact with the protective coat and the encapsulation. | 06-20-2013 |
20130154118 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion; forming a die paddle, adjacent to the isolated contact, having a die paddle contour; depositing a contact pad on the contact protrusion; coupling an integrated circuit die to the contact protrusion; molding an encapsulation on the integrated circuit die; and depositing an organic filler on and between the isolated contact and the die paddle, the contact protrusion extended past the organic filler. | 06-20-2013 |
20130154119 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TERMINALS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead top side; forming a lower interior conductive layer directly on the lead top side; forming an interior insulation layer directly on the lower interior conductive layer; forming an upper interior conductive layer directly on the interior insulation layer; and mounting an integrated circuit over the upper interior conductive layer. | 06-20-2013 |
20130154120 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead; forming an interior conductive layer directly on the peripheral lead; forming a vertical connector directly on the interior conductive layer, the vertical connector having a connector top side; connecting an integrated circuit to the interior conductive layer; and forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation top side coplanar with the connector top side. | 06-20-2013 |
20130214385 | Package-in-Package Using Through-Hole Via Die on Saw Streets - A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die. | 08-22-2013 |
20130241030 | Semiconductor Device and Method of Forming Base Substrate with Recesses for Capturing Bumped Semiconductor Die - A semiconductor device has a base substrate with recesses formed in a first surface of the base substrate. A first conductive layer is formed over the first surface and into the recesses. A second conductive layer is formed over a second surface of the base substrate. A first semiconductor die is mounted to the base substrate with bumps partially disposed within the recesses over the first conductive layer. A second semiconductor die is mounted to the first semiconductor die. Bond wires are formed between the second semiconductor die and the first conductive layer over the first surface of the base substrate. An encapsulant is deposited over the first and second semiconductor die and base substrate. A portion of the base substrate is removed from the second surface between the second conductive layer down to the recesses to form electrically isolated base leads for the bumps and bond wires. | 09-19-2013 |
20130249065 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND LEADFRAME ETCHING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting region; applying a mounting structure in the mounting region; mounting an integrated circuit die on the mounting structure; forming an encapsulation on the integrated circuit die and having an encapsulation cavity, the encapsulation cavity shaped by the mounting structure; forming a lead having a lead protrusion from the leadframe, the lead protrusion below a horizontal plane of the integrated circuit die; and removing the mounting structure for exposing the integrated circuit die. | 09-26-2013 |
20130249068 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXTERNAL INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a routable distribution layer on a leadframe; mounting an integrated circuit over the routable distribution layer; encapsulating with an encapsulation over the routable distribution layer; peeling the leadframe away from the routable distribution layer with a bottom distribution side of the routable distribution layer exposed from the encapsulation; and mounting an external interconnect on the routable distribution layer. | 09-26-2013 |
20130249077 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TERMINALS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting platform; applying an attach layer on the mounting platform; mounting an integrated circuit die on the attach layer; forming an encapsulation on the integrated circuit die and the attach layer, the mounting platform exposed from the encapsulation; and forming a terminal having a terminal protrusion from the leadframe, the terminal protrusion below a horizontal plane of the mounting platform. | 09-26-2013 |
20130249118 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A GRID ARRAY WITH A LEADFRAME AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a conductive trace having a terminal end and a circuit end; forming a terminal on the terminal end; connecting an integrated circuit die directly on the circuit end of the conductive trace, the integrated circuit die laterally offset from the terminal, the active side of the integrated circuit die facing the circuit end; and forming an insulation layer on the terminal and the integrated circuit die, the integrated circuit die covered by the insulation layer. | 09-26-2013 |
20130256861 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE CIRCUITRY AND METHOD OF MANUFACTURE THEREOF - An integrated circuit packaging system, and a method of manufacture therefor, including: electrical terminals; circuitry protective material around the electrical terminals and formed to have recessed pad volumes; routable circuitry on the top surface of the circuitry protective material; and an integrated circuit die electrically connected to the electrical terminals. | 10-03-2013 |
20130292850 | Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant - A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die. | 11-07-2013 |
20130299971 | Semiconductor Device and Method of Forming Penetrable Film Encapsulant Around Semiconductor Die and Interconnect Structure - A semiconductor device has a plurality of bumps formed over a carrier. A semiconductor die is mounted to the carrier between the bumps. A penetrable film encapsulant layer having a base layer, first adhesive layer, and second adhesive layer is placed over the semiconductor die and bumps. The penetrable film encapsulant layer is pressed over the semiconductor die and bumps to embed the semiconductor die and bumps within the first and second adhesive layers. The first adhesive layer and second adhesive layer are separated to remove the base layer and first adhesive layer and leave the second adhesive layer around the semiconductor die and bumps. The bumps are exposed from the second adhesive layer. The carrier is removed. An interconnect structure is formed over the semiconductor die and second adhesive layer. A conductive layer is formed over the second adhesive layer electrically connected to the bumps. | 11-14-2013 |
20130299975 | Semiconductor Device and Method of Forming Through Vias with Reflowed Conductive Material - A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die. | 11-14-2013 |
20140001627 | Semiconductor Device and Method of Embedding Thermally Conductive Layer in Interconnect Structure for Heat Dissipation | 01-02-2014 |
20140165389 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE GRID ARRAY LEAD FRAME - System and method of manufacturing an integrated circuit packaging system using routable grid array lead frame. Method includes providing a lead frame having top metal connector and bottom contact, and treating the top metal connector with an additive, or the bottom contact with an additive, or both. Concomitant to the treatment process, insulation cover or bottom encapsulation can be formed about the top metal connector or the bottom contact with respective openings. Upon coupling the interconnects to the lead frame the interconnects do not exceed the metal contacts by more than about 60% due to the treatment process. | 06-19-2014 |
20140167236 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSFERABLE TRACE LEAD FRAME - System and method of manufacturing an integrated circuit packaging system using transferable trace lead frame. A lead frame is provided having lower metal contacts. A masking layer can be formed on an upper surface of the lead frame for protection and shielding purposes. Routing layer and conductive lands may subsequently be formed by shaping the lead frame, along with bottom encapsulation. The masking layer may subsequently be removed for additional processing steps including connecting an integrated circuit die to the upper surface of the lead frame. | 06-19-2014 |
20140197540 | Extended Redistribution Layers Bumped Wafer - A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad. | 07-17-2014 |
20140197548 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED GRID-ARRAY MECHANISM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a lead-frame having a metal connector mounted thereon and having a peripheral mounting region; forming an insulation cover on the lead-frame and on the metal connector; connecting an integrated circuit die over the insulation cover; forming a top encapsulation on the integrated circuit die with the peripheral mounting region exposed from the top encapsulation; forming a routing layer, having a conductive land, from the lead-frame; and forming a bottom encapsulation partially encapsulating the routing layer and the insulation cover. | 07-17-2014 |
20140203443 | Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core - A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar. | 07-24-2014 |
20140217609 | Semiconductor Device and Method of Forming Conductive Vias with Trench in Saw Street - A semiconductor wafer has a plurality of semiconductor die separated by a peripheral region. A trench is formed in the peripheral region of the wafer. A via is formed on the die. The trench extends to and is continuous with the via. A first conductive layer is deposited in the trench and via to form conductive TSV. The first conductive layer is conformally applied or completely fills the trench and via. The trench has a larger area than the vias which accelerates formation of the first conductive layer. A second conductive layer is deposited over a front surface of the die. The second conductive layer is electrically connected to the first conductive layer. The first and second conductive layers can be formed simultaneously. A portion of a back surface of the wafer is removed to expose the first conductive layer. The die can be electrically interconnected through the TSVs. | 08-07-2014 |
20140284791 | CORELESS INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF - A system and method for manufacturing an integrated circuit packaging system includes: forming a base substrate including: providing a sacrificial carrier: mounting a metallic sheet on the sacrificial carrier, applying a top trace to the metallic sheet, forming a conductive stud on the top trace, forming a base encapsulation over the metallic sheet, the top trace, and the conductive stud, the top trace exposed from a top surface of the base encapsulation, and removing the sacrificial carrier and the metallic sheet; mounting an integrated circuit device on the base substrate; and encapsulating the integrated circuit device and the base substrate with a top encapsulation. | 09-25-2014 |
20140353846 | Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant - A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die. | 12-04-2014 |
20150084172 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SIDE SOLDERABLE LEADS AND METHOD OF MANUFACTURE THEREOF - A system and method of manufacture of an integrated circuit packaging system includes: a leadframe having a side solderable lead with a half-etched lead portion and a lead top side; a mold body directly on the leadframe and the side solderable lead, the lead top side of the side solderable lead exposed from the mold body; a mold groove in the mold body and in a portion of the side solderable lead for exposing a lead protrusion of the side solderable lead on an upper perimeter side of the mold body; and the half-etched lead portion exposed from a lower perimeter side of the mold body. | 03-26-2015 |