Stueckler
Ewald Stueckler, Unterpremstaetten AT
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20150380308 | MASKING METHOD FOR SEMICONDUCTOR DEVICES WITH HIGH SURFACE TOPOGRAPHY - The method comprises the steps of providing a semiconductor body or substrate ( | 12-31-2015 |
Franz Stueckler, Stefan AT
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20120007244 | Backside Processing of Semiconductor Devices - A semiconductor device includes a workpiece having a bottom surface opposite the top surface. Metallization layers are disposed over the top surface and a protective layer is disposed over the metallization layers. The semiconductor device further includes a metal silicide layer disposed on the bottom surface. The metal silicide layer is less than about five atomic layers in thickness. A first metal layer is disposed over the metal silicide layer such that a metal of the first metal layer is the same as a metal of the metal silicide layer. | 01-12-2012 |
20140015141 | Backside Processing of Semiconductor Devices - A semiconductor device includes a workpiece having a bottom surface opposite the top surface. Metallization layers are disposed over the top surface and a protective layer is disposed over the metallization layers. The semiconductor device further includes a metal silicide layer disposed on the bottom surface. The metal silicide layer is less than about five atomic layers in thickness. A first metal layer is disposed over the metal silicide layer such that a metal of the first metal layer is the same as a metal of the metal silicide layer. | 01-16-2014 |
Franz Stueckler, St. Stefan AT
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20120068345 | LAYER STACKS AND INTEGRATED CIRCUIT ARRANGEMENTS - In various embodiments, a layer stack is provided. The layer stack may include a carrier; a first metal disposed over the carrier; a second metal disposed over the first metal; and a solder material disposed above the second metal or a material that provides contact to a solder that is supplied by an external source. The second metal may have a melting temperature of at least 1800° C. and is not or substantially not dissolved in the solder material at least one of during a soldering process and after the soldering process. | 03-22-2012 |
20140210061 | CHIP ARRANGEMENT AND CHIP PACKAGE - Various embodiments provide a chip arrangement. The chip arrangement may include a first chip including a first contact and a second contact; a second chip; a leadframe including a first leadframe portion and a second leadframe portion electrically insulated from the first leadframe portion; and a plurality of pins coupled to the leadframe. At least one first pin is coupled to the first leadframe portion and at least one second pin is coupled to the second leadframe portion. The first contact of the first chip is electrically coupled to the first leadframe portion and the second contact of the first chip is coupled to the second leadframe portion. A contact of the second chip is electrically coupled to the second leadframe portion. | 07-31-2014 |
20150228607 | LAYER STACKS AND INTEGRATED CIRCUIT ARRANGEMENTS - In various embodiments, a layer stack is provided. The layer stack may include a carrier; a first metal disposed over the carrier; a second metal disposed over the first metal; and a solder material disposed above the second metal or a material that provides contact to a solder that is supplied by an external source. The second metal may have a melting temperature of at least 1800° C. and is not or substantially not dissolved in the solder material at least one of during a soldering process and after the soldering process. | 08-13-2015 |
Franz Stueckler, St.stefan AT
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20150270208 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device is provided. The power semiconductor device includes a leadframe, which includes a first chip carrier part and at least one second chip carrier part, which are fitted at a distance from one another and are in each case electrically conductive, at least one first power semiconductor component applied on the first chip carrier part, at least one second power semiconductor component applied on the second chip carrier part, external contacts in the form of external leads, and a capacitor. The capacitor is mounted on two adjacent external leads. | 09-24-2015 |
Gerd Stueckler, Tegernsee DE
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20090303335 | Method of Spatial Frequency Filtering and Image Capture Device - The present invention relates to a method of spatial frequency filtering in an image capture device ( | 12-10-2009 |
Thomas Stueckler, Wimpassing AT
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20150314395 | METHOD FOR PRODUCING AN ENDLESS BELT - The invention relates to a method of producing an endless belt ( | 11-05-2015 |