Patent application number | Description | Published |
20090313503 | SYSTEMS AND METHODS OF EVENT DRIVEN RECOVERY MANAGEMENT - Systems and methods of event driven recovery management are disclosed. In one embodiment, a method of providing event driven recovery management includes continually copying one or more data blocks that are generated from a computing device, associating at least one event marker with the copies of the one or more data blocks, and allowing access to the copies of the one or more data blocks according to the at least one event marker in order to provide event driven recovery. For purposes of this disclosure, an event marker, a book mark, an application consistency point, and/or a business event are interchangeably used, depending on the context. | 12-17-2009 |
20100169282 | ACQUISITION AND WRITE VALIDATION OF DATA OF A NETWORKED HOST NODE TO PERFORM SECONDARY STORAGE - Methods and a system to acquire and perform write validation of data generated by one or more networked host nodes to perform secondary storage are disclosed. According to one embodiment, a method to passively acquire and perform write validation of data generated by one or more networked host nodes to perform secondary storage in a SAN-based data storage and recovery network includes generating data to store in primary storage. The method further includes generating metadata describing the data generated to store in primary storage, sending the data and metadata to a primary SAN storage device, acquiring passive access to data traveling a data path between a generating node and the primary SAN storage device, the data mirrored over an access line to a secondary storage server. The method further includes receiving, at the secondary storage server, an exact copy of a data stream that passes a splitter. | 07-01-2010 |
20100169452 | CAUSATION OF A DATA READ OPERATION AGAINST A FIRST STORAGE SYSTEM BY A SERVER ASSOCIATED WITH A SECOND STORAGE SYSTEM ACCORDING TO A HOST GENERATED INSTRUCTION - Methods and systems of causation of a data read operation against a first storage system by a server associated with a second storage system according to a host generated instruction are disclosed. In an embodiment, a method of causing a data read operation against a first storage system, the data read operation performed by a server associated with a second storage system according to a machine-readable instruction generated by a host directly associated with the first storage system. The method further includes saving data from the host to the first storage system, creating a record of at least one data write comprising the data saved to the first storage system, and using a variable contained in the record to process a mapping scheme resulting in knowledge of at least one physical offset in the first storage system to receive the at least one data write. | 07-01-2010 |
20100169466 | CONFIGURING HOSTS OF A SECONDARY DATA STORAGE AND RECOVERY SYSTEM - A software suite, a method and a system of configuring hosts of a secondary data storage and recovery system are disclosed. In an embodiment, a system includes hosts saving data in primary storage devices, a software suite to provide secondary storage and a recovery service to one or more networked node includes a portion to configure at least one network node to perform a service, a portion to order a service and to generate metadata about data generated to store in secondary storage using a processor and a non-volatile memory, and a portion to perform data write validation and a portion to receive and prepare data to store in secondary storage. The portion to perform service configuration, the portion to perform ordering, and the portion to perform metadata generation are part of a client instance may be provided one instance per to the one or more networked node. | 07-01-2010 |
20100169587 | CAUSATION OF A DATA READ AGAINST A FIRST STORAGE SYSTEM TO OPTIONALLY STORE A DATA WRITE TO PRESERVE THE VERSION TO ALLOW VIEWING AND RECOVERY - Machine readable instructions, methods, and systems of causation of a data read against a first storage system to optionally store a data write to preserve the version to allow viewing and recovery are disclosed. In an embodiment, a system for providing secondary data storage and recovery services for one or more networked host nodes includes a server application for facilitating data backup and recovery services; a first data storage medium accessible to the server application; a second data storage medium accessible to the server application; and at least one client application for mapping write locations allocated by the first data storage medium to write locations represented in a logical view of the first data storage medium. | 07-01-2010 |
20100169591 | TIME ORDERED VIEW OF BACKUP DATA ON BEHALF OF A HOST - A method and systems of a time ordered view of backup data on behalf of a host are disclosed. In an embodiment, a method to provide a time-ordered snapshot view on behalf of a host of a specified portion of a backup of a first storage system data container stored at a second storage system includes initiating an order at the host to obtain a view of a data container. The order specifies a date and time of the ordered view. The method further includes receiving the order at a server adapted to assemble and enable access to the ordered view, and at the server, accessing the second storage system according to the date and time of the ordered view and accessing an applicable data write representing a data change to the data container. | 07-01-2010 |
20150074458 | Systems and Methods of Event Driven Recovery Management - Systems and methods of event driven recovery management are disclosed. In one embodiment, a method of providing event driven recovery management includes continually copying one or more data blocks that are generated from a computing device, associating at least one event marker with the copies of the one or more data blocks, and allowing access to the copies of the one or more data blocks according to the at least one event marker in order to provide event driven recovery. For purposes of this disclosure, an event marker, a book mark, an application consistency point, and/or a business event are interchangeably used, depending on the context. | 03-12-2015 |
Patent application number | Description | Published |
20090184668 | HIGH EFFICIENCY BOOST LED DRIVER WITH OUTPUT - A current driver for powering a string of LEDs has a boost converter coupled to an input voltage source. A voltage multiplier circuit is coupled to the boost converter and to the string of LEDs. A latch is provided having an output coupled to the boost converter. A current sense element is coupled to the boost converter. A current comparator is provided having an output coupled to a first input of the latch, a first input coupled to the current sense element, and a second input coupled to a reference current. A zero-volt detector circuit is provided having an output coupled to a second input of the latch and an input coupled to the boost converter and the voltage multiplier circuit. | 07-23-2009 |
20090302774 | CONTROL CIRCUIT AND METHOD FOR REGULATING AVERAGE INDUCTOR CURRENT IN A SWITCHING CONVERTER - A switching power converter has an input voltage source. An output load is coupled to the input voltage source. An inductive element is coupled to the load. A switch is coupled to the inductive element. A current reference input is provided. A control circuit is coupled to the switch and the current reference input for activating and deactivating the switch. The inductive element receives power from the input voltage source when the switch is activated and conducting continuous current. The control circuit deactivates the switch after a controlled delay time when the current in the inductive element and the switch exceeds the current reference input so that an average current in the inductive element is determined by a magnitude of the current reference input. | 12-10-2009 |
20100118572 | LED DRIVER WITH LOW HARMONIC DISTORTION OF INPUT AC CURRENT AND METHODS OF CONTROLLING THE SAME - A power supply circuit for powering a load at constant current has a rectifier stage for receiving an AC voltage input and for producing a first substantially DC voltage. A first capacitor is attached to the load. A charge-pump is attached to an output of the rectifier stage and to the load for providing power factor correction and for converting the first substantially DC voltage to a second substantially DC voltage at the first capacitor. The charge pump is prevented from conducting energy back into the output of the rectifier stage. The charge pump delivers energy to a charge pump output, the energy being delivered directly instead of being stored. A converter stage is attached to the load and the first capacitor. The converter stage is used for converting voltages at the first capacitor and the charge pump to an output DC current. The converter stage has a switch for periodically connecting a first series-coupled circuit of the charge pump to the output of the rectifier stage. | 05-13-2010 |
20100259177 | LED DRIVER WITH EXTENDED DIMMING RANGE AND METHOD FOR ACHIEVING THE SAME - A circuit for powering of a Light Emitting Diode (LED) string has a switching power converter. A brightness control circuit is coupled to the switching power converter to allow a duration of a conductive state of the power converter to exceed a duration of a conductive state of the LED string for maintaining a current magnitude in the LED string constant. | 10-14-2010 |
20140210360 | LED DRIVER WITH EXTENDED DIMMING RANGE AND METHOD FOR ACHIEVING THE SAME - A circuit for powering of a Light Emitting Diode (LED) string has a switching power converter. A brightness control circuit is coupled to the switching power converter to allow a duration of a conductive state of the power converter to exceed a duration of a conductive state of the LED string for maintaining a current magnitude in the LED string constant. | 07-31-2014 |
Patent application number | Description | Published |
20110093830 | Integrated Circuit Optimization Modeling Technology - A design optimization method for a target circuit design specified by a machine-readable file, comprises providing a computer-implemented model as a function of a set of characteristics of circuit designs of circuit optimization achievable due to a circuit modification procedure, such as timing constrained gate length modification for leakage power reduction. Using values of said set of characteristics for the target circuit design, the computer-implemented model is applied to the target circuit design to produce an indication of susceptibility of the target circuit design to optimization. The model can be produced using Monte Carlo simulations of a set of virtual designs, and fitting a function of said characteristics to the results. | 04-21-2011 |
20110140278 | OPTICAL PROXIMITY CORRECTION AWARE INTEGRATED CIRCUIT DESIGN OPTIMIZATION - An EDA method is implemented for modifying a layout file after place and route. The method includes storing a library of shape modifications for cells in the design library used for implementation of the circuit. The library of shape modifications includes the results of process-specific calibration of the shape modifications which indicate adjustment of a circuit parameter caused by applying the shape modifications to the cells. The layout file is analyzed to identify a cell for adjustment of the circuit parameter. A shape modification calibrated to achieve the desired adjustment is selected from the library. The shape modification is applied to the identified cell in the layout file to produce a modified layout file. The modified layout file can be used for tape out, and subsequently for manufacturing of an improved integrated circuit. | 06-16-2011 |
20110231811 | MODELING OF CELL DELAY CHANGE FOR ELECTRONIC DESIGN AUTOMATION - An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage V | 09-22-2011 |
20120131531 | Reducing Leakage Power in Integrated Circuit Designs - A method for reducing leakage power of an IC during the design of the IC. A cell based IC design is received that includes a plurality of signal paths with positive slack. The positive slack is converted to negative slack by replacing cell instances in the IC design with footprint equivalent variants of the cell instances. The negative slack is converted back to positive slack via an iterative path-based analysis of the IC design. In each iteration, a path is selected that has negative slack and replacement values are computed for cell instances in the path. One or more cell instances in the path are then replaced with variants based on the replacement values. | 05-24-2012 |
20120324411 | INTEGRATED CIRCUIT OPTIMIZATION MODELING TECHNOLOGY - A design optimization method for a target circuit design specified by a machine-readable file, comprises providing a computer-implemented model as a function of a set of characteristics of circuit designs of circuit optimization achievable due to a circuit modification procedure, such as timing constrained gate length modification for leakage power reduction. Using values of said set of characteristics for the target circuit design, the computer-implemented model is applied to the target circuit design to produce an indication of susceptibility of the target circuit design to optimization. The model can be produced using Monte Carlo simulations of a set of virtual designs, and fitting a function of said characteristics to the results. | 12-20-2012 |
20120324412 | Reducing Leakage Power in Integrated Circuit Designs - A method for reducing leakage power of an IC during the design of the IC. A cell based IC design is received that includes a plurality of signal paths with positive slack. The positive slack is converted to negative slack by replacing cell instances in the IC design with footprint equivalent variants of the cell instances. The negative slack is converted back to positive slack via an iterative path-based analysis of the IC design. In each iteration, a path is selected that has negative slack and replacement values are computed for cell instances in the path. One or more cell instances in the path are then replaced with variants based on the replacement values. | 12-20-2012 |
20130174115 | MODELING OF CELL DELAY CHANGE FOR ELECTRONIC DESIGN AUTOMATION - An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage V | 07-04-2013 |
20150022550 | SYSTEMS AND METHODS FOR IMAGE PROCESSING - Embodiments of the present disclosure can be used to generate an image replica of a person wearing various outfits to help the person visualize how clothes and accessories will look without actually having to try them on. Images can be generated from various angles to provide the person an experience as close as possible to actually wearing the clothes, accessories and looking at themselves in the mirror. Among other things, embodiments of the present disclosure can help remove much of the current uncertainty involved in buying clothing and accessories online. | 01-22-2015 |