Patent application number | Description | Published |
20090302427 | Semiconductor Chip with Reinforcement Structure - Various semiconductor chip reinforcement structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate wherein the semiconductor chip has a first side facing toward but separated from a second of the substrate to define an interface region. An array of electrical interconnects is provided between the semiconductor chip and the substrate positioned in the interface region. A reinforcement structure is coupled to the first side of the semiconductor chip and the second side of the substrate and in the interface region while outside the array of electrical interconnects. An underfill is provided in the interface region. | 12-10-2009 |
20100207281 | Semiconductor Chip with Reinforcement Layer - Various semiconductor chip reinforcement structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a side and forming a polymer layer on the side. The polymer layer has a central portion and a first frame portion spatially separated from the central portion to define a first channel. | 08-19-2010 |
20100301460 | SEMICONDUCTOR DEVICE HAVING A FILLED TRENCH STRUCTURE AND METHODS FOR FABRICATING THE SAME - Methods are provided for packaging a semiconductor die having a first surface. In accordance with an exemplary embodiment, a method comprises the steps of forming a trench in the first surface of the die, electrically and physically coupling the die to a packaging substrate, forming a sealant layer on the first surface of the die, forming an engagement structure within the trench, and infusing underfill between the sealant layer and the engagement structure and the packaging substrate. | 12-02-2010 |
20110031603 | SEMICONDUCTOR DEVICES HAVING STRESS RELIEF LAYERS AND METHODS FOR FABRICATING THE SAME - Methods are provided for fabricating a semiconductor device. In accordance with an exemplary embodiment, a method comprises the steps of providing a semiconductor die having a conductive terminal, forming an insulating layer overlying the semiconductor die, and forming a cavity in the insulating layer which exposes the conductive terminal. The method also comprises forming a first stress-relief layer in the cavity, forming an interconnecting structure having a first end electrically coupled to the first stress-relief layer, and having a second end, and electrically and physically coupling the second end of the interconnecting structure to a packaging substrate. | 02-10-2011 |
20130221517 | SEMICONDUCTOR WORKPIECE WITH BACKSIDE METALLIZATION AND METHODS OF DICING THE SAME - Various semiconductor workpieces and methods of dicing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a channel in a metallization structure on a backside of a semiconductor workpiece. The semiconductor workpiece includes a substrate. The channel is in substantial alignment with a dicing street on a front side of the semiconductor chip. | 08-29-2013 |
20130256872 | THERMAL MANAGEMENT OF STACKED SEMICONDUCTOR CHIPS WITH ELECTRICALLY NON-FUNCTIONAL INTERCONNECTS - A method of manufacturing is provided that includes fabricating a first plurality of electrically functional interconnects on a front side of a first semiconductor chip and fabricating a first plurality of electrically non-functional interconnects on a back side of the first semiconductor chip. Additional chips may be stacked on the first semiconductor chip. | 10-03-2013 |
20130256895 | STACKED SEMICONDUCTOR COMPONENTS WITH UNIVERSAL INTERCONNECT FOOTPRINT - A method of manufacturing is provided that includes fabricating a first set of interconnect structures on a side of a first semiconductor substrate. The first semiconductor substrate is operable to have at least one of plural semiconductor substrates stacked on the side. The first set of interconnect structures is arranged in a pattern. Each of the plural semiconductor substrates has a second set of interconnect structures arranged in the pattern, one of the plural semiconductor substrates has a smallest footprint of the plural semiconductor substrates. The pattern has a footprint smaller than the smallest footprint of the plural semiconductor substrates. | 10-03-2013 |
20130256913 | DIE STACKING WITH COUPLED ELECTRICAL INTERCONNECTS TO ALIGN PROXIMITY INTERCONNECTS - A method of manufacturing is provided that includes forming a first proximity interconnect on a first side of a first semiconductor chip and a first plurality of interconnect structures projecting from the first side. A second proximity interconnect is formed on a second side of a second semiconductor chip and a second plurality of interconnect structures are formed projecting from the second side. The second semiconductor chip is coupled to the first semiconductor chip so that the second side faces the first side and the first interconnect structures are coupled to the second interconnect structures. The first and second proximity interconnects cooperate to provide a proximity interface. The coupling of the first interconnect structures to the second interconnect structures provides desired vertical and lateral alignment of the first and second proximity interconnects. | 10-03-2013 |
Patent application number | Description | Published |
20090065952 | Semiconductor Chip with Crack Stop - Various semiconductor chip crack stops and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor substrate that has a first corner defined by a first edge and a second edge. A crack stop is formed in the semiconductor substrate. The crack stop includes a first projection extending to the first edge and a second projection extending to the second edge to fence off a portion of the semiconductor substrate that includes the first corner. | 03-12-2009 |
20100207250 | Semiconductor Chip with Protective Scribe Structure - Apparatus and methods pertaining to die scribe structures are disclosed. In one aspect, a method of manufacturing is provided that includes fabricating an active region of a semiconductor die so that the active region has at least one corner. A scribe structure is fabricated around the active region so that the scribe structure includes at least one fillet. | 08-19-2010 |
20110147916 | Semiconductor Chip Device with Solder Diffusion Protection - Various methods and apparatus for establishing thermal pathways for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor chip that has a substrate and a first active circuitry portion extending a first distance into the substrate. A barrier is formed in the first semiconductor chip that surrounds but is laterally separated from the first active circuitry portion and extends into the substrate a second distance greater than the first distance. | 06-23-2011 |
20120038061 | SEMICONDUCTOR CHIP WITH OFFSET PADS - A semiconductor chip device includes a first semiconductor chip adapted to be stacked with a second semiconductor chip wherein the second semiconductor chip includes a side and first and second conductor structures projecting from the side. The first semiconductor chip includes a first edge, a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and that has a first lateral dimension and is adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad and that has a second lateral dimension larger than the first lateral dimension and is adapted to couple to the other of the first and second conductor structures. | 02-16-2012 |
20120043539 | SEMICONDUCTOR CHIP WITH THERMAL INTERFACE TAPE - A method of manufacturing is provided that includes applying a thermal interface tape to a side of a semiconductor wafer that includes at least one semiconductor chip. The thermal interface material tape is positioned on the at least one semiconductor chip. The at least one semiconductor chip is singulated from the semiconductor wafer with at least a portion of the thermal interface tape still attached to the semiconductor chip. | 02-23-2012 |
20120043668 | STACKED SEMICONDUCTOR CHIPS WITH THERMAL MANAGEMENT - A method of assembling a semiconductor chip device is provided that includes placing an interposer on a first semiconductor chip. The interposer includes a first surface seated on the first semiconductor chip and a second surface adapted to thermally contact a heat spreader. The second surface includes a first aperture. A second semiconductor chip is placed in the first aperture. | 02-23-2012 |
20120043669 | STACKED SEMICONDUCTOR CHIP DEVICE WITH THERMAL MANAGEMENT CIRCUIT BOARD - A method of assembling a semiconductor chip device is provided that includes providing a circuit board including a surface with an aperture. A portion of a first heat spreader is positioned in the aperture. A stack is positioned on the first heat spreader. The stack includes a first semiconductor chip positioned on the first heat spreader and a substrate that has a first side coupled to the first semiconductor chip. | 02-23-2012 |
20120061821 | SEMICONDUCTOR CHIP WITH REDUNDANT THRU-SILICON-VIAS - A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias. | 03-15-2012 |
20120061852 | SEMICONDUCTOR CHIP DEVICE WITH POLYMERIC FILLER TRENCH - A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench. | 03-15-2012 |
20120061853 | SEMICONDUCTOR CHIP DEVICE WITH UNDERFILL - A method of manufacturing is provided that includes placing a removable cover on a surface of a substrate. The substrate includes a first semiconductor chip positioned on the surface. The first semiconductor chip includes a first sidewall. The removable cover includes a second sidewall positioned opposite the first sidewall. A first underfill is placed between the first semiconductor chip and the surface wherein the second sidewall provides a barrier to flow of the first underfill. Various apparatus are also disclosed. | 03-15-2012 |
20120074579 | SEMICONDUCTOR CHIP WITH REINFORCING THROUGH-SILICON-VIAS - A method of manufacturing includes connecting a first end of a first through-silicon-via to a first die seal proximate a first side of a first semiconductor chip. A second end of the first thu-silicon-via is connected to a second die seal proximate a second side of the first semiconductor chip opposite the first side. | 03-29-2012 |
20120075807 | STACKED SEMICONDUCTOR CHIP DEVICE WITH THERMAL MANAGEMENT - A method of manufacturing is provided that includes placing a thermal management device in thermal contact with a first semiconductor chip of a semiconductor chip device. The semiconductor chip device includes a first substrate coupled to the first semiconductor chip. The first substrate has a first aperture. At least one of the first semiconductor chip and the thermal management device is at least partially positioned in the first aperture. | 03-29-2012 |
20120098119 | SEMICONDUCTOR CHIP DEVICE WITH LIQUID THERMAL INTERFACE MATERIAL - A method of manufacturing is provided that includes providing a semiconductor chip device that has a circuit board and a first semiconductor chip coupled thereto. A lid is placed on the circuit board. The lid includes an opening and an internal cavity. A liquid thermal interface material is placed in the internal cavity for thermal contact with the first semiconductor chip and the circuit board. | 04-26-2012 |
20120119767 | POWER CYCLING TEST ARRANGEMENT - A device instructs a power supply to provide a current to a power cycling test structure that includes a heat source interconnected with a package, via a first level interconnect mechanism, and a printed circuit board (PCB) interconnected with the package, via a second level interconnect mechanism. The device also monitors thermal feedback associated with the heat source, and monitors, based on the provided current, voltage feedback associated with the power cycling test structure. The device further determines a thermal profile of the power cycling test structure based on the thermal feedback and the voltage feedback. | 05-17-2012 |
20120241985 | SEMICONDUCTOR CHIP WITH SUPPORTIVE TERMINAL PAD - Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a first conductor pad and a passivation structure. A second conductor pad is fabricated around but not in physical contact with the first conductor pad to leave a gap. The second conductor pad is adapted to protect a portion of the passivation structure. | 09-27-2012 |
20130049229 | SEMICONDUCTOR CHIP DEVICE WITH SOLDER DIFFUSION PROTECTION - Various methods and apparatus for establishing thermal pathways for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor chip that has a substrate and a first active circuitry portion extending a first distance into the substrate. A barrier is formed in the first semiconductor chip that surrounds but is laterally separated from the first active circuitry portion and extends into the substrate a second distance greater than the first distance. | 02-28-2013 |
20130147028 | HEAT SPREADER FOR MULTIPLE CHIP SYSTEMS - Various heat spreaders and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a heat spreader that has a surface adapted to establish thermal contact with a first semiconductor chip and a second semiconductor chip on a substrate. The surface includes a first portion adapted to thermally contact a solder-based thermal interface material and a second portion having an opening adapted to hold an organic thermal interface material. | 06-13-2013 |
20130161814 | SEMICONDUCTOR CHIP WITH OFFSET PADS - A semiconductor chip device includes a first semiconductor chip adapted to be stacked with a second semiconductor chip wherein the second semiconductor chip includes a side and first and second conductor structures projecting from the side. The first semiconductor chip includes a first edge, a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and that has a first lateral dimension and is adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad and that has a second lateral dimension larger than the first lateral dimension and is adapted to couple to the other of the first and second conductor structures. | 06-27-2013 |
20130341783 | INTERPOSER WITH IDENTIFICATION SYSTEM - Various interposers and method of manufacturing related thereto are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an identification structure to an interposer. The identification structure is operable to provide identification information about the interposer. The identification structure is programmable to create or alter the identification information. | 12-26-2013 |
20130341802 | INTEGRATED CIRCUIT PACKAGE HAVING OFFSET VIAS - Integrated circuit packages comprise vias, each of which extends from a pad in communication with an integrated circuit on a semiconductor chip through insulating material overlying the semiconductor chip to an attachment surface facing a substrate. The portion of each via proximate the attachment surface is laterally offset from the portion proximate the pad from which it extends in a direction away from the centre of the semiconductor chip. Metallic material received in the vias mechanically and electrically interconnects the semiconductor chip to the substrate. | 12-26-2013 |
20130342231 | SEMICONDUCTOR SUBSTRATE WITH ONBOARD TEST STRUCTURE - Various interposers and methods of manufacturing related thereto are disclosed. In one aspect, a method of manufacturing is provided that includes fabricating a first test structure onboard an interposer that has a first side and second side opposite the first side. Additional test structures may be fabricated. | 12-26-2013 |
20140103506 | SEMICONDUCTOR CHIP DEVICE WITH POLYMERIC FILLER TRENCH - A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench. | 04-17-2014 |
Patent application number | Description | Published |
20110009512 | REDUCTION OF ALDEHYDES IN AMINES - A tertiary amine, such as a tertiary amine catalyst that is useful in the production of polyurethanes, may undergo decomposition, which may result in the production of undesirable products. These tertiary amines, however, may be treated with a primary amine containing material to reduce the presence of the undesirable products to an acceptable level. Thus, a foam made from a treated tertiary amine will also have a reduction in the presence of the same undesirable products. | 01-13-2011 |
20110112335 | PROCESS FOR THE PRODUCTION AND PURIFICATION OF PROPYLENE GLYCOL - The present invention relates to a process for producing an odorless and colorless industrial grade propylene glycol from glycerol obtained during the manufacturing of biodiesel. The process includes hydrogenating the glycerol to form a hydrogenated product, distilling the hydrogenated product to form a glycol product, and contacting the glycol product with a treatment bed. The propylene glycol may be used in various industrial and consumer applications and products such as personal care products. | 05-12-2011 |
20130280155 | Sterically Hindered Amines and Associated Methods - Amine compositions comprising sterically hindered amines and associated methods are provided. In some embodiments, amine compositions of the present disclosure may be useful for selective removal of H | 10-24-2013 |
20150051132 | Emulsifier for Lubricating Oil Concentrate - The present disclosure provides a lubricating oil concentrate containing an ethoxylated ether amine and a base oil. The lubricating oil concentrate is capable of forming a stable, low foaming emulsion when added to an aqueous medium and may be useful in metalworking and cleaning fluids. | 02-19-2015 |
Patent application number | Description | Published |
20110013766 | METHOD AND APPARATUS HAVING ECHO CANCELLATION AND TONE DETECTION FOR A VOICE/TONE COMPOSITE SIGNAL - A system includes receive and send inputs, an adaptive filter, a combiner, a non-linear processor, and a tone detector. The receive input receives a first signal having first voice and first tone information. The send input receives a second signal having echo information, second tone information, and second voice information. The adaptive filter has an input coupled to the receive input, and an output. The combiner has a first input coupled to the send input, a second input coupled to the output of the adaptive filter, and an output providing an intermediate signal. The nonlinear processor has an input coupled to the output of the combiner and an output for providing an output signal for obtaining the second voice. The tone detector is coupled to the output of the combiner and detects the second tone in the intermediate signal prior to the intermediate signal being processed by the nonlinear processor. | 01-20-2011 |
20110261948 | Techniques for Updating Filter Coefficients of an Adaptive Filter - A technique for updating filter coefficients of an adaptive filter includes filtering a signal with an adaptive filter, whose filter coefficients are grouped into filter blocks. In this case a number of the filter blocks is less than or equal to a number of the filter coefficients. During each update period, the filter coefficients for less than all of the filter blocks are updated based on a network echo path impulse response. | 10-27-2011 |
20110261949 | Techniques for Implementing Adaptation Control of an Echo Canceller to Facilitate Detection of In-Band Signals - A technique for detecting in-band signaling tones in a communication system includes performing a first adaptation of an adaptive filter of an echo canceller in response to detection of a far-end harmonic signal. In this case, the adaptive filter provides an echo estimation signal. The technique also includes subtracting the echo estimation signal from a near-end signal that includes one or more in-band signaling tones to provide an error signal. The technique further includes detecting, using a tone detector, the one or more in-band signaling tones in the error signal. | 10-27-2011 |
Patent application number | Description | Published |
20110225030 | INTEGRATED QUALIFICATION AND MONITORING FOR CUSTOMER PROMOTIONS - A device receives, from a user device, a request for qualified offers for a particular customer, and retrieves, based on the request, profile information associated with the particular customer. The device generates a call to a backend database based on the profile information, and receives, from the backend database, offer qualification indicators based on the call. The device determines qualified offers based on the offer qualification indicators, and provides the qualified offers to the user device for display. | 09-15-2011 |
20120284125 | INTEGRATED QUALIFICATION AND MONITORING FOR CUSTOMER PROMOTIONS - A device receives, from a user device, a request for qualified offers for a particular customer, and retrieves, based on the request, profile information associated with the particular customer. The device generates a call to a backend database based on the profile information, and receives, from the backend database, offer qualification indicators based on the call. The device determines qualified offers based on the offer qualification indicators, and provides the qualified offers to the user device for display. | 11-08-2012 |
20130132332 | RULE CREATION AND APPLICATION - A computing device receives a rule that includes information describing conditions associated with a consequence, and identifies rule components corresponding to the rule. The computing device creates a rule formula, based on the rule components, by creating a first-order logic version of the rule and creating a rule formula table based on the first-order logic version of the rule. The computing device stores the rule formula table in a relational database. | 05-23-2013 |
Patent application number | Description | Published |
20120222082 | Low Noise Amplifier and Method of Input Impedance Control for Terrestrial and Cable Modes - A low noise amplifier (LNA) for use in a receiver circuit includes an adjustable impedance network including an input for receiving a radio frequency signal, a plurality of control inputs, and an output. The LNA further includes a controller coupled to the plurality of control inputs and configured to control an impedance of the adjustable impedance network. The controller controls the adjustable impedance network to provide a relatively low impedance in a terrestrial mode and to provide a relatively high impedance in a cable mode. | 08-30-2012 |
20130171952 | LOW-COST RECEIVER USING INTEGRATED INDUCTORS - A receiver includes a first amplifier, a first variable capacitor, and an inductance leg. The first amplifier has an input for receiving a radio frequency signal, and an output. The first variable capacitor has a first terminal coupled to the output of the first amplifier, a second terminal coupled to a power supply voltage terminal, and a control terminal for receiving a tuning signal. The inductance leg has a first terminal coupled to the output of the first amplifier, and a second terminal coupled to the power supply voltage terminal. The inductance leg includes a first inductor and has an effective resistance in series with the first inductor, wherein the effective resistance has a value related to an upper frequency threshold to be tuned by the receiver. | 07-04-2013 |
20130171954 | RECEIVER INCLUDING A TRACKING FILTER - A receiver includes a low noise amplifier having an input for receiving a radio frequency signal, and an output. The receiver further includes a tracking Filter having an input coupled to the output of the low noise amplifier. The tracking filter including a bandpass filter configured to pass the radio frequency signals. The bandpass filter includes a variable capacitor having a first electrode coupled to the input of the tracking filter for receiving the radio frequency signals, and a second electrode coupled to a power supply terminal. The bandpass filter further includes a transformer having a primary winding including a first terminal coupled to the first electrode of the variable capacitor and a second terminal coupled to a second power supply terminal. The transformer further includes a secondary winding. | 07-04-2013 |
20140361838 | AMPLIFIER FOR TELEVISION TUNER CHIP AND METHOD THEREFOR - An amplifier includes a negative gain amplifier, a load element, and a transconductance device. The negative gain amplifier has an input and an output. The load element has a first terminal coupled to a power supply voltage terminal, and a second terminal. The transconductance device has a first current electrode coupled to the second terminal of the load element, a control electrode coupled to the output of the negative gain amplifier, and a second current electrode coupled to the input of the negative gain amplifier. | 12-11-2014 |
20150123714 | HIGHLY LINEAR BUFFER - Techniques relating to buffer circuits. In one embodiment, a circuit includes a first transistor configured as a source follower and a feed-forward path coupled to the gate terminal of the first transistor and the drain terminal of the first transistor. In this embodiment, the feed-forward path includes circuitry configured to decouple the feed-forward path from a DC component of an input signal to the gate terminal of the first transistor. In this embodiment, the circuitry is configured to reduce a drain-source voltage of the first transistor based on the input signal. In some embodiment, the feed-forward path includes a second transistor configured as a source follower and the source terminal of the second transistor is coupled to the drain terminal of the first transistor. In various embodiments, reducing the drain-source voltage may improve linearity of the first transistor. | 05-07-2015 |
20150147991 | LOW-COST RECEIVER USING INTEGRATED INDUCTORS - A receiver includes a first amplifier having an input for receiving an RF signal, and an output for providing an amplified RF signal, a switch section that selectively switches the amplified RF signal onto a selected one of a plurality of nodes, and a filter section comprising a plurality of filters coupled to respective ones of the plurality of nodes. A first filter of the plurality of filters comprises a first variable capacitor coupled in parallel with an inductance leg between a corresponding one of the plurality of nodes and a power supply voltage terminal. The first variable capacitor has a capacitance that varies in response to a tuning signal. The inductance leg includes a first inductor in series with an effective resistance, wherein the effective resistance has a value related to an upper cutoff frequency to be tuned by the first filter. | 05-28-2015 |
Patent application number | Description | Published |
20120287215 | REFLECTOR STRUCTURE FOR A RADIANT DRYER UNIT OF AN INKJET PRINTER - Structures for radiant dryer units of a printer. A radiant dryer unit includes a reflector element that reflects light waves from a light source back towards a printable medium to dry ink printed on the medium. The reflector element includes a plurality of modular sections. Each modular section includes a base portion having a reflective surface, and includes legs that protrude from an opposing surface of the base portion. The modular sections are affixed to one another so that the reflective surfaces of the modular sections form an aggregate reflective surface that faces toward the light source of the radiant dryer unit. | 11-15-2012 |
20140076633 | HOUSING FOR DOWNHOLE MEASUREMENT - Systems, methods and devices for equipping a rotatable drill string with measurement equipment. The system includes a removable carriage unit arranged and designed to be disposed within a bore of a removable section of the rotatable drill string. The removable carriage unit has measurement equipment disposed within a cavity thereof. The method includes disposing measurement equipment in the cavity of the removable carriage unit, coupling the removable carriage unit with a first end portion of the removable section of the rotatable drill string after disposing the measurement equipment in the cavity, and coupling a second end portion of the removable section with a shaft of the rotatable drill string. | 03-20-2014 |
20150114716 | VIBRATION TOOL - Various implementations described herein are directed to a vibration tool, e.g., for use in drilling or other downhole operations. In one implementation, the vibration tool may include a housing having a bore extending therethrough. The vibration tool may also include a piston subassembly positioned inside the bore, where the piston subassembly is configured to oscillate when fluid flow inside the piston subassembly exceeds a predetermined flow rate. The vibration tool may further include a valve mechanism positioned around the piston subassembly, where the valve mechanism is configured to restrict fluid to flow inside the piston subassembly when the valve mechanism is in a closed state and configured to allow the fluid to flow from the piston subassembly to the bore when the valve mechanism is in an open state. | 04-30-2015 |
20150376950 | DOWNHOLE TOOL USING A LOCKING CLUTCH - A downhole tool may be operated using a locking clutch. The downhole tool may include an upper downhole motor having a rotor. The downhole tool may also include a lower downhole motor having a shaft. Both the rotor and shaft may rotate relative to the housing. The locking clutch may be coupled to the rotor and the shaft, and may transmit a torque from the rotor to the shaft. The locking clutch may include at least one locking pawl configured to move from an engaged position to a disengaged position when the shaft rotates above a disengagement speed. In the engaged position, the upper downhole motor may provide a torque boost to limit sticking or stall of a drill bit coupled to the downhole tool. | 12-31-2015 |