Patent application number | Description | Published |
20120161983 | PARKING PILOT METHOD AND DEVICE - A parking pilot method and a device thereof are disclosed. Image detectors capture surrounding images of a vehicle. A speed detector detects speed of the vehicle. A distance detector obtains distance between the vehicle and a barrier. A processor obtains relative coordinates of the vehicle and parking lot and the angle and width of the parking lot with the images, speed and distances. Thereby, the processor creates a preset parking pilot frame and works out a relative position of the preset parking pilot frame and the parking lot. Then, the processor designates the preset parking pilot frame and the parking lot on a display. According to the information on the display, the driver moves the vehicle to an initial position and makes the preset parking pilot frame coincide with the parking lot. Then, the processor instructs the driver to manually park the vehicle, or automatically parks the vehicle. | 06-28-2012 |
20120173083 | VEHICLE ROLL OVER PREVENTION SAFETY DRIVING SYSTEM AND METHOD - A vehicle rollover prevention safety driving system, comprising: at least an image sensor, used to fetch road images in front of said vehicle; an image processor, connected to said image sensor, and is used to identify a drive lane in road images, and calculate a drive lane curvature, an inclination angle of said road, and relative positions of said vehicle and a lane marking; a vehicle conditions sensing module, used to sense dynamic information of a vehicle turning angle, a vehicle inclination angle, and a vehicle speed; a microprocessor, connected to said image processor and said vehicle conditions sensing module, and it calculates a rollover prediction point and a rollover threshold speed, and it issues a corresponding warning signal or a control signal; and an accelerator and brake controller, connected to said microprocessor, and it controls deceleration of said vehicle according to said control signal. | 07-05-2012 |
Patent application number | Description | Published |
20080303550 | INTEGRATED CIRCUIT WITH PLURAL LEVEL SHIFTERS - An integrated circuit is provided. The integrated circuit includes N level shifting devices. Each level shifting device receives a first digital signal and a second digital signal, and includes a first level shifter converting a first voltage of the first digital signal into a third voltage and converting a second voltage of the first digital signal into a fourth voltage, and a second level shifter converting a first voltage of the second digital signal into a fifth voltage and converting a second voltage of the second digital signal into a sixth voltage. | 12-11-2008 |
20090160835 | SIGNAL PROCESSING CIRCUIT AND METHOD - A signal processing method is provided and includes the following steps. A first synchronizing signal having a synchronizing frequency and a next expected pulse with an expected rising edge is provided. A second synchronizing signal having a selected frequency being within a frequency range is produced when the synchronizing frequency of the first synchronizing signal is out of a frequency range. A third synchronizing signal having a first pulse with a first rising edge is produced when the synchronizing frequency is within the frequency range, wherein the first rising edge is produced at an expected time point. Whether the next expected pulse appears in a period from the expected time point to a certain time point is detected as a detecting result. And a first falling edge of the first pulse is produced based on the detecting result. A picture-field flicker phenomenon of an LCD is eliminated through the method. | 06-25-2009 |
20130080668 | INTEGRATED CIRCUT WITH SERIAL INTERFACE, RECEIVING TRANSMITTAL INFORMATION CONFORMING TO TWO COMMUNICATION PROTOCOLS - A processing system including a control integrated circuit (IC), a serial transmission interface, a transformation unit and an application unit is disclosed. The control IC provides transmittal information, which conforms to a first communication protocol or a second communication protocol. The serial transmission interface is coupled to the control IC and receives the transmittal information. The transformation unit is coupled to the serial transmission interface. The transformation unit transforms the transmittal information received by the serial transmission interface to generate processed information when the transmittal information conforms to the first communication protocol. The transformation unit transforms the transmittal information received by the serial transmission interface to generate the processed information when the transmittal information conforms to the second communication protocol. The application unit is coupled to the transformation unit and executes a corresponding operation according to the processed information. | 03-28-2013 |
Patent application number | Description | Published |
20130242578 | HIGH THERMALLY CONDUCTIVE COMPOSITES AND ILLUMINATION DEVICE - Disclosed is a high thermally conductive composite, including a first composite and a second composite having a co-continuous and incompatible dual-phase manner. The first composite consists of glass fiber distributed in polyphenylene sulfide (PPS), acrylonitrile-butadiene-styrene copolymer (ABS), polybutylene terephthalate (PBT), poly(ε-caprolactam) (Nylon 6), polyhexamethylene adipamide (nylon 66), or polypropylene (PP). The second composite consists of carbon material distributed in polyethylene terephthalate. | 09-19-2013 |
20150175771 | COMPOSITE AND METHOD FOR FORMING THE SAME - A method for forming composite is provided. The method comprises following steps. Firstly, a polypropylene homopolymer and at least one kind of inorganic particles are provided to a twin screw extruder, wherein the polypropylene homopolymer occupies 40 wt %˜90 wt % of the composite, the inorganic particles occupies 10 wt %˜60 wt % of the composite, the melt flow index of the polypropylene homopolymer is lower than 3.6 g/10 min, and the particle sizes of the inorganic particles are in a range of 100 nm to 1000 nm. The polypropylene homopolymer is heated to a molten state. Then, the molten-state polypropylene homopolymer and the inorganic particles are enabled to pass through at least five kneading blocks of the twin screw extruder to be mixed together such that the inorganic particles are dispersed in the polypropylene homopolymer. | 06-25-2015 |
Patent application number | Description | Published |
20140264362 | Method and Apparatus for Forming a CMOS Device - A method and apparatus for forming a CMOS device are provided. The CMOS device may include an N-type channel region formed of an III-V material and a P-type channel region formed of a germanium material. Over each channel may be formed corresponding gates and source/drain regions. The source/drain regions may be formed of a germanium material and one or more metallization layers. An anneal may be performed to form ohmic contacts for the source/drain regions. Openings may be formed in a dielectric layer covering the device and conductive plugs may be formed to provide contact to the source/drain regions. | 09-18-2014 |
20150044842 | Integrating Junction Formation of Transistors with Contact Formation - A method includes forming a gate stack over a semiconductor region, depositing an impurity layer over the semiconductor region, and depositing a metal layer over the impurity layer. An annealing is then performed, wherein the elements in the impurity layer are diffused into a portion of the semiconductor region by the annealing to form a source/drain region, and wherein the metal layer reacts with a surface layer of the portion of the semiconductor region to form a source/drain silicide region over the source/drain region. | 02-12-2015 |
20150129938 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region. | 05-14-2015 |
20160043173 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor structure, a semiconductor device, and a method for forming the semiconductor device are provided. In various embodiments, the method for forming the semiconductor device includes forming transistors on a substrate. Forming each transistor includes forming a doped region on the substrate. A nanowire is formed protruding from the doped region. An interlayer dielectric layer is deposited over the doped region. A dielectric layer is deposited over the interlayer dielectric layer and surrounding each of the nanowires. A first gate layer is deposited over the dielectric layer. The dielectric layer and first gate layer are etched to expose portions of the nanowires and the interlayer dielectric layer. A second gate layer is formed over the exposed interlayer dielectric layer and surrounding the first gate layer. Then, the second gate layer was patterned to remove the second gate layer on the interlayer dielectric layer between the transistors. | 02-11-2016 |
20160071966 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region. | 03-10-2016 |
20160079358 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor structure, and methods for forming the semiconductor device are provided. In various embodiments, the semiconductor device includes a substrate, source/drain regions over the substrate, a plurality of nanowires over the substrate and sandwiched by the source/drain regions, a gate dielectric layer surrounding the plurality of nanowires, and a gate layer surrounding the gate dielectric layer. | 03-17-2016 |
Patent application number | Description | Published |
20150069467 | DELTA DOPING LAYER IN MOSFET SOURCE/DRAIN REGION - A transistor includes a gate terminal, a source terminal and a drain terminal. At least one of the source and drain terminals has a layered configuration that includes a terminal layer and an intervening layer. The terminal layer has a top surface and a bottom surface. The intervening layer is located within the terminal layer, between and spaced from the top and bottom surfaces, is oriented to be perpendicular to current flow, and is less than one tenth the thickness of the terminal layer. The terminal layer and the intervening layer include a common semiconductive compound and a common dopant, with a concentration of the dopant in the intervening layer being over ten times an average concentration of the dopant in the terminal layer. | 03-12-2015 |
20150102287 | NANOWIRE MOSFET WITH SUPPORT STRUCTURES FOR SOURCE AND DRAIN - A transistor device and method for forming a nanowire field effect transistor (FET) device are provided. A device layer including a source region and a drain region is formed, where the source region and the drain region are connected by a suspended nanowire channel. Etch stop layers are formed beneath the source region and the drain region. The etch stop layers comprise support structures interposed between a semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material beneath the suspended nanowire channel. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region. | 04-16-2015 |
20150108550 | TRANSISTOR AND METHOD FOR FORMING THE SAME - A method for forming a transistor is provided. The method includes: forming a channel layer over a substrate; patterning the channel layer to form a recess; and forming a source layer in the recess, such that at least a portion of the channel layer protrudes to form the fin-type channel. | 04-23-2015 |
20150129981 | SEMICONDUCTOR DEVICE HAVING FIN-TYPE CHANNEL AND METHOD FOR FORMING THE SAME - A method for forming a semiconductor device having a fin-type channel is provided. The method may include the following operations: forming a first buffer layer over a substrate; forming a first dielectric layer over the first buffer layer; patterning the first dielectric layer over the first buffer layer; forming a barrier layer over the first buffer layer; forming a second dielectric layer over the barrier layer; patterning the second dielectric layer over the barrier layer; forming a channel layer over the barrier layer; and patterning the second dielectric layer, such that at least a portion of the channel layer protrudes to form the fin-type channel. | 05-14-2015 |
20150228721 | FIN STRUCTURE AND METHOD FOR FORMING THE SAME - According to an exemplary embodiment, a method of forming a fin structure is provided. The method includes the following operations: etching a first dielectric layer to form at least one recess and a first core portion of a fin core; form an oxide layer as a shallow trench isolation layer in the recess; etching back the oxide layer to expose a portion of the fin core; and forming a fin shell to cover a sidewall of the exposed portion of the fin core. | 08-13-2015 |
20150255306 | NANOWIRE MOSFET WITH SUPPORT STRUCTURES FOR SOURCE AND DRAIN - A nanowire field effect transistor (FET) device and method for forming the same is disclosed. The device comprises: a semiconductor substrate; a device layer including a source region and a drain region connected by a suspended nanowire channel; and etch stop layers respectively arranged beneath the source region and the drain region, the etch stop layers forming support structures interposed between the semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material disposed beneath the suspended nanowire channel and between the etch stop layers. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region. | 09-10-2015 |
20150263094 | SEMICONDUCTOR DEVICES WITH CORE-SHELL STRUCTURES - A device structure includes: a core structure formed on a support, and a shell material formed on the core structure and surrounding at least part of the core structure. The shell material and the core structure are configured to form a quantum-well channel in the shell material. | 09-17-2015 |
20160064493 | FIN STRUCTURE AND METHOD FOR FORMING THE SAME - According to an exemplary embodiment, a method of forming a fin structure is provided. The method includes the following operations: etching a first dielectric layer to form at least one recess and a first core portion of a fin core; form an oxide layer as a shallow trench isolation layer in the recess; etching back the oxide layer to expose a portion of the fin core; and forming a fin shell to cover a sidewall of the exposed portion of the fin core. | 03-03-2016 |