Charra
Elodie Charra, Antibe FR
Elodie Charra, Antibes FR
Patent application number | Description | Published |
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20080229070 | Cache circuitry, data processing apparatus and method for prefetching data - Cache circuitry, a data processing apparatus including such cache circuitry, and a method for prefetching data into such cache circuitry, are provided. The cache circuitry has a cache storage comprising a plurality of cache lines for storing data values, and control circuitry which is responsive to an access racquet issued by a device of the data processing apparatus identifying a memory address of a data value to be accessed, to cause a lookup operation to be performed to determine whether the data value for that memory address is stored within the cache storage. If not, a linefill operation is initiated to retrieve the data value from memory. Further, prefetch circuitry is provided which is responsive to a determination that the memory address specified by a current access request is the same as a predicted memory address, to perform either a first prefetch linefill operation or a second prefetch linefill operation to retrieve from memory at least one further data value in anticipation of that data value being the subject of a subsequent access request. The selection of either the first prefetch linefill operation or the second prefetch linefill operation is performed in dependence on an attribute of the current access request. The first prefetch linefill operation involves issuing a sequence of memory addresses to memory, and allocating into a corresponding sequence of cache lines the data values returned from the memory in response to that sequence of addresses. The second prefetch linefill operation comprises issuing a selected memory address to memory, and storing in a linefill buffer the at least one data value returned from the memory in response to that memory address, with that at least one data value only being allocated into the cache when a subsequent access request specifies the selected memory address. By such an approach, the operation of the prefetch circuitry can be altered to take into account the type of access request being issued. | 09-18-2008 |
Fabrice Charra, Marcoussis FR
Patent application number | Description | Published |
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20090300805 | Photon-Emission Scanning Tunneling Microscopy - The present invention relates to an indirect-gap semiconductor substrate, the gap being greater than that of silicon and preferably greater than 1.5 eV, to its use for imaging a specimen by photon-emission scanning tunnel microscopy, and to a photon-emission scanning tunnel imaging method using such an indirect-gap semiconductor substrate. Advantageously, the indirect-gap semiconductor substrate is made of silicon carbide. The present invention also relates to devices for implementing the imaging method according to the invention. | 12-03-2009 |
20090314990 | NOVEL TRIPHENYLAMINE DERIVATIVES USEFUL AS FLUOROPHORES IN BIOLOGY, IN PARTICULAR FOR TWO-PHOTON MICROSCOPY - Triphenylamine derivatives useful as fluorophores in biology, in particular for two-photon microscopy; and | 12-24-2009 |
20100012587 | METHOD FOR TREATING A FLUID USING A SELF-ORGANIZED NETWORK ADSORBED ON A SURFACE - The invention concerns a method for treating a fluid. According to the invention, the fluid is contacted with a substrate at the surface of which there is a network of organic molecules, hereafter referred to as “network molecules”, having a central corre and at least one lateral arm, said molecules being adsorbed at the surface of the substrate. The invention also concerns a two-dimensional molecular sieve consisting of substrate at the surface of which a network of network molecules is adsorbed. The invention further concerns a module for treating a fluid comprising means for circulating the fluid to be treated and containing one or more two-dimensional molecule sieves. | 01-21-2010 |
20100072472 | Nanostructures With 0, 1, 2, and 3 Dimensions, With Negative Differential Resistance and Method for Making These Nanostructures - Nanostructures with 0, 1, 2 and 3 dimensions, with negative differential resistance and method for making these nanostructures. A nanostructure according to the invention may notably be used in nanoelectronics. It comprises at least one structure ( | 03-25-2010 |
Stephane Robert Elie Charra, Figeac FR
Patent application number | Description | Published |
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20100139865 | COMPOSITE LAY-UP HEAD WITH A RETRACTABLE DEVICE FOR SEPARATING A PREPREG FROM ITS SUPPORT TAPE - A lay-up head receives a prepreg bonded to a support tape, and the prepreg is separated from its support tape by peeling, by means of a separator just upstream of a depositing member for depositing the prepreg tape on a deposition tool; the head includes, downstream of the separator, a retractable device for moving the prepreg away from the support tape, allowing the prepreg to be moved away just upstream of the separator, by means of which the prepreg can be separated earlier when the retractable device is activated. | 06-10-2010 |