Patent application number | Description | Published |
20120132967 | THROUGH SILICON VIA AND METHOD OF FABRICATING SAME - A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closet to the substrate contacting a top surface of the conductive core. | 05-31-2012 |
20140094007 | THROUGH SILICON VIA AND METHOD OF FABRICATING SAME - A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closest to the substrate contacting a top surface of the conductive core. | 04-03-2014 |
Patent application number | Description | Published |
20080274583 | THROUGH-WAFER VIAS - A through-wafer via structure and method for forming the same. The through-wafer via structure includes a wafer having an opening and a top wafer surface. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The through-wafer via structure further includes a through-wafer via in the opening. The through-wafer via has a shape of a rectangular plate. A height of the through-wafer via in the first reference direction essentially equals a thickness of the wafer in the first reference direction. A length of the through-wafer via in a second reference direction is at least ten times greater than a width of the through-wafer via in a third reference direction. The first, second, and third reference directions are perpendicular to each other. | 11-06-2008 |
20090194864 | INTEGRATED MODULE FOR DATA PROCESSING SYSTEM - An apparatus for an integrated module. A silicon carrier with through-silicon vias has a plurality of die connected to a top side of the silicon carrier. In addition, a substrate is connected to a bottom side of the silicon carrier. The substrate is coupled to the plurality of die via the through-silicon vias. | 08-06-2009 |
20100032764 | THROUGH SILICON VIA AND METHOD OF FABRICATING SAME - A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closet to the substrate contacting a top surface of the conductive core. | 02-11-2010 |
20100035430 | METHOD OF MAKING THROUGH WAFER VIAS - A method of making a through wafer via. The method includes: forming a trench in a semiconductor substrate, the trench open to a top surface of the substrate; forming a polysilicon layer on sidewalls and a bottom of the trench; oxidizing the polysilicon layer to convert the polysilicon layer to a silicon oxide layer on the sidewalls and bottom of the trench, the silicon oxide layer not filling the trench; filling remaining space in the trench with an electrical conductor; and thinning the substrate from a bottom surface of the substrate and removing the silicon oxide layer from the bottom of the trench. The method may further include forming a metal layer on the silicon oxide layer before filling the trench. | 02-11-2010 |
20140144593 | WAFER DEBONDING USING LONG-WAVELENGTH INFRARED RADIATION ABLATION - Structures and methods are provided for temporarily bonding handler wafers to device wafers using bonding structures that include one or more releasable layers that absorb long-wavelength infrared radiation to achieve wafer debonding by infrared radiation ablation. | 05-29-2014 |
20140147986 | WAFER DEBONDING USING LONG-WAVELENGTH INFRARED RADIATION ABLATION - Methods are provided for handling a device wafer. For example, a method includes providing a stack structure having a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and handler wafer, and irradiating the bonding structure with long-wavelength infrared energy to ablate the bonding structure. | 05-29-2014 |
20150035173 | ADHESIVES FOR BONDING HANDLER WAFERS TO DEVICE WAFERS AND ENABLING MID-WAVELENGTH INFRARED LASER ABLATION RELEASE - Methods are provided to form adhesive materials that are used to temporarily bond handler wafers to device wafers, and which enable mid-wavelength infrared laser ablation release techniques to release handler wafers from device wafers. | 02-05-2015 |
20150035554 | WAFER DEBONDING USING MID-WAVELENGTH INFRARED RADIATION ABLATION - Structures and methods are provided for temporarily bonding handler wafers to device wafers using bonding structures that include one or more releasable layers which are laser-ablatable using mid-wavelength infrared radiation | 02-05-2015 |
Patent application number | Description | Published |
20080252331 | DEVICE FOR DEFEATING REVERSE ENGINEERING OF INTEGRATED CIRCUITS BY OPTICAL MEANS - A method for an electronic device is provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the electronic device. The method emits extraneous randomized light emissions in substantial close proximity to the transistors to hide a pattern of light emissions emitted from the transistors. As one feature, the device can include a source of randomized light emissions in substantial close proximity to the transistors to hide a pattern of the emitted light from the transistors in randomized light emissions emitted by the source. As a second feature, the device can emit the randomized light emissions by randomly delaying an electrical signal that is electrically coupled to the transistors and, in response to the randomly delayed electrical signal, the transistors randomly emitting light emissions thereby hiding a separate pattern of light emission emitted from the transistors. | 10-16-2008 |
20100044724 | DEVICE FOR DEFEATING REVERSE ENGINEERING OF INTEGRATED CIRCUITS BY OPTICAL MEANS - An integrated circuit and method are provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the integrated circuit. The method prevents, in an integrated circuit, a pattern of light emitted from at least one active device in the integrated circuit from being detected external to the integrated circuit by reduction of the intensity of light emitted from the at least one active device in the integrated circuit thereby preventing the reduced intensity light emitted from the at least one active device in the integrated circuit from being detected external to the integrated circuit. The intensity of light emitted from the at least one active device in the integrated circuit can be reduced by modification of operational characteristics of the at least one active device during switching transitions. | 02-25-2010 |
20100044725 | DEVICE FOR DEFEATING REVERSE ENGINEERING OF INTEGRATED CIRCUITS BY OPTICAL MEANS - An integrated circuit and method are provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the integrated circuit. The method prevents, in an integrated circuit, a pattern of light emitted from at least one active device in the integrated circuit from being detected external to the integrated circuit by fading the light emitted from the at least one active device in the integrated circuit and that is emitted external to the integrated circuit. Bright light emission emitted in substantial close proximity to the at least one active device in the integrated circuit, and emitted external to the integrated circuit, fades a pattern of light emission emitted from the at least one active device. | 02-25-2010 |
20100046756 | DEVICE FOR DEFEATING REVERSE ENGINEERING OF INTEGRATED CIRCUITS BY OPTICAL MEANS - An integrated circuit and method are provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the integrated circuit. The method prevents, in an integrated circuit, a pattern of light emitted from at least one active device in the integrated circuit from being detected external to the integrated circuit by randomizing a pattern of light emitted from the at least one active device in an integrated circuit and that is emitted external to the integrated circuit. The pattern of light emitted from the at least one active device in the integrated circuit and that is emitted external to the integrated circuit can be randomized by randomizing a clock signal applied to a clocked circuit comprising the at least one active device in the integrated circuit. | 02-25-2010 |
Patent application number | Description | Published |
20130317315 | METHOD OF AGE MANAGEMENT - A method of age management, by consulting with a patient, performing comprehensive testing on the patient, determining the physiological, functional, and biological age of the patient, and recommending and performing treatments based on the physiological, functional, and biological age of the patient. The performing comprehensive testing is further defined as performing a test of standard plus functional medicine testing, complete hormonal panel, infectious disease panel, tumor markers panel, and combinations thereof. | 11-28-2013 |
20130317484 | METHOD OF LIPOSUCTION - A method of liposuction that results in a smooth skin surface to a patient post procedure, by performing superficial liposuction on the patient by inching and fanning, obtaining an even skin flap, aspirating deep fat, and achieving a smooth contour of skin. SVF extracted from the method above. | 11-28-2013 |
Patent application number | Description | Published |
20090286385 | METHODS FOR REMOVING A PHOTORESIST FROM A METAL-COMPRISING MATERIAL - Methods for removing a photoresist from a metal-comprising material are provided. In accordance with an exemplary embodiment of the present invention, the method comprises applying to the photoresist a substantially non-aqueous-based solvent having a pH no less than about 9 or no pH and subsequently applying to the metal-comprising material an aqueous-based fluid having a pH no less than about 9. | 11-19-2009 |
20090294920 | METHOD FOR FORMING DUAL HIGH-K METAL GATE USING PHOTORESIST MASK AND STRUCTURES THEREOF - Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N | 12-03-2009 |
20100213553 | METAL OXIDE SEMICONDUCTOR DEVICES HAVING BURIED GATE CHANNELS AND METHODS FOR FABRICATING THE SAME - Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a channel layer overlying the semiconductor substrate, forming a channel capping layer having a first surface overlying the channel layer, oxidizing the first surface of the channel capping layer, and depositing a high-k dielectric layer overlying the channel capping layer. | 08-26-2010 |
20100213555 | METAL OXIDE SEMICONDUCTOR DEVICES HAVING CAPPING LAYERS AND METHODS FOR FABRICATING THE SAME - Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a silicon oxide layer overlying the semiconductor substrate, forming a metal oxide gate capping layer overlying the silicon oxide layer, depositing a first metal gate electrode layer overlying the metal oxide gate capping layer, and removing a portion of the first metal gate electrode layer and the metal oxide gate capping layer to form a gate stack. | 08-26-2010 |
20110121436 | METHOD FOR FORMING DUAL HIGH-K METAL GATE USING PHOTORESIST MASK AND STRUCTURES THEREOF - Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N | 05-26-2011 |