Patent application number | Description | Published |
20090113178 | Microprocessor based on event-processing instruction set and event-processing method using the same - Provided are a microprocessor based on event-processing instruction set and an event-processing method using the same. The microprocessor includes an event register controlling an event according to an event-processing instruction set provided in an instruction set architecture (ISA) and an event controller transmitting externally generated events into the microprocessor. Therefore, the microprocessor may be useful to reduce its unnecessary power consumption by suspending the execution of its program when an instruction decoded to execute the program is an event-processing instruction, and also to cut off its unnecessary power consumption that is caused for an interrupt delay period since the program of the microprocessor may be executed again by immediately re-running the microprocessor with the operation of the event register and the event controller when external events are generated. | 04-30-2009 |
20090150706 | WRAPPER CIRCUIT FOR GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS SYSTEM AND METHOD FOR OPERATING THE SAME - Provided are a high-performance wrapper circuit for a globally asynchronous locally synchronous (GALS) system and a synchronization method using the same, which are capable of solving a synchronization problem caused when data are transmitted between locally synchronous modules employing different clocks, and a method for operating the wrapper circuit. The GALS system includes a clock generator for supplying an operation clock to a locally synchronous module, a sender port for transmitting data to the outside according to a data transmission request signal output from the locally synchronous module, and generating a first clock stop signal for stopping an operation of the clock generator, and a receiver port for receiving data from the outside, and generating a second clock stop signal for stopping the operation of the clock generator. The sender port generates the first clock stop signal to the clock generator when a next data transmission request signal is received before completing a data transmission performed by a previous data transmission request signal output from the locally synchronous module. | 06-11-2009 |
20100135430 | DATA TRANSMITTING DEVICE, DATA RECEIVING DEVICE, DATA TRANSMITTING SYSTEM, AND DATA TRANSMITTING METHOD - Provided are a data transmitting device transmitting data through a delay insensitive data transmitting method and a data transmitting method. The data transmitting device and the data transmitting method use the delay insensitive data transmitting method supporting a 2-phase hand shake protocol. During data transmission, data are encoded into three logic state having no space state through a ternary encoding method. According to the data transmitting device and the data transmitting method, data are stably transmitted to a receiver regardless of the length of a wire, and provides more excellent performance in an aspect of a data transmission rate, compared to a related art 4-phase delay data transmitting method. | 06-03-2010 |
20100146364 | METHOD AND APPARATUS FOR ENCODING/DECODING BUS SIGNAL - Provided is a bus signal encoding/decoding method and apparatus. The bus signal encoding method includes receiving a bus signal, XOR-operating all but the first byte sequence of the bus signal in a bitwise manner, inverting the even-numbered byte sequences of the XOR-operated bus signal in a bitwise manner, and serializing the inverted bus signal. | 06-10-2010 |
20120102300 | ASYNCHRONOUS PIPELINE SYSTEM, STAGE, AND DATA TRANSFER MECHANISM - Disclosed are an asynchronous pipeline system, a stage, and a data transfer mechanism. The asynchronous pipeline system having a plurality of stages based on a 4-phase protocol, includes: a first stage among the plurality of stages; and a second stage among the plurality of stages connected next to the first stage, wherein the first stage transmits and the second receives bundled data and control data through an always bundled data channel and on-demand data through an on-demand data channel according to need of the second stage. | 04-26-2012 |
20120166170 | DELAY CIRCUIT, AND DEVICE AND METHOD FOR SIMULATING ASYNCHRONOUS CIRCUIT IN FPGA USING DELAY CIRCUIT - Disclosed herein is an apparatus for simulating an asynchronous circuit in an FPGA. The apparatus includes a plurality of function execution units, a plurality of delay circuits, and a control unit. The function execution units are set for respective unit functions included in the asynchronous circuit, and are configured to perform the unit functions. The delay circuits are provided for the respective function execution units using a look-up table in the FPGA, and are configured to output delayed input signals by delaying input signals by respective preset delay times. The control unit transmits the input signals to the delay circuits and the function execution units, and receives the delayed input signals from the respective delay circuits. | 06-28-2012 |
20130326454 | APPARATUS AND METHOD FOR REDUCING PEAK POWER USING ASYNCHRONOUS CIRCUIT DESIGN TECHNOLOGY - Disclosed herein are an apparatus and method for reducing peak power using an asynchronous circuit design technology. The apparatus includes a combinational circuit unit and an asynchronous control circuit unit. The combinational circuit unit divides a combinational circuit into a plurality of partial circuits based on the depth of input and output. The asynchronous control circuit unit controls the combinational circuit so that the switching operations of the partial circuits are performed in an asynchronous manner according to temporal order and so that a switching operation is not performed in other partial circuits when a switching operation is performed in a partial circuit. | 12-05-2013 |
Patent application number | Description | Published |
20090029520 | METHODS OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device, where the method may include forming a first trench in a semiconductor substrate, forming first device isolation patterns that fill the first trench, forming spacers on sidewalls of the first device isolation patterns, forming a second trench in the semiconductor substrate between first device isolation patterns, and forming second device isolation patterns that fill the second trench. The second trench is formed using an etching process adopting the first device isolation pattern and the spacer as a mask. | 01-29-2009 |
20100295113 | SEMICONDUCTOR DEVICES COMPRISING A PLURALITY OF GATE STRUCTURES - Semiconductor devices including a plurality of gate structures disposed on a semiconductor substrate are provided. Each of the gate structures includes a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, and a mask layer. Liners cover opposing sidewalls of adjacent floating gates. Spacers are disposed on the liners, the spacers protruding from opposing sidewalls of adjacent ones of the gate structures, and a top of each of the spacers is disposed below a top of a corresponding one of the gate structures. The liners define sidewalls of respective air gaps and the spacers define tops of the respective air gaps. | 11-25-2010 |
20110163367 | Semiconductor Devices Comprising a Plurality of Gate Structures - Semiconductor devices are provided. The semiconductor devices may include a plurality of gate structures disposed on a semiconductor substrate, each of the gate structures including a floating gate, an inter-gate dielectric layer, and a control gate. The semiconductor devices may also include liners on opposing sidewalls of adjacent ones of the gate structures. The liners may define a gap. A first width of the gap may be less than a second width of the gap. | 07-07-2011 |
Patent application number | Description | Published |
20090277674 | Printed circuit board and manufacturing method thereof - A printed circuit board and a manufacturing method thereof are disclosed. The method of manufacturing a printed circuit board can include: forming surface roughness on an insulation layer, coating a chemical compound onto the insulation layer that lowers the surface energy of the insulation layer, and forming a circuit pattern by inkjet printing on the insulation layer coated with the chemical compound. Certain embodiments of the invention can be utilized to improve adhesive strength between the insulation layer and the inkjet-printed circuit patterns, suppress spreading in the inkjet-printed circuit patterns to improve resolution, and reduce manufacturing costs by forming the circuits using inkjet printing. | 11-12-2009 |
20090286004 | METHOD OF FORMING PRINTED CIRCUIT PATTERN, FORMING GUIDE FOR PATTERN, AND GUIDE-FORMING INK - Disclosed are methods of forming a printed circuit pattern and forming a guide, and a guide-forming ink. The method of forming a printed circuit pattern in accordance with the present invention includes forming a guide by using guide-forming ink having a slip property, curing the formed guide by in-situ UV, and forming a printed circuit pattern on the inside of the cured guide by using metal ink. | 11-19-2009 |
20100053264 | INKJET PRINTER AND PRINTING METHOD USING THE SAME - An inkjet printer and a printing method using the inkjet printer are disclosed. The inkjet printer in accordance with an embodiment of the present invention can include: a first inkjet head, which prints in one direction; and a second inkjet head, which prints in a different direction intersecting the one direction. In accordance with an embodiment of the present invention, the inkjet printer can print a pattern having a plurality of directions with a stable printing quality. | 03-04-2010 |
20120024573 | Printed circuit board and manufacturing method thereof - There are provided a printed circuit board and a manufacturing method thereof. The manufacturing method of a printed circuit board includes: preparing a substrate having active regions and non-active regions, the non-active regions being formed on edges thereof; printing resists on dummy portions corresponding to the non-active regions of the substrate by using an inkjet printing method; curing the resists; and performing plating on the active regions of the substrate. The resists are masked on the dummy portions corresponding to the non-active regions of the substrate to prevent plating from being performed on the dummy portions, thereby reducing manufacturing costs. | 02-02-2012 |
20120113181 | Resist ink printing device - There is provided a resist ink printing device according to an exemplary embodiment of the present invention including: a transfer unit transferring a substrate on which lead-in wires for electrolytic gold plating are patterned into a main body; a controller formed on the main body to measure a warpage degree of the substrate and recognizing a gerber file stored with circuit diagram information of the substrate to compensate for the warpage degree of the substrate and correct the gerber file; and at least one inkjet printing head part discharging liquid photo resist ink to the lead-in wires by the corrected gerber file. | 05-10-2012 |
Patent application number | Description | Published |
20080207934 | METHOD FOR PRODUCING METAL NANOPARTICLES AND METAL NANOPARTICLES PRODUCED THEREBY - The present invention relates to a method for producing metal nanoparticles and metal nanoparticles produced thereby, in particular, to a method for producing metal nanoparticles used for inkjet that comprises, preparing metal nanoparticles capped with a fatty acid; heating a mixture of the capped metal nanoparticles and a linear or branched first amine of C1-C7 so that a part of the fatty acid is substituted to the first amine; and heating after adding a linear or branched second amine of C | 08-28-2008 |
20140186593 | RESIN COMPOSITION FOR PRINTED CIRCUIT BOARD, INSULATING FILM, PREPREG, AND PRINTED CIRCUIT BOARD - Disclosed herein are a resin composition for a printed circuit board, an insulating film, a prepreg, and a printed circuit board, the resin composition including: a composite epoxy resin containing a bisphenol A type epoxy resin, a cresol novolac epoxy resin, a rubber-modified epoxy resin, a phosphorus based epoxy resin, and an alkyl sulfonated tetrazole-modified epoxy resin; and a curing agent. The insulating film and the prepreg according to the present invention may have basically low coefficient of thermal expansion, excellent heat resistance, a high glass transition temperature, and excellent adhesion force with the metal. | 07-03-2014 |
20140187677 | SURFACE MODIFIED SILICA BY ALKYL SULFONATED TETRAZOLE COMPOUND, PREPARING METHOD THEREOF, AND RESIN COMPOSITION CONTAINING THE SAME - This invention relates to a surface modified silica by an alkyl sulfonated tetrazole compound, a preparation method thereof, and a resin composition containing the same. The silica according to this invention can exhibit superior adhesion to a metal. | 07-03-2014 |