Patent application number | Description | Published |
20090296791 | Multi-Pair Gigabit Ethernet Transceiver - Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized. | 12-03-2009 |
20100135371 | DYNAMIC REGULATION OF POWER CONSUMPTION OF A HIGH-SPEED COMMUNICATION SYSTEM - A method for dynamically regulating the power consumption of a high-speed integrated circuit which includes a multiplicity of processing blocks. A first metric and a second metric, which are respectively related to a first performance parameter and a second performance parameter of the integrated circuit, are defined. The first metric is set at a pre-defined value. Selected blocks of the multiplicity of processing blocks are disabled in accordance with a set of pre-determined patterns. The second metric is evaluated, while the disabling operation is being performed, to generate a range of values of the second metric. Each of the values corresponds to the pre-defined value of the first metric. A most desirable value of the second metric is determined from the range of values and is matched to a corresponding pre-determined pattern. The integrated circuit is subsequently operated with selected processing blocks disabled in accordance with the matching pre-determined pattern. | 06-03-2010 |
20100309963 | MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER HAVING ADAPTIVE DISABLING OF CIRCUIT ELEMENTS - Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized. | 12-09-2010 |
20110064123 | MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER - Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized. | 03-17-2011 |
20110096824 | MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER HAVING A SINGLE-STATE DECISION FEEDBACK EQUALIZER - Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized. | 04-28-2011 |
Patent application number | Description | Published |
20100149006 | ETHERNET SYSTEM - Four (4) unshielded twisted pairs of wires connect a hub and a computer in an Ethernet system: one (1) pair for transmission only, another for reception only and the other two (2) for transmission and reception. The signals in the wires are in packets each having timing signals defining a preamble and thereafter having digital signals representing information as by individual ones of three (3) amplitude levels. The signals received at the computer are provided with an automatic gain control (AGC) and then with digital conversions at a particular rate. A control loop operative upon the digital conversions regulates the AGC gain at a particular value. An equalizer operative only during the occurrence of the digital signals in each packet selects an individual one of the three (3) amplitude levels closest to the amplitude of each digital conversion at the time assumed to constitute the conversion peak. The amplitudes of the timing signals in each preamble at the times assumed to constitute the peaks and zero crossings of such signals are multiplied. The rate of such digital conversions is adjusted in accordance with the polarity and magnitude of the multiplication product. The relative amplitudes of the successive equalizer values following each preamble are evaluated at the times assumed to be the peaks of the digital conversions. The rate of the digital conversions is adjusted in accordance with such evaluations, thereby further regulating the digital conversions at the particular rate. The equalizer thus operates on the information signals in each packet at the signal peaks. | 06-17-2010 |
20110026423 | Robust Techniques for Upstream Communication Between Subscriber Stations and a Base Station - A number of features for enhancing the performance of a communication system, in which data is transmitted between a base station and a plurality of subscriber stations located different distances from the base station, are presented. The power transmission level, slot timing, and equalization of the subscriber stations are set by a ranging process. Data is transmitted by the subscriber stations in fragmented form. Various measures are taken to make transmission from the subscriber stations robust. The uplink data transmission is controlled to permit multiple access from the subscriber stations. | 02-03-2011 |
20110176789 | SYSTEM AND METHOD IN A PROGRAM RECORDER FOR MANAGING ADVERTISEMENT PRESENTATION - A system and method for managing advertisement presentation in user equipment, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. | 07-21-2011 |
20110178853 | SYSTEM AND METHOD FOR UPDATING ADVERTISING CONTENT FOR A RECORDED PROGRAM - A system and method for updating advertising content for a recorded program (e.g., recorded on personal video recorder equipment), substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. | 07-21-2011 |
20110178876 | SYSTEM AND METHOD FOR PROVIDING VIEWER IDENTIFICATION-BASED ADVERTISING - A system and method for providing viewer identification-based advertising, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. | 07-21-2011 |
20110178880 | SYSTEM AND METHOD FOR MONITORING AND REPORTING PRESENTATION OF RECORDED ADVERTISING CONTENT - A system and method for monitoring and reporting presentation of recorded advertising content, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. | 07-21-2011 |
20110179446 | SYSTEM AND METHOD FOR COMMUNICATING PROGRAMMING AND ADVERTISING CONTENT THROUGH DIVERSE COMMUNICATION NETWORKS - A system and method for communicating programming and advertising content through diverse communication networks, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. | 07-21-2011 |
20110179448 | SYSTEM AND METHOD FOR PROVIDING USER SPECIFICATION OF ADVERTISING CONTENT - A system and method for providing user specification of advertising content, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. | 07-21-2011 |
20130294377 | Robust Techniques for Upstream Communication Between Subscriber Stations and a Base Station - A number of features for enhancing the performance of a communication system, in which data is transmitted between a base station and a plurality of subscriber stations located different distances from the base station, are presented. The power transmission level, slot timing, and equalization of the subscriber stations are set by a ranging process. Data is transmitted by the subscriber stations in fragmented form. Various measures are taken to make transmission from the subscriber stations robust. The uplink data transmission is controlled to permit multiple access from the subscriber stations. | 11-07-2013 |