Hsu, Chiayi County
Chang-Shuen Hsu, Chiayi County TW
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20160023791 | Sealing Device for Automatic Bagging Machine - A sealing device for an automatic bagging machine contains: a film sealing assembly including a first seal, a second seal mount opposite to the first seal mount; a slide assembly including an elongated plate, a rail arranged on the elongated plate, and a sliding piece fixed on the rail; a cutting module including a cylinder seat, a mounting sheet, four screwing elements, a driving cylinder, and a roller. The cylinder seat is mounted on one side surface of the sliding piece, and the driving cylinder and the roller are inserted through the second seal mount. Between the cylinder seat and the mounting sheet are defined a central shaft and two gaps on two sides of the central shaft. In addition, at least two springs are arranged between the cylinder seat and the mounting sheet and are fitted on the four screwing elements. | 01-28-2016 |
Chia-Chen Hsu, Chiayi County TW
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20120251035 | CIRCULAR PHOTONIC CRYSTAL STRUCTURE, LIGHT EMITTING DIODE DEVICE AND PHOTOELECTRIC CONVERSION DEVICE - A method applying a circular photonic crystal structure to improve optical properties of a photoelectric conversion device such as a light emitting diode device, an organic light emitting diode device or a solar cell is provided, wherein the circular photonic crystal structure is configured on a junction surface between two different mediums where passes a light emitted or received by the photoelectric conversion device. The circular photonic crystal structure provides isotropic photonic band gap which conduces high light extraction efficiency. | 10-04-2012 |
20130312822 | SOLAR-CELL DEVICE - The disclosure provides a solar-cell device, including a substrate, a first electrode layer comprising a first two-dimensional periodic structure disposed on the substrate, a first light conversion layer disposed on the first two-dimensional periodic structure, a second light conversion layer disposed on the first light conversion layer; and a second electrode layer disposed on the second light conversion layer. | 11-28-2013 |
Hsin-Yu Hsu, Chiayi County TW
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20100055857 | METHOD OF FORMING A POWER DEVICE - A method of forming a power device includes providing a substrate, a semiconductor layer having at least a trench and being disposed on the substrate, a gate insulating layer covering the semiconductor layer, and a conductive material disposed in the trench, performing an ion implantation process to from a body layer, performing a tilted ion implantation process to from a heavy doped region, forming a first dielectric layer overall, performing a chemical mechanical polishing process until the body layer disposed under the heavy doped region is exposed to form source regions on the opposite sides of the trench, and forming a source trace directly covering the source regions disposed on the opposite sides of the trench. | 03-04-2010 |
20100117142 | Semiconductor Device for Improving the Peak Induced Voltage in Switching Converter - A power semiconductor device includes a backside metal layer, a substrate formed on the backside metal layer, a semiconductor layer formed on the substrate, and a frontside metal layer. The semiconductor layer includes a first trench structure including a gate oxide layer formed around a first trench with poly-Si implant, a second trench structure including a gate oxide layer formed around a second trench with poly-Si implant, a p-base region formed between the first trench structure and the second trench structure, a plurality of n+ source region formed on the p-base region and between the first trench structure and the second trench structure, a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source region. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source region on the p-base region. | 05-13-2010 |
20100117164 | SEMICONDUCTOR DEVICE WITH A LOW JFET REGION RESISTANCE - A high-voltage MOS transistor device includes a substrate, a semiconductor layer formed on the substrate, a gate structure having an opening, formed on the semiconductor layer, a first source/drain region of a first conductivity type formed in the semiconductor layer at one side of the gate structure, a second source/drain region of the first conductivity type formed in the semiconductor layer at the other side of the gate structure, a channel region disposed by a dopant of the first conductivity type between the first source/drain region and the second source/drain region, and a doping region of the first conductivity type formed in the channel region and under the opening of the gate structure, wherein a doping concentration of the doping region is higher than a doping concentration of the channel region. | 05-13-2010 |
20100285646 | Method of fabricating power semiconductor device - Wider and narrower trenches are formed in a substrate. A first gate material layer is deposited but not fully fills the wider trench. The first gate material layer in the wider trench and above the substrate original surface is removed by isotropic or anisotropic etching back. A first dopant layer is formed in the surface layer of the substrate at the original surface and the sidewall and bottom of the wider trench by tilt ion implantation. A second gate material layer is deposited to fully fill the trenches. The gate material layer above the original surface is removed by anisotropic etching back. A second dopant layer is formed in the surface layer of the substrate at the original surface by ion implantation. The dopants are driven-in to form a base in the substrate and a bottom-lightly-doped layer surrounding the bottom of the wider trench and adjacent to the base. | 11-11-2010 |
20100289075 | SEMICONDUCTOR DEVICE HAVING INTEGRATED MOSFET AND SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF - A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer. | 11-18-2010 |
Liang-Kuei Hsu, Chiayi County TW
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20080226015 | PULSE EXTENSION CIRCUITS FOR EXTENDING PULSE SIGNALS - A pulse extension circuit for extending a pulse signal includes an input unit for receiving the pulse signal, an edge detection unit coupled to the input unit for generating a initiation signal, a pulse initiation unit coupled to the edge detection unit for outputting a control signal and adjusting a voltage level of the control signal, a pulse width control unit coupled to the pulse initiation unit for outputting a termination signal, a reset unit coupled to the edge detection unit, the pulse initiation unit and the pulse width control unit for outputting the first reset signal and the second reset signal to reset the pulse initiation unit and the pulse width control unit, and an output unit coupled to the input unit and the pulse initiation unit for extending a signal period of the pulse signal according to the pulse signal and the control signal. | 09-18-2008 |
Tien-Ken Hsu, Chiayi County TW
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20110052553 | STRAIN OF LACTOBACILLUS PLANTARUM LP28 AND ITS USE IN TREATING HYPERSENSITIVITY REACTIONS - A new strain of | 03-03-2011 |
Tzu Hsuan Hsu, Chiayi County TW
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20090296474 | PROGRAM AND ERASE METHODS WITH SUBSTRATE TRANSIENT HOT CARRIER INJECTIONS IN A NON-VOLATILE MEMORY - The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. the programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure. | 12-03-2009 |
20110116317 | PROGRAM AND ERASE METHODS WITH SUBSTRATE TRANSIENT HOT CARRIER INJECTIONS IN A NON-VOLATILE MEMORY - The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. the programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure. | 05-19-2011 |
20150372001 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes a first electrode layer, a second electrode layer and a dielectric layer between the first electrode layer and the second electrode layer. A width of the second electrode layer becomes larger in a direction away from the dielectric layer. | 12-24-2015 |
Wei-Ting Hsu, Chiayi County TW
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20130102089 | Method For Processing A Sensor Chip - The method for processing a sensor chip in accordance with the present invention has: 1) providing an acoustic wave operation system and a biochemical sensor chip, wherein the acoustic wave operation system has a piezoelectric transducer generating at least one cycle of longitudinal acoustic waves by a driving voltage and wherein a probe is immobilized on a surface of the biochemical sensor chip; 2) arranging the piezoelectric transducer at a distance from the biochemical sensor chip and filling therebetween with a medium for transmitting longitudinal acoustic waves; and 3) applying longitudinal acoustic waves to the biochemical sensor chip to remove an adsorbate bound to the probe. | 04-25-2013 |