Patent application number | Description | Published |
20090127666 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND PHASE SHIFT MASK - A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in āLā shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance. | 05-21-2009 |
20090294902 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, an insulating film formed over the substrate, first and second conductive plugs formed in the insulating film, a capacitor element, and a wiring. The capacitor element includes a lower electrode, a dielectric film, and an upper electrode. The lower electrode is connected to an end of the first plug and formed on the insulating film, and includes a first barrier film. The dielectric film is formed on upper and side surfaces of the lower electrode. The upper electrode is formed on the dielectric film, and includes a second barrier metal film being wider than the lower electrode. The wiring is connected to an end of the second plug and formed on the insulating film, and includes a first layer and a second layer formed on the first layer. The first and second layers include the first and second barrier metal films, respectively. | 12-03-2009 |
20090294905 | Semiconductor device - A substrate is provided with a first wiring layer | 12-03-2009 |
20090294988 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a pad forming region electrically connecting an element forming region to the outside, in which a low dielectric constant insulating film is formed in association with in the element forming region, a Cu film serving as a via formed in the low dielectric constant insulating film in the pad forming region is disposed in higher density than that of a Cu film serving as a via in the element forming region. Hereby, when an internal stress occurs, the stress is prevented from disproportionately concentrating on the via, and deterioration of a function of a wiring caused thereby can be avoided. | 12-03-2009 |
20100006984 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate; a layered body formed on the substrate and including a multilayer interconnection structure, the layered body including multiple interlayer insulating films stacked in layers, the interlayer insulating films being lower in dielectric constant than a SiO | 01-14-2010 |
20100130004 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a pad forming region electrically connecting an element forming region to the outside, in which a low dielectric constant insulating film is formed in association with in the element forming region, a Cu film serving as a via formed in the low dielectric constant insulating film in the pad forming region is disposed in higher density than that of a Cu film serving as a via in the element forming region. Hereby, when an internal stress occurs, the stress is prevented from disproportionately concentrating on the via, and deterioration of a function of a wiring caused thereby can be avoided. | 05-27-2010 |
20100240211 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND PHASE SHIFT MASK - A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, includes the step of selectively forming a sub-wall part including metal films between the integrated circuit part and the main wall part, in parallel to formation of the integrated circuit part and the main wall part. A sub-wall part which is in an āLā shape is provided between each corner of the main wall part and the integrated circuit part of the resulting semiconductor device. | 09-23-2010 |
20110001248 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 01-06-2011 |
20110115091 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 05-19-2011 |
20110121460 | SEMICONDUCTOR DEVICE HAVING A MULTILAYER INTERCONNECTION STRUCTURE - A semiconductor device has a multilayer interconnection structure, wherein the multilayer interconnection structure comprises at least a first interconnection layer and a second interconnection layer formed over the first interconnection layer, the first interconnection layer comprises a first conductor pattern embedded in a first interlayer insulation film and constituting a part of an interconnection pattern and a second, another interconnection pattern embedded in the first interlayer insulation film, the second interconnection layer comprises a third conductor pattern embedded in a second interlayer insulation film and constituting a part of said interconnection pattern, the third conductor pattern has an extension part in a part thereof so as to extend in a layer identical to the third conductor pattern, the third conductor pattern being electrically connected to the first conductor pattern at a first region of the extension part via a first via plug, the extension part making a contact with the second conductor pattern at a second region further away from, or closer to the third conductor pattern with regard to the first region via a second via-plug of a diameter smaller than the first via-plug, the extension part of the third conductor pattern, the first via-plug and the second via-plug form, together with the second interlayer insulation film, a dual damascene structure. | 05-26-2011 |
20110177672 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO | 07-21-2011 |
20120086105 | SEMICONDUCTOR DEVICE HAVING CAPACITOR CAPABLE OF REDUCING ADDITIONAL PROCESSES AND ITS MANUFACTURE METHOD - A first capacitor recess and a wiring trench are formed through an interlayer insulating film. A lower electrode fills the first capacitor recess, and a first wiring fills the wiring trench. An etching stopper film and a via layer insulating film are disposed over the interlayer insulating film. A first via hole extends through the via layer insulating film and etching stopper film and reaches the first wiring, and a first plug fills the first via hole. A second capacitor recess is formed through the via layer insulating film, the second capacitor recess at least partially overlapping the lower electrode, as viewed in plan. The upper electrode covers the bottom and side surfaces of the second capacitor recess. A capacitor is constituted of the upper electrode, etching stopper film and lower electrode. A second wring connected to the first plug is formed over the via layer insulating film. | 04-12-2012 |
20120149190 | SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO | 06-14-2012 |
20120175736 | SEMICONDUCTOR DEVICE - A substrate is provided with a first wiring layer | 07-12-2012 |
20120190154 | SEMICONDUCTOR DEVICE INCLUDING CAPACITOR ELEMENT AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, an insulating film formed over the substrate, first and second conductive plugs formed in the insulating film, a capacitor element, and a wiring. The capacitor element includes a lower electrode, a dielectric film, and an upper electrode. The lower electrode is connected to an end of the first plug and formed on the insulating film, and includes a first barrier film. The dielectric film is formed on upper and side surfaces of the lower electrode. The upper electrode is formed on the dielectric film, and includes a second barrier metal film being wider than the lower electrode. The wiring is connected to an end of the second plug and formed on the insulating film, and includes a first layer and a second layer formed on the first layer. The first and second layers include the first and second barrier metal films, respectively. | 07-26-2012 |
20120248572 | SEMICONDUCTOR DEVICE HAVING CAPACITOR CAPABLE OF REDUCING ADDITIONAL PROCESSES AND ITS MANUFACTURE METHOD - A first capacitor recess and a wiring trench are formed through an interlayer insulating film. A lower electrode fills the first capacitor recess, and a first wiring fills the wiring trench. An etching stopper film and a via layer insulating film are disposed over the interlayer insulating film. A first via hole extends through the via layer insulating film and etching stopper film and reaches the first wiring, and a first plug fills the first via hole. A second capacitor recess is formed through the via layer insulating film, the second capacitor recess at least partially overlapping the lower electrode, as viewed in plan. The upper electrode covers the bottom and side surfaces of the second capacitor recess. A capacitor is constituted of the upper electrode, etching stopper film and lower electrode. A second wring connected to the first plug is formed over the via layer insulating film. | 10-04-2012 |
20120252181 | SEMICONDUCTOR DEVICE HAVING CAPACITOR CAPABLE OF REDUCING ADDITIONAL PROCESSES AND ITS MANUFACTURE METHOD - A first capacitor recess and a wiring trench are formed through an interlayer insulating film. A lower electrode fills the first capacitor recess, and a first wiring fills the wiring trench. An etching stopper film and a via layer insulating film are disposed over the interlayer insulating film. A first via hole extends through the via layer insulating film and etching stopper film and reaches the first wiring, and a first plug fills the first via hole. A second capacitor recess is formed through the via layer insulating film, the second capacitor recess at least partially overlapping the lower electrode, as viewed in plan. The upper electrode covers the bottom and side surfaces of the second capacitor recess. A capacitor is constituted of the upper electrode, etching stopper film and lower electrode. A second wring connected to the first plug is formed over the via layer insulating film. | 10-04-2012 |
20120261833 | SEMICONDUCTOR DEVICE HAVING A MULTILAYER INTERCONNECTION STRUCTURE - A semiconductor device includes first and second conductor patterns embedded in a first interlayer insulation film and a third conductor pattern embedded in a second interlayer insulation film, the third conductor pattern including a main part and an extension part, the extension part being electrically connected to the first conductor pattern by a first via-plug, the extension part having a branched pattern closer to the main part compared with the first conductor pattern, the branched pattern making a contact with the second conductor pattern via a second via-plug, each of the main part, extension part including the branched pattern, first via-plug and second via-plug forming a damascene structure. | 10-18-2012 |
20120273953 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 11-01-2012 |
20120273956 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 11-01-2012 |
20120273969 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 11-01-2012 |
20120280396 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 11-08-2012 |
20120319281 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 12-20-2012 |
20130011995 | SEMICONDUCTOR DEVICE HAVING WIRING MADE BY DAMASCENE METHOD AND CAPACITOR AND ITS MANUFACTURE METHOD - A wiring trench is formed in an interlayer insulating film partway in the depth direction of the interlayer insulating film. A via hole is formed extending from the bottom of the wiring trench to the bottom of the interlayer insulating film. A capacitor recess is formed reaching the bottom of the interlayer insulating film. A conductive member is embedded in the wiring trench and via hole. A capacitor is embedded in the capacitor recess, including a lower electrode, a capacitor dielectric film and an upper electrode. The lower electrode is made of the same material as that of the conductive member and disposed along the bottom and side surface of the capacitor recess. A concave portion is formed on an upper surface of the lower electrode, and the capacitor dielectric film covers an inner surface of the concave portion. The upper electrode is embedded in the concave portion. | 01-10-2013 |
20130109177 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD | 05-02-2013 |
20130168799 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 07-04-2013 |
20130168865 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 07-04-2013 |
20130175691 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 07-11-2013 |
20130175692 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 07-11-2013 |
20130200481 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 08-08-2013 |
20140312507 | SEMICONDUCTOR DEVICE HAVING A MULTILAYER INTERCONNECTION STRUCTURE - A semiconductor device includes first and second conductor patterns embedded in a first interlayer insulation film and a third conductor pattern embedded in a second interlayer insulation film, the third conductor pattern including a main part and an extension part, the extension part being electrically connected to the first conductor pattern by a first via-plug, the extension part having a branched pattern closer to the main part compared with the first conductor pattern, the branched pattern making a contact with the second conductor pattern via a second via-plug, each of the main part, extension part including the branched pattern, first via-plug and second via-plug forming a damascene structure. | 10-23-2014 |