Patent application number | Description | Published |
20150331625 | MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks, and a controller controlling the nonvolatile memory. The controller cyclically executes patrol read, the patrol read including reading data and testing the read data, the read data being data of pages connected to some of word lines in each of the blocks of the nonvolatile memory. | 11-19-2015 |
20150332758 | MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM - According to an embodiment, a controller performs a coding process based on a first frame including data of a plurality of pages connected to first word lines being a predetermined number of consecutive word lines in a block, and performs, when padding data is written to a plurality of pages connected to second word lines being the predetermined number of word lines subsequent to the first word lines, the coding process based on a second frame obtained by excluding the padding data from a frame including data of the pages connected to the second word lines. | 11-19-2015 |
20150339069 | MEMORY SYSTEM AND METHOD - According to one embodiment, a memory system includes a first memory, a second memory, and a processor. The second memory stores first management information and second management information. The first management information has an information that associates a logical address with a physical address. The second management information has an information which has a volume of valid data in each block included in the first memory. The controller updates the first management information and the second management information. When saving a differential data in the first memory, the controller stores the differential data and the second management information in one page of the first memory. The differential data is a difference between before and after update of the first management information. When restoring the second management information, the controller loads to the second memory the second management information stored in the first memory. | 11-26-2015 |
20150339223 | MEMORY SYSTEM AND METHOD - According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a plurality of parallel operation elements each having a plurality of physical blocks. The controller drives the plurality of parallel operation elements in parallel. The controller associates each of a plurality of logical blocks with a plurality of physical blocks each belonging to different parallel operation elements. The controller levels, among the plurality of logical blocks, the numbers of Bad blocks included in the plurality of physical blocks being associated with each of the plurality of logical blocks. | 11-26-2015 |
Patent application number | Description | Published |
20130227246 | MANAGEMENT INFORMATION GENERATING METHOD, LOGICAL BLOCK CONSTRUCTING METHOD, AND SEMICONDUCTOR MEMORY DEVICE - A management information generating method wherein logical and physical block addresses (BAs) of continuous addresses are associated with each other in the BA translation table. When a logical block is constructed, an allowable value is set for the number of defective physical blocks. A logical block having fewer defects than the set number is set usable, and a logical block having more defects than the set number is set unusable. System logical block construction is performed to preferentially select physical blocks from a plane list including a large number of usable blocks to equalize the number of usable blocks in each plane list. It is determined whether the number of free blocks is insufficient on the basis of a first management unit and whether the storage area for the indicated capacity can be reserved on the basis of the management unit different from the first unit. | 08-29-2013 |
20130232296 | MEMORY SYSTEM AND CONTROL METHOD OF MEMORY SYSTEM - A memory system in embodiments includes a nonvolatile semiconductor memory that stores user data, a forward lookup address translation table and a reverse lookup address translation table, and a controller. The controller is configured to determine that the user data stored in the nonvolatile semiconductor memory is valid or invalid based on these two tables. The controller may perform data organizing of selecting data determined valid and rewriting the data in a new block. The controller may perform write processing and rewriting processing to the new block alternately at a predetermined ratio. The controller may determine whether a predetermined condition is satisfied on a basis of addresses included in write requests and write data in the MLC mode when the condition is satisfied and write data in the SLC mode when the condition is not satisfied. | 09-05-2013 |
20130246689 | MEMORY SYSTEM, DATA MANAGEMENT METHOD, AND COMPUTER - According to one embodiment, a memory system includes a non-volatile memory, a volatile memory, a controller, and a compression/decompression processor. When data transmission is performed through the volatile memory between a host apparatus and the non-volatile memory, the controller updates management information stored in the volatile memory. In addition, the compression/decompression processor compresses the management information in the case where a first condition is satisfied, and decompresses the compressed management information in the case where a second condition is satisfied. The controller stores the compressed management information in the non-volatile memory. | 09-19-2013 |
Patent application number | Description | Published |
20090241010 | MEMORY SYSTEM - A memory system includes a controller that manages data stored in the first and second storing areas. The controller determines, when a readout error occurs when the stored data in the second storing area is read out, success or failure of error correction to the read-out data based on the result of the error correction stored in a storage buffer, writes, when the error correction is successful, correction data corresponding to the read-out data stored in the storage buffer, and writes, when the error correction fails, the read-out data itself not subjected to error correction processing. | 09-24-2009 |
20110231734 | MEMORY SYSTEM - A memory system includes a controlling unit that configured to control data transfer between the first and the second memory. The controlling unit executes copy processing for, after reading out data stored in a first page of the second memory to the first memory, writing the data in a second page of the second memory, determines, when executing the copy processing, whether the error correction processing for the data read out from the first page is successful, stores, when the error correction processing is successful, corrected data in the first memory and writes the corrected data in the second page, and reads out, when the error correction processing is unsuccessful, the data from the first page to the first memory and writes the data not subjected to the error correction processing in the second page. | 09-22-2011 |
20140237320 | MEMORY SYSTEM - A memory system includes a controlling unit that configured to control data transfer between the first and the second memory. The controlling unit executes copy processing for, after reading out data stored in a first page of the second memory to the first memory, writing the data in a second page of the second memory, determines, when executing the copy processing, whether the error correction processing for the data read out from the first page is successful, stores, when the error correction processing is successful, corrected data in the first memory and writes the corrected data in the second page, and reads out, when the error correction processing is unsuccessful, the data from the first page to the first memory and writes the data not subjected to the error correction processing in the second page. | 08-21-2014 |
Patent application number | Description | Published |
20120313172 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, AND METHODS OF MANUFACTURING THE SAME - This invention is to provide a semiconductor device having a reduced variation in the transistor characteristics. The semiconductor device has a SOI substrate, a first element isolation insulating layer, first and second conductivity type transistors, and first and second back gate contacts. The SOI substrate has a semiconductor substrate having first and second conductivity type layers, an insulating layer, and a semiconductor layer. The first element isolation insulating layer is buried in the SOI substrate, has a lower end reaching the first conductivity type layer, and isolates a first element region from a second element region. The first and second conductivity type transistors are located in the first and second element regions, respectively, and have respective channel regions formed in the semiconductor layer. The first and second back gate contacts are coupled to the second conductivity type layers in the first and second element regions, respectively. | 12-13-2012 |
20130077379 | SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - In a case where a DRAM and a ReRAM are mounted together, a manufacturing cost thereof is reduced while maintaining performance of a capacitance element and a variable resistance element. A semiconductor memory device includes a variable resistance element and a capacitance element. The variable resistance element has a cylinder type MIM structure with a first depth, and is designed for a variable resistance type memory. The capacitance element has a cylinder type MIM structure with a second depth deeper than the first depth, and is designed for a DRAM. | 03-28-2013 |
Patent application number | Description | Published |
20140072025 | TRANSMISSION APPARATUS AND COMMUNICATION SYSTEM - A transmission apparatus includes a transmission equalizer that equalizes a transmission signal transmitted in a signal transmission performed via a non-contact coupling including a magnetic coupling of a pair of coupling elements. The transmission equalizer creates plural equivalent transmission signals by branching the transmission signal; and includes plural signal paths that respectively give time delays different from each other to the equivalent transmission signals, and respectively multiplies the delayed transmission signals by tap coefficients. In addition, at least one pair of signal paths is set includes a variable delay circuit that can change the corresponding time delay to be given to the corresponding transmission signal. | 03-13-2014 |
20140073243 | WIRELESS COMMUNICATION SYSTEM AND WIRELESS COMMUNICATION APPARATUS - A first communication device includes a first coupling element and a second communication device includes a second coupling element. The first and second communication devices are configured to wirelessly transmit, between the first and second communication devices, a differential-mode signal and a common-mode signal simultaneously through non-contact coupling between the first and second coupling elements. | 03-13-2014 |
20150156040 | TRANSMISSION APPARATUS AND COMMUNICATION SYSTEM - A communication device includes a transmission equalizer that equalizes a transmission signal transmitted in a signal transmission performed via a non-contact coupling, the transmission equalizer creates a plurality of equivalent transmission signals by branching the transmission signal. The transmission equalizer includes a plurality of signal paths that respectively provide time delays different from each other to the equivalent transmission signals, and an output path that provides a filter output based on the total sum of outputs of the signal paths to the non-contact coupling, and at least one of the plurality of signal paths includes a variable delay circuit that can change a time delay to be given to the corresponding transmission signal. | 06-04-2015 |
Patent application number | Description | Published |
20140177739 | TRANSMISSION DEVICE AND NODE FOR THE SAME - Nodes are connected in parallel between two transmission lines and configured to utilize a telecommunications standard of a differential transmission. At least one of the nodes includes two input/output terminals, a driver, a receiver, a resistor, and a comparator. The two input/output terminals are connected to the two transmission lines. The driver includes two output terminals connected to the two input/output terminals. The receiver includes two input terminals connected to the two input/output terminals. The resistor is connected between each of the two input/output terminals and one of a grand and a power supply voltage. The comparator compares a voltage between the transmission lines with a reference voltage to determine whether the transmission lines are in an idle state or in a communication state. | 06-26-2014 |
20150333937 | DECISION FEEDBACK EQUALIZER - In a decision feedback equalizer, at least one of weighting devices that has a tap coefficient an absolute value of which is relatively larger than absolute values of tap coefficients of other weighting devices is referred to as a main weighting device, and delay elements are disposed asymmetrically on signal processing paths or updating paths of the to coefficients of the weighting devices in such a manner that an updating interval of the tap coefficient of the main weighting device is shorter than updating intervals of the tap coefficients of the other weighting devices. | 11-19-2015 |
20160036606 | WAVEFORM EQUALIZATION APPARATUS - A waveform equalization apparatus includes an A/D converter, a waveform equalizer, a training sequence generator, a clock recovery circuit, multiple matched filters, and a clock optimization logic. The A/D converter oversamples a reception signal in synchronization with a base clock signal and generates an A/D converted data sequence. The waveform equalizer performs an arithmetic operation to equalize a waveform. The training sequence generator generates a data sequence for training. The data sequence for training is used instead of an output data of the detector so as to converge a coefficient used in the arithmetic operation in advance. The clock recovery circuit supplies the base clock signal without executing a clock recovery operation during a training period, and executes the clock recovery operation according to the output data of the detector. The matched filters receive the A/D converted data sequence, and execute a filter arithmetic operation. | 02-04-2016 |
Patent application number | Description | Published |
20150063514 | DATA RECEPTION APPARATUS AND DATA COMMUNICATION SYSTEM - A data reception apparatus obtains an integrated number of bits by integrating the numbers of bits of a bit string, obtains an integrated number of samples by integrating the number of samples obtained by oversampling each bit, obtains an approximated line that indicates correspondence between the integrated number of bits and the integrated number of samples, determines, based on the approximated line, a bit length of a bit string corresponding to a segment in which identical values continue in oversampling data after the integrated number of samples. Even when a receive-side clock source has a degree of clock frequency error against a transmit-side clock source, how many samples one bit of the bit string corresponds to is obtained with an accuracy higher than a period of oversampling (inverse of the number of samples). | 03-05-2015 |
20150220471 | COMMUNICATION SYSTEM - A communication system includes a communication wiring, at least one master node connected to the communication wiring, and at least one slave node connected to the communication wiring. The at least one master node and the at least one slave node are connected in a ring shape through the communication wiring and communicate in a start-stop synchronous communication. | 08-06-2015 |
20150222455 | COMMUNICATION SYSTEM - A communication system including multiple communication nodes is provided. Each of the multiple communication nodes includes a low speed communication transceiver that is directly connected to a differential communication channel, and a high speed communication transceiver that is AC coupled to the differential channel. The multiple communication nodes include a sending communication node. The sending communication node sends a command to switch from the low speed communication to a high speed communication when the sending communication node performs a low speed communication using the low speed communication transceiver. The sending communication node initiates the high speed communication using the high speed communication transceiver. | 08-06-2015 |
20150244420 | COMMUNICATION SYSTEM, COMMUNICATION SLAVE AND COMMUNICATION MASTER - A communication system includes multiple communication nodes and a communication line. The multiple communication nodes include a master and multiple slaves. The communication line cascade-connects the communication nodes and supplies electricity. The communication line corresponds to a feeder line. Each of the communication nodes is connected with the communication line through an inductor to be supplied with electricity. The each of the communication nodes is AC coupled to the communication line to transmit and receive a communication signal. The master and the slaves perform a bidirectional communication. A communication slave is provided. The communication slave is connected with a communication line through an inductor to be supplied with electricity. A communication master is provided. | 08-27-2015 |
Patent application number | Description | Published |
20110135324 | BELT DRIVE APPARATUS AND IMAGE FORMING APPARATUS - A belt drive apparatus, including, an endless belt to be laid across in a tensioned condition between supporting rollers and to travel being in pressure contact with or being separated from a body to receive the pressure contact, a pressure contact/separating state detection section to detect whether the endless belt is in the pressure contact with the body or separated therefrom, a belt position detection section to detect a position of the endless belt in a width direction thereof, a belt abnormality judging section to judge whether the endless belt is in an abnormal position based on a detection result obtained by the belt position detection section and one of judgment values which are set correspondingly to the pressure contact/separating state of the endless belt, and a belt drive control section to control a drive of the endless belt. | 06-09-2011 |
20110188872 | FIXING DEVICE AND IMAGE FORMING APPARATUS - Disclosed is a fixing device including a fixing belt to fix a toner image formed on a paper onto the paper, a driving unit to make the fixing belt reciprocate in a direction perpendicular to a feeding direction of the paper when fixing the toner image onto the paper and a detecting unit to detect a position of the fixing belt in the perpendicular direction, and a control target value of the fixing belt is changed in accordance with the position of the fixing belt in the perpendicular direction detected by the detecting unit, and the fixing belt is made to reciprocate by the driving unit based on the changed control target value. | 08-04-2011 |
20110194860 | IMAGE FORMING APPARATUS - When an input image is to be formed on a sheet conveyed to a transfer roller, the exposure section is controlled and deviation correction is performed to offset the image forming position across the width of the sheet in response to the result of detection by a deviation sensor. By contrast, when pattern images are to be formed on a sheet in response to the instruction of the main control section, the image forming control section does not perform deviation correction in the process of forming a pattern image. | 08-11-2011 |
20120251150 | IMAGE FORMING APPARATUS - An image formation control section sets a secondary transfer section in the pressed state in the case of execution of a main scanning correction processing as color registration correction, and sets the secondary transfer section in the separated state in the case of execution of a sub-scanning correction processing, an entire lateral magnification correction processing, a partial lateral magnification correction processing, or a skew correction processing, which is the correction of the image position for components other than the main scanning direction as color registration correction so as to prevent the situation where the correction accuracy of the image position with respect to the main scanning direction decreases and to prevent a decrease in print quality due to a residual image of a registration correction processing. | 10-04-2012 |
Patent application number | Description | Published |
20100061783 | SHEET CONVEYING APPARATUS AND IMAGE FORMING APPARATUS - A sheet conveying apparatus provided with the first pair of rollers and the second pair of rollers which are positioned in the same axis perpendicular to a fixed direction, and convey a sheet in the conveying direction by rotating while nipping the sheet, the first drive section which drives the first pair of rollers and the second drive section which drives the second pair of rollers, the first detection section which detects a skew angle of the sheet against the conveying direction and a position of an edge part of the sheet in a direction perpendicular to the conveying direction before the sheet is conveyed by the pairs of rollers, and the control section which changes at least one of the rotating speeds based on the detected skew angle, and controls a timing to change the rotating speed based on the detected position of an edge part. | 03-11-2010 |
20110008086 | IMAGE FORMING APPARATUS, CLEAR LAYER FORMING APPARATUS, AND IMAGE FORMING SYSTEM - While having an image forming section which transfers a toner image according to image data onto a recording sheet, a first fixing section which fixes the toner image on the recording sheet with heat of the first fixing roller which rotates on the recording sheet, a clear layer forming section which forms a clear layer on the toner image which the first fixing section has fixed, a second fixing section which fixes the clear layer on the recording sheet with heat of the second fixing roller which rotates on the recording sheet and a control section which controls each part, the control section controls the clear layer forming section to increase the thickness of the clear layer in the recording sheet area corresponding to the fixed area during the second revolution of the first fixing roller on the recording sheet, compared with the first revolution thereof. | 01-13-2011 |