Patent application number | Description | Published |
20090117497 | METHOD OF FORMING PATTERN USING FINE PITCH HARD MASK - A method of forming a fine pattern of a semiconductor device using a fine pitch hard mask is provided. A first hard mask pattern including first line patterns formed on an etch target layer of a substrate with a first pitch is formed. A first layer including a top surface where a recess is formed between adjacent first line patterns is formed. A second hard mask pattern including second line patterns within the recess is formed. An anisotropic etching process is performed on the first layer using the first and the second line patterns as an etch mask. Another anisotropic etching process is performed on the etch target layer using the first and the second hard mask patterns as an etch mask. | 05-07-2009 |
20090239158 | Method of maintaining mask for semiconductor process - A method of maintaining a mask for a semiconductor process, the method includes providing a first structure and a second structure being attached to each other via a thermosetting material, detaching the first and second structures from each other, and performing an ashing process on the first structure. | 09-24-2009 |
20090258473 | Nonvolatile memory device and method of manufacturing the same - Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner. | 10-15-2009 |
20100173230 | PHOTOMASK - A photomask or equivalent optical component includes a scattering element in the medium of a substrate, which actively modifies (adjusts/filters the intensity, shape, and/or components of) light that propagates through the substrate. The substrate has a front surface and a back surface and is transparent to exposure light of a photolithography process, i.e., light of given wavelength, at least one mask pattern at the front surface of the substrate and the image of which is to be transferred to an electronic device substrate in a photolithographic process using the photomask, a blind pattern at the front surface of the substrate and opaque to the exposure light, and the scattering element. The scattering element, in addition to being formed in the medium of the substrate, is situated below the blind pattern as juxtaposed with the blind pattern in the direction of the thickness of the substrate. Also, a section of the photomask substrate is irradiated with energy which does not melt and/or vaporize the medium of the photomask substrate to form the scattering element. To this end, a femtosecond laser may be used. | 07-08-2010 |
20110059613 | MASK PATTERN FOR SEMICONDUCTOR DEVICE FABRICATION, METHOD OF FORMING THE SAME, AND METHOD OF FABRICATING FINELY PATTERNED SEMICONDUCTOR DEVICE - Provided are a mask pattern including a silicon-containing self-assembled molecular layer, a method of forming the same, and a method of fabricating a semiconductor device. The mask pattern includes a resist pattern formed on a semiconductor substrate and the self-assembled molecular layer formed on the resist pattern. The self-assembled molecular layer has a silica network formed by a sol-gel reaction. To form the mask pattern, first, the resist pattern is formed with openings on an underlayer covering the substrate to expose the underlayer to a first width. Then, the self-assembled molecular layer is selectively formed only on a surface of the resist pattern to expose the underlayer to a second width smaller than the first width. The underlayer is etched by using the resist pattern and the self-assembled molecular layer as an etching mask to obtain a fine pattern. | 03-10-2011 |
20110076846 | SEMICONDUCTOR DEVICE HAVING FINE CONTACTS AND METHOD OF FABRICATING THE SAME - A semiconductor device has a structure of contacts whose size and pitch are finer that those that can be produced under the resolution provided by conventional photolithography. The contact structure includes a semiconductor substrate, an interlayer insulating layer disposed on the substrate, annular spacers situated in the interlayer insulating layer, first contacts surrounded by the spacers, and a second contact buried in the interlayer insulating layer between each adjacent pair of the first spacers. The contact structure is formed by forming first contact holes in the interlayer insulating layer, forming the spacers over the sides of the first contact holes to leave second contact holes within the first contact holes, etching the interlayer insulating layer from between the spacers using the first spacers as an etch mask to form third contact holes, and filling the first and second contact holes with conductive material. In this way, the pitch of the contacts can be half that of the first contact holes. | 03-31-2011 |
20110104591 | Methods of Fabricating Halftone Phase Shift Blank Photomasks and Halftone Phase Shift Photomasks - Halftone phase shift photomasks are provided including a substrate configured to transmit light; a shift pattern on the substrate, the shift pattern including a pattern area on a center portion of the substrate and a blind area disposed on a periphery of the substrate, the shift pattern of the blind area having a greater thickness than a thickness that of the pattern area, and being configured to partially transmit the light; and a light shielding pattern formed on the shift pattern in the blind area and being configured to shield the light. Related methods are also provided herein. | 05-05-2011 |
20110244374 | Methods of Correcting Optical Parameters in Photomasks - A method of correcting an optical parameter in a photomask is provided. The method includes providing a photomask, exposing the photomask, detecting an aerial image to estimate the photomask, and irradiating gas cluster ion beams to the photomask based on an estimation result to correct the optical parameter in the photomask in relation to the aerial image. The gas cluster ion beams may be irradiated to a front surface of the photomask on which a mask pattern is formed or a rear surface of the photomask on which the mask pattern is not formed. | 10-06-2011 |
20130101926 | Halftone Phase Shift Blank Photomasks and Halftone Phase Shift Photomasks - Halftone phase shift photomasks are provided including a substrate configured to transmit light; a shift pattern on the substrate, the shift pattern including a pattern area on a center portion of the substrate and a blind area disposed on a periphery of the substrate, the shift pattern of the blind area having a greater thickness than a thickness that of the pattern area, and being configured to partially transmit the light; and a light shielding pattern formed on the shift pattern in the blind area and being configured to shield the light. Related methods are also provided herein. | 04-25-2013 |
Patent application number | Description | Published |
20090218609 | Semiconductor Memory Devices Including Offset Bit Lines - A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a respective drain portion of an active region of each column, and with each bitline being arranged between the respective drain portion and another drain portion of an adjacent active region of the same column. | 09-03-2009 |
20090218610 | Semiconductor Memory Devices Including Diagonal Bit Lines - A semiconductor memory device may include a semiconductor substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a drain portion of a respective active region of each column, and with each bitline crossing drain portions of active regions of adjacent columns in different directions so that different portions of a same bitline are aligned in different directions on different active regions of adjacent columns. | 09-03-2009 |
20090218654 | Semiconductor Memory Devices Including Extended Memory Elements - A semiconductor memory device may include a semiconductor substrate having an active region thereof, and the active region may have a length and a width, with the length being greater than the width. A field isolation layer may be on the semiconductor substrate surrounding the active region. First and second wordlines may be on the substrate crossing the active region, with the first and second wordlines defining a drain portion of the active region between the first and second wordlines and first and second source portions of the active region at opposite ends of the active region. First and second memory storage elements may be respectively coupled to the first and second source portions of the active region, with the first and second wordlines being between portions of the respective first and second memory storage elements and the active region in a direction perpendicular to a surface of the substrate. | 09-03-2009 |
20090263732 | MASK PATTERNS INCLUDING GEL LAYERS FOR SEMICONDUCTOR DEVICE FABRICATION - Mask patterns include a resist pattern and a gel layer on a surface of the resist pattern having a junction including hydrogen bonds between a proton donor polymer and a proton acceptor polymer. Methods of forming the mask patterns and methods of fabricating a semiconductor device using the mask patterns as etching masks are also provided. | 10-22-2009 |
20100112466 | OPTICAL MASKS AND METHODS FOR MEASURING ABERRATION OF A BEAM - An optical mask for use with an exposure beam includes a mask substrate adapted to be placed on a traveling path of the exposure beam. A reference pattern is formed on the mask substrate. The reference pattern is adapted to direct the exposure beam to travel in a predetermined reference direction. A comparative pattern is formed on the mask substrate. The comparative pattern is adapted to direct the exposure beam to travel in a direction inclined at a predetermined angle with respect to the reference direction. | 05-06-2010 |