Patent application number | Description | Published |
20090004807 | PASSIVE ELEMENTS, ARTICLES, PACKAGES, SEMICONDUCTOR COMPOSITES, AND METHODS OF MANUFACTURING SAME - Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein. | 01-01-2009 |
20090108328 | Array Of Non-volatile Memory Cells - An array of nonvolatile memory cells comprises a substantially single crystalline semiconductor substrate of a first conductivity type, having a planar surface. A plurality of non-volatile memory cell units are arranged in a plurality of rows and columns in the substrate. Each cell unit comprises a first region of a second conductivity type in the substrate along the planar surface. A second region of the second conductivity type is in the substrate along the planar surface, spaced apart from the first region. A channel region is between the first region and the second region. The channel region is characterized by three portions: a first portion, a second portion and a third portion, with the second portion between the first portion and the third portion, and the first portion adjacent to the first region, and the third portion adjacent to the second region. A first floating gate is over the first portion of the channel region, and is insulated therefrom. A first control gate is over the first floating gate and is capacitively coupled thereto. A first erase gate is over the first region and is insulated therefrom. A word line is over the second portion and is insulated therefrom. A second erase gate is over the second region and is insulated therefrom. A second floating gate is over the third portion and is insulated therefrom. A second control gate is over the second floating gate and is capacitively coupled thereto. Cell units in the same row share the word line in common. Cell units in the same column share the first region in common to one side, the first erase gate in common, the second region in common to the other side and the second erase gate in common, and the first and second control gates in common. Cell units in the same column share the first control gate in common and the second control gate in common. Electrical contacts are made to the array only along extremities of the array at first and second regions. | 04-30-2009 |
20090256590 | STORAGE ELEMENT FOR CONTROLLING A LOGIC CIRCUIT, AND A LOGIC DEVICE HAVING AN ARRAY OF SUCH STORAGE ELEMENTS - The present invention is a storage element for controlling a logic circuit and a logic device having a plurality of storage elements. The storage element has a first and a second non-volatile memory cells connected in series at an output node Each of the first and second non-volatile memory cells is for storing a state opposite to the other. A multiplexer has an input, a switched input and two outputs. The output node is connected to the input of the multiplexer. One of the outputs is used to control the logic circuit. The other output is connected to a bit line which is connected to a sense amplifier. Finally, the switched input receives a switch signal and outputs the signal from the output node to either the one output or the other output. | 10-15-2009 |
20090309182 | ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE - A first embodiment of an Electrostatic Discharge (ESD) structure for an integrated circuit for protecting the integrated circuit from an ESD signal, has a substrate of a first conductivity type. The substrate has a top surface. A first region of a second conductivity type is near the top surface and receives the ESD signal. A second region of the second conductivity type is in the substrate, separated and spaced apart from the first region in a substantially vertical direction. A third region of the first conductivity type, heavier in concentration than the substrate, is immediately adjacent to and in contact with the second region, substantially beneath the second region. In a second embodiment, a well of a second conductivity type is provided in the substrate of the first conductivity type. The well has a top surface. A first region of the second conductivity type is near the top surface. A second region of the second conductivity type is in the well, substantially along the bottom of the well. A third region of the first conductivity type, is immediately adjacent to and in contact with the second region, substantially beneath the second region. A fourth region of the first conductivity type is in the well, along the top surface thereof, and spaced apart from the first region. The first region and the fourth region receive the ESD signal. | 12-17-2009 |
20100173468 | PASSIVE ELEMENTS, ARTICLES, PACKAGES, SEMICONDUCTOR COMPOSITES, AND METHODS OF MANUFACTURING SAME - Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein. | 07-08-2010 |
20100259979 | Self Limiting Method For Programming A Non-volatile Memory Cell To One Of A Plurality Of MLC Levels - A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end, a floating gate insulated from a first portion of the channel region and adjacent to the second region, a first control gate adjacent to the floating gate and insulated therefrom, and insulated from a second portion of the channel region, and adjacent to the first region, a second control gate capacitively coupled to the floating gate, and positioned over the floating gate. A method programming the cell to one of a plurality of MLC states comprises applying a current source to the first region. A first voltage is applied to the first control gate sufficient to turn on the second portion of the channel region. A second voltage is applied to the second region, sufficient to cause electrons to flow from the first region towards the second region. A third voltage is applied to the second control gate sufficient to cause electrons in the channel region to be injected onto the floating gate. The third voltage is applied uninterrupted until the floating gate is programmed to the one state. | 10-14-2010 |
Patent application number | Description | Published |
20090176454 | Methods and apparatus for wireless device coexistence - Methods and apparatus for compensating for the effects of interference between multiple wireless communication apparatus. In one embodiment, the method comprises providing a first wireless communication apparatus operating in a first band and a second wireless communication apparatus operating at least partly in the first band, where the second wireless communication apparatus operates according to a different communication protocol than the first wireless communication apparatus. Interference is compensated for between the first wireless communication apparatus and the second wireless communication apparatus by selecting and operating according to one of a plurality of operational protocols. In another embodiment, the first wireless communication apparatus and the second wireless communication apparatus operate in a closed-loop relationship to cooperatively compensate for communication interference. | 07-09-2009 |
20090257379 | Methods and apparatus for network capacity enhancement for wireless device coexistence - Methods and apparatus for enhancing network capacity in a network comprising multiple wireless communication that overlap at least partly in frequency spectrum. In one embodiment, the apparatus comprises a portable device such as a laptop or smartphone having both a WLAN (e.g., Wi-Fi) interface and a PAN (e.g., Bluetooth) interface which each operate with approximately the same frequency range. One variant places the WLAN interface into a power-saving mode as a default, thereby mitigating interference with the PAN interface in cases where the WLAN interface is not in active use. In another variant, an aggressive PAN management algorithm is used to enforce network policy on the PAN interface, thereby mitigating interference between the PAN interface and the WLAN interfaces of other devices in the network (as well as the parent device). AP-based variants are also described. Methods of operation and doing business utilizing the aforementioned apparatus are also disclosed. | 10-15-2009 |
20090323652 | Methods and apparatus for antenna isolation-dependent coexistence in wireless systems - Methods and apparatus for selectively switching one or more antennas in a multiple-input, multiple-output (MIMO) antenna array so as to mitigate interference with another RF interface within the same space-constrained device, based on radio frequency isolation. In one embodiment, the MIMO interface comprises a WLAN interface having a 2×2 or 3×3 array of antennae which are placed in a wireless device in an asymmetric fashion with respect to the antenna of the second interface, and the other interface comprises a PAN (e.g., Bluetooth) interface operating in an overlapping frequency band (e.g., ISM band). When both interfaces are operating, interference is mitigated through selectively switching off one or more of the MIMO antennae, and using the remaining antenna(e) having the best isolation from the Bluetooth antennae. This approach allows simultaneous operation of both interferences without significant degradation to user experience or the operation of either interface, and may also provide power savings critical to mobile device battery longevity. | 12-31-2009 |
20100240317 | METHODS AND APPARATUS FOR TESTING AND INTEGRATION OF MODULES WITHIN AN ELECTRONIC DEVICE - Methods and apparatus for analysis of electronic components such as radio transceivers (for example, WLAN, Bluetooth, cellular, GPS). In one embodiment, a “black box” is diagnosed in its final device application and layout, using a series of software test routines or suites. The test suites provide simultaneous monitoring of multiple non-overlapping status indicators. Each test suite can be selectively enabled or disabled, and may also provide runtime modification of one or more parameters, and or intelligent testing of system operation. In another embodiment, multiple black box modules within a single form factor device are simultaneously run; the interference levels between the black box modules (as well as other parameters) are independently measured, displayed and logged to the user. Exemplary embodiments are described in reference to a Bluetooth module and WLAN module operating within a spatially restricted device (such as a desktop/laptop computer, “smartphone”, Bluetooth mouse and keyboard). | 09-23-2010 |
20110081858 | METHODS AND APPARATUS FOR ENHANCED COEXISTENCE ALGORITHMS IN WIRELESS SYSTEMS - Methods and apparatus for mitigating the effects of interference between multiple air interfaces located on an electronic device. In one embodiment, the air interfaces include a WLAN interface and PAN (e.g., Bluetooth) interface, and information such as Receiver Signal Strength Index (RSSI) as well as system noise level information are used in order to intelligently execute interference mitigation methodologies, including the selective application of modified frequency selection, variation of transmitter power, and/or change of operating mode (e.g., from multiple-in multiple-out (MIMO) to single-in, single-out (SISO)) so as to reduce isolation requirements between the interfaces. These methods and apparatus are particularly well suited to use cases where the WLAN interface is operating with high data transmission rates. Business methods associated with the foregoing technology are also described. | 04-07-2011 |
20110090982 | METHODS AND APPARATUS FOR DYNAMIC WIRELESS DEVICE COEXISTENCE - Methods and apparatus for dynamically compensating for the effects of interference between multiple wireless communications apparatus. In one embodiment, the method comprises providing a first wireless communication apparatus operating in a first band and a second wireless communication apparatus operating in the same first band (or proximate to the first band and with a comparatively high transmitter power), where the second wireless communication apparatus operates according to a different communication protocol than the first wireless communication apparatus and further change in physical configuration with respect to one another. Based on the physical configuration, interference is compensated for between the first wireless communication apparatus and the second wireless communication apparatus “on the fly” by selecting and operating according to one of a plurality of operational protocols. | 04-21-2011 |
20120207032 | METHODS AND APPARATUS FOR WIRELESS COEXISTENCE BASED ON TRANSCEIVER CHAIN EMPHASIS - Methods and apparatus for reduction of interference between a plurality of wireless interfaces. In one exemplary embodiment, a device having a first (e.g., Wi-Fi) interface and a second (e.g., Bluetooth) interface monitors interference between its interfaces. A reduction in transmit power of the Wi-Fi module causes a disproportionately larger reduction in undesirable interference experienced at the Bluetooth antennas. For example, when the Bluetooth interface detects interference levels above acceptable thresholds, the Wi-Fi interface adjusts operation of one or more of its transmit chains based on various conditions such as duty cycle, Received Signal Strength Indication (RSSI), etc. Various embodiments of the present invention provide simultaneous operation of WLAN and PAN interfaces, without requiring time division coexistence, by reducing power on a subset of interfering antennas. | 08-16-2012 |
20130035047 | METHODS AND APPARATUS FOR ANTENNA ISOLATION-DEPENDENT COEXISTENCE IN WIRELESS SYSTEMS - Methods and apparatus for selectively switching one or more antennas in a multiple-input, multiple-output (MIMO) antenna array so as to mitigate interference with another RF interface within the same space-constrained device, based on radio frequency isolation. In one embodiment, the MIMO interface comprises a WLAN interface having a 2×2 or 3×3 array of antennae which are placed in a wireless device in an asymmetric fashion with respect to the antenna of the second interface, and the other interface comprises a PAN (e.g., Bluetooth) interface operating in an overlapping frequency band (e.g., ISM band). When both interfaces are operating, interference is mitigated through selectively switching off one or more of the MIMO antennae, and using the remaining antenna(e) having the best isolation from the Bluetooth antennae. This approach allows simultaneous operation of both interferences without significant degradation to user experience or the operation of either interface, and may also provide power savings critical to mobile device battery longevity. | 02-07-2013 |
20130064118 | METHODS AND APPARATUS FOR NETWORK CAPACITY ENHANCEMENT FOR WIRELESS DEVICE COEXISTENCE - Methods and apparatus for enhancing network capacity in a network comprising multiple wireless communication that overlap at least partly in frequency spectrum. In one embodiment, the apparatus comprises a portable device such as a laptop or smartphone having both a WLAN (e.g., Wi-Fi) interface and a PAN (e.g., Bluetooth) interface which each operate with approximately the same frequency range. One variant places the WLAN interface into a power-saving mode as a default, thereby mitigating interference with the PAN interface in cases where the WLAN interface is not in active use. In another variant, an aggressive PAN management algorithm is used to enforce network policy on the PAN interface, thereby mitigating interference between the PAN interface and the WLAN interfaces of other devices in the network (as well as the parent device). AP-based variants are also described. Methods of operation and doing business utilizing the aforementioned apparatus are also disclosed. | 03-14-2013 |
20130143494 | METHODS AND APPARATUS FOR WIRELESS OPTIMIZATION BASED ON PLATFORM CONFIGURATION AND USE CASES - Methods and apparatus for optimizing wireless network performance by incorporating platform configuration and use case information. In one exemplary scheme, a client device provides the wireless network with an indications of impacted operations based on the client device's platform configuration. The wireless network can adjust the radio link to the client device so as to best accommodate the impacted operation. In one embodiment, a client device that includes a 3×3 Wireless Local Area Network (WLAN) (or 4×4, 2×2, etc.) and Bluetooth (BT) module identifies a subset of modulation and coding schemes (MCS) that are preferred for operation. The client device provides the identified subset to the WLAN access point (AP). Responsively, the WLAN AP selects a MCS, such that the client device's overall performance remains at an acceptable level. In another embodiment, the server/client can adjust MCS and/or active antenna chains based on the noise floor (NF) level. | 06-06-2013 |
20130182589 | METHODS AND APPARATUS FOR ENHANCED COEXISTENCE ALGORITHMS IN WIRELESS SYSTEMS - Methods and apparatus for mitigating the effects of interference between multiple air interfaces located on an electronic device. In one embodiment, the air interfaces include a WLAN interface and PAN (e.g., Bluetooth) interface, and information such as Receiver Signal Strength Index (RSSI) as well as system noise level information are used in order to intelligently execute interference mitigation methodologies, including the selective application of modified frequency selection, variation of transmitter power, and/or change of operating mode (e.g., from multiple-in multiple-out (MIMO) to single-in, single-out (SISO)) so as to reduce isolation requirements between the interfaces. These methods and apparatus are particularly well suited to use cases where the WLAN interface is operating with high data transmission rates. Business methods associated with the foregoing technology are also described. | 07-18-2013 |
20130225100 | METHODS AND APPARATUS FOR WIRELESS DEVICE COEXISTENCE - Methods and apparatus for compensating for the effects of interference between multiple wireless communication apparatus. In one embodiment, the method comprises providing a first wireless communication apparatus operating in a first band and a second wireless communication apparatus operating at least partly in the first band, where the second wireless communication apparatus operates according to a different communication protocol than the first wireless communication apparatus. Interference is compensated for between the first wireless communication apparatus and the second wireless communication apparatus by selecting and operating according to one of a plurality of operational protocols. In another embodiment, the first wireless communication apparatus and the second wireless communication apparatus operate in a closed-loop relationship to cooperatively compensate for communication interference. | 08-29-2013 |
20130329821 | METHODS AND APPARATUS FOR MITIGATING INTERFERENCE IN AGGRESSIVE FORM FACTOR DESIGNS - Methods and apparatus for mitigation of radio interference between two or more wireless concurrently operating interfaces in a wireless device having an aggressive form factor. In one embodiment, the interfaces are used for different tasks (e.g., WLAN for data and PAN for human interface devices), and the device includes logic configured to evaluate the priority of the tasks and adjust the operation of one or more of the interfaces accordingly. | 12-12-2013 |
20140177459 | METHODS AND APPARATUS FOR RAPID AND COST EFFECTIVE TESTING OF WIRELESS SYSTEMS - Apparatus and methods for rapid, cost effective testing of wireless systems. In one embodiment, a unit under test (UUT) is tested by a test “server”. The UUT and test server communicate via a “connectionless” protocol which is based on beacons (and beacon responses) which can carry one or more test primitives. The aforementioned “connection-less” test protocol can be performed without wireless network configuration, which greatly reduces test time, Additionally, exemplary solutions are presented for “lock-up” of the UUT and the test server. | 06-26-2014 |
20140221029 | METHODS AND APPARATUS FOR WIRELESS COEXISTENCE BASED ON TRANSCEIVER CHAIN EMPHASIS - Methods and apparatus for reduction of interference between a plurality of wireless interfaces. In one exemplary embodiment, a device having a first (e.g., Wi-Fi) interface and a second (e.g., Bluetooth) interface monitors interference between its interfaces. A reduction in transmit power of the Wi-Fi module causes a disproportionately larger reduction in undesirable interference experienced at the Bluetooth antennas. For example, when the Bluetooth interface detects interference levels above acceptable thresholds, the Wi-Fi interface adjusts operation of one or more of its transmit chains based on various conditions such as duty cycle, Received Signal Strength Indication (RSSI), etc. Various embodiments of the present invention provide simultaneous operation of WLAN and PAN interfaces, without requiring time division coexistence, by reducing power on a subset of interfering antennas. | 08-07-2014 |
Patent application number | Description | Published |
20110099519 | Menuing Structure for Media Content - Methods, systems, articles of manufacture, and apparatus for causing a computer system such as a media device to perform operations may include receiving input from the user selecting a media type category, identifying media content items within the selected media category that the user has previously selected for presentation, prioritizing the identified media content items based on a predetermined set of rules, and presenting to the user a menu of at least some of the identified media content items in an order based on a result of the prioritization. | 04-28-2011 |
20130095463 | CONTENT AUTHORING APPLICATION - This disclosure describes systems, methods, and computer program products for authoring content for e-learning courses, such as network-enabled (e.g., Web-based) education courses. Graphical user interfaces (GUIs) provide an instructor with user interface elements to manage online course content. Using the GUIs, the instructor can create in-session and self-paced courses that can be delivered over a network to any number of student operated client devices. The instructor is provided a suite of editing tools that can be used to create and edit pages of content for a course, including adding links and multimedia, information pages, posts and course materials. The GUI can include a side bar that can display descriptors that can be used by the instructor to navigate pages of the course. | 04-18-2013 |
20130095464 | ELECTRONIC LEARNING APPLICATION - Systems, methods, and computer program products for accessing e-learning courses from an online resource are disclosed. Graphical user interfaces (GUIs) allow students to enroll in online courses or collections of other media (e.g., video files, presentations). The courses can include in-session and self-paced courses. The courses can be delivered over a network to any number and types of student operated devices. An e-learning application running on the student-operated device provides various user interface elements that allow the student to browse, select, enroll and interact with online courses. In some implementations, the GUIs provide a display object (e.g., a virtual spiral-bound notebook) that includes tabs that can be selected by the student to navigate pages of an online course to access information, materials, posts and notes. | 04-18-2013 |
20140114808 | DISPLAYING A BUY/DOWNLOAD BUTTON BASED ON PURCHASE HISTORY - Methods, systems, computer-readable media, and apparatuses for providing enhanced user interfaces and functionalities for internet radio applications are presented. In some embodiments, a computer system may provide a user interface that includes one or more regions configured to control playback of an internet radio station. The computer system then may determine, based on music purchase history associated with a user account, whether a selected song associated with the internet radio station has been previously purchased. In response to determining that the selected song has not been previously purchased, the computer system may display a user-selectable control that enables the selected song to be purchased. On the other hand, in response to determining that the selected song has been previously purchased, the computer system may display a user-selectable control that enables the selected song to be downloaded. | 04-24-2014 |
20140123006 | USER INTERFACE FOR STREAMING MEDIA STATIONS WITH FLEXIBLE STATION CREATION - User interfaces provide options for customizing a streaming media application to incorporate a personalized stations list defined by a user. For example, a user can create stations based on categories (e.g., genres or other characteristics), specific artists, and/or specific tracks. The user can select categories, artists, or tracks to be used for defining a station via a number of options, such as by searching or browsing a radio service's library of tracks; by selecting a currently playing or previously played track; and/or by selecting a track from a user's personal media library. Stations that a user has defined can be further customized based on user feedback, and stations on the user's personal stations list can be edited, deleted, and/or rearranged as the user sees fit. | 05-01-2014 |
20140266637 | BROADCAST CONTROL AND ACCRUED HISTORY OF MEDIA - Pairing a portable electronic device with a media device that is playing media, providing control to the portable device, displaying information about the media being played on the portable electronic device, and providing a link to the media asset in an online store. Discovering that a media device that is currently publically playing media, receiving a media signal encoded with metadata describing the media being played, and displaying an accrued history of various instances of media items that have been overheard during a public play session as a list of media items associated with metadata describing the media items. | 09-18-2014 |
20140362167 | CONFERENCE ROOM MODE OF A MEDIA DEVICE - Techniques for automatically configuring and controlling a conference room mode setting of a digital media device are described. A digital media device can be programmed to enter a conference room operating mode upon a trigger event. The trigger event can include a time-based trigger or an event-based trigger. In the conference room mode, the digital media device can provide for display an identifier of the digital media device and an identifier of a network for accessing the digital media device. The identifier of the digital media device and identifier of a network can be used by a mobile device to connect to the digital media device and to submit content to the digital media device. Once configured, the digital media device can enter the conference room mode automatically, without requiring a user to select the conference room mode using a remote control. | 12-11-2014 |
Patent application number | Description | Published |
20080263750 | Headwear with signal generating capability - A headwear with signal generating capability includes: a headwear body; a signal output unit mounted on the headwear body for generating at least one of audio and video signals; a control circuit including a controller coupled electrically to the signal output unit for controlling activation and deactivation of the signal output unit; and a switch mounted on the headwear body and coupled electrically to the control circuit for controlling operating states of the control circuit. | 10-30-2008 |
20090183401 | MESSAGE CARD - A message card includes: a card body having first and second leaves, the card body being foldable and unfoldable in a manner that the first leaf is movable toward and away from the second leaf between closed and opened positions; a mounting base provided on the second leaf; a supporting mechanism mounted on the mounting base and defining two opposite end openings that are spaced apart from each other by a gap; a circuit unit; a switch mounted on the mounting base, coupled electrically to the circuit unit, and having an actuating member extending into the gap; and a flexible driving lever attached to the first leaf, extending through the end openings, and co-movable with the first leaf relative to the second leaf. The driving lever has a driving segment that is received in the gap to drive movement of the actuating member of the switch. | 07-23-2009 |
20090220928 | ARTICLE WITH CIRCUIT ACTUATING CAPABILITY - An article with circuit actuating capability includes a first article part, a second article part formed with a pocket and linked to the first article part such that the first and second article parts being movable relative to each other, the pocket having an access opening, and a circuit built in the pocket in the second article part and accessible through the access opening of the pocket for controlling circuit states of the circuit. | 09-03-2009 |
20100038276 | Zipper assembly with a circuit actuating capability and bag having the zipper assembly - A zipper assembly includes: first and second zipper tapes; a zipper chain having one end and including first teeth secured to the first zipper tape and second teeth secured to the second zipper tape; a zipper slider mounted slidably on the zipper chain for engaging and disengaging the first and second teeth; an end stopper secured to the first and second zipper tapes, and disposed adjacent to the end of the zipper chain; and a switch mounted to the end stopper in such a manner that the switch is switched on by the zipper slider so as to actuate a circuit when the zipper slider is moved to the end of the zipper chain. | 02-18-2010 |
20100089786 | GIFT PACKAGE HAVING CIRCUIT ACTUATING CAPABILITY - A gift package includes: a box body having a partitioning plate dividing an inner space in the box body into first and second chambers and adapted to abut against an article, the box body being provided with a lid for covering and uncovering an access opening of the box body; a signal output unit mounted in the second chamber; a circuit board mounted securely in the second chamber and provided with a controller that is electrically coupled to the signal output unit for controlling activation and deactivation of the signal output unit; and a switch operable through a selected one of the lid and the article to activate the signal output unit. | 04-15-2010 |
20100264045 | CUP ASSEMBLY WITH CIRCUIT ACTUATING CAPABILITY - A cup assembly with circuit actuating capability comprises: a cup body having a bottom recess that is defined by a recess-defining wall and that has an open end, the recess-defining wall being provided with a threaded structure; a module support having a base part that covers the open end of the bottom recess, and a threaded confining part that is connected to the base part, that is received in the bottom recess, that defines an accommodating space, and that engages threadedly with the threaded structure; and a signal producing module mounted on the base part, received in the accommodating space, and including a signal producing member and a first switch that is coupled to the signal producing member and that is operable to enable and disable the signal producing member. | 10-21-2010 |
20110273280 | MEDICAMENT REMINDER DEVICE - A medicament reminder device for reminding patients to ingest or administer medicaments includes an output ( | 11-10-2011 |
Patent application number | Description | Published |
20100153912 | Variable type knowledge based call specialization - Variable type knowledge based call specialization is disclosed. An indication is received that a variable that is an argument of a function or operation the behavior of which depends at least in part on a data type of the argument is of a first data type. Machine code that implements a first behavior that corresponds to the first data type, but not a second behavior that corresponds to a second data type other than the first data type, is generated for the function or operation. | 06-17-2010 |
20100153929 | Converting javascript into a device-independent representation - A device-independent intermediate representation of a source code is generated and stored, e.g., in a memory or other storage mechanism. The stored intermediate representation of the source code is used to generate a device-specific machine code corresponding to the source code. The stored intermediate representation may be updated, e.g., periodically, for example by obtaining an updated version of the source code and compiling the updated source code to generate an updated intermediate representation. The stored intermediate representation may be based on source code received from a device that is synchronized with which a compiling device that generates the device-specific machine code. In some cases, the stored intermediate representation may be used to generate for each of a plurality of devices a corresponding device-specific machine code. | 06-17-2010 |
20120030653 | ASSUMPTION-BASED COMPILATION - Techniques for processing source code written in a traditionally interpreted language such as JavaScript, or another dynamic and/or interpreted language, are disclosed. In one example, compiled code associated with the source code is constructed and executed. An assumption on which a specific aspect of the compiled code is based (e.g., an optimization) is tested at a checkpoint of the compiled code. A roll over to fallback code is performed if the test indicates the assumption is not true. | 02-02-2012 |
20120030659 | CONSTRUCTING RUNTIME STATE FOR INLINED CODE - Techniques for processing computer code are disclosed. In one example, an indication that a computer code is to begin execution at a portion of code other than a starting portion of the code is received, and a runtime state associated with the portion of the code at which execution is to begin is constructed. In some examples, execution of the portion of code is initiated. In some examples, a program counter associated with the portion of the code is used to initiate execution of the code. In some examples, the computer code comprises a fallback code associated with a previously executing code. | 02-02-2012 |
20120030661 | OBSERVATION AND ANALYSIS BASED CODE OPTIMIZATION - Observation and analysis based optimization of software code is disclosed. An expected value is chosen for a dynamic attribute that cannot be determined, prior to execution of the associated software code, to be guaranteed to have that expected value at runtime. An optimized version of the software code is generated, including one or more optimizations based on an assumption that the dynamic attribute will have the expected value. Non-exhaustive examples of a dynamic attribute include a variable type; a location in memory; a location in which a global object, property, or variable is stored; the contents of a global function or method; and a value of a global property or variable. A check is performed during execution of the optimized version of the software code, prior to executing the portion that has been optimized based on the assumption, to verify that the dynamic attribute has the expected value. In the event that it is determined at runtime that the dynamic attribute does not have the expected value, execution reverts to backup code that is not based on the assumption that dynamic attribute will have the expected value. | 02-02-2012 |
Patent application number | Description | Published |
20110096572 | LOW POWER CONSUMPTION START-UP CIRCUIT WITH DYNAMIC SWITCHING - A start-up circuit in a switch-mode power converter that employs a Zener diode to provide a reference voltage to reduce the power consumption and the size of the start-up circuit. The start-up circuit also includes a coarse current source and a coarse reference voltage signal generator for producing current and reference voltage for initial startup operation of a bandgap circuit. The reference signal and current from coarse current source and the reference voltage signal generator are subject to large process, voltage and temperature (PVT) variations or susceptible to noise from the power supply, and hence, these signals are used temporarily during start-up and replaced with signals from higher performance components. After bandgap circuit becomes operational, the start-up receives voltage reference signal from the bandgap circuit to more accurately detect undervoltage lockout conditions. | 04-28-2011 |
20130107584 | Dynamic Mosfet Gate Drivers | 05-02-2013 |
20130121044 | Power Converter Controller IC Having Pins with Multiple Functions - A controller integrated circuit (IC) for controlling a power converter uses one or more IC pins having plurality of functions such as configuration of a parameter supported by the controller IC and shutdown protection. Several different functions may be supported by a single IC pin, thereby reducing the number of pins required in the controller IC and also reducing the cost of manufacturing the controller IC. The controller IC may also share a comparison circuit among different pins and the different functions provided by those pins. Use of a shared comparison circuit further reduces the cost of manufacturing the controller IC without sacrificing the performance of the IC. | 05-16-2013 |
20130241430 | Dynamic Control of Power Switching Bipolar Junction Transistor - The embodiments disclosed herein describe the dynamic control of a switching power converter between different operation modes of the switching power converter. In one embodiment, the operation modes of the switching power converter include a switching mode and a linear mode. The switching power converter may be included in a LED lamp system according to one embodiment. | 09-19-2013 |
20140078789 | SWITCHING POWER CONVERTER WITH SECONDARY-SIDE DYNAMIC LOAD DETECTION AND PRIMARY-SIDE FEEDBACK AND CONTROL - A power converter includes a transformer with a primary and a secondary winding. Feedback and control is maintained on the primary-side while a separate load detection circuit detects dynamic load conditions on the secondary-side. The load detection circuit detects dynamic load conditions at the time when a load is connected to the output of the switching power converter and, in turn, generates an alert signal. A coupling circuit coupled to the load detection circuit at the secondary winding side of the transformer and to the controller at the primary winding side of the transformer transmits the alert signal to the controller. The controller regulates the output voltage based on the feedback signal generated at the primary side of the transformer while detecting and responding to the dynamic load condition based on the alert signal generated at the secondary side of the transformer. | 03-20-2014 |
20140085940 | Power System Switch Protection Using Output Driver Regulation - A controller of a switching power converter includes a voltage protection circuit that generates a modified supply voltage that does not exceed a predetermined threshold voltage to power one or more components of the controller. | 03-27-2014 |
20140159616 | ADAPTIVE HOLDING CURRENT CONTROL FOR LED DIMMER - A TRIAC dimmer controller for an LED lamp dynamically adjusts the amount of additional current supplied to the TRIAC dimmer based on the TRIAC dimmer operating mode. A TRIAC dimmer current controller continually senses the TRIAC dimmer current loading and determines a TRIAC dimmer operating mode based on the detected current. The TRIAC dimmer controller compares the detected current with a threshold current value called a TRIAC holding current, and adjusts the amount of bleeder current based on the difference between the detected current and the threshold current value. By continually sensing the TRIAC dimmer current loading, the LED controller regulates the amount of bleeder current supplied to the TRIAC dimmer using a single sink current path to satisfy the TRIAC dimmer current demands of multiple TRIAC dimmer operating modes. | 06-12-2014 |
Patent application number | Description | Published |
20120322250 | N-Metal Film Deposition With Initiation Layer - Provided are methods of depositing N-Metals onto a substrate. Some methods comprise providing an initiation layer of TaM or TiM layer on a substrate, wherein M is selected from aluminum, carbon, noble metals, gallium, silicon, germanium and combinations thereof; and exposing the substrate having the TaM or TiM layer to a treatment process comprising soaking the surface of the substrate with a reducing agent to provided a treated initiation layer. | 12-20-2012 |
20120322262 | N-Metal Film Deposition With Initiation Layer - Provided are methods of depositing N-Metals onto a substrate. Methods include first depositing an initiation layer. The initiation layer may comprise or consist of cobalt, tantalum, nickel, titanium or TaAlC. These initiation layers can be used to deposit TaC | 12-20-2012 |
20130122697 | Doping aluminum in tantalum silicide - Provided are methods of providing aluminum-doped TaSi | 05-16-2013 |
20130295759 | Methods For Manufacturing Metal Gates - Provided are methods for making metal gates suitable for FinFET structures. The methods described herein generally involve forming a high-k dielectric material on a semiconductor substrate; depositing a high-k dielectric cap layer over the high-k dielectric material; depositing a PMOS work function layer having a positive work function value; depositing an NMOS work function layer; depositing an NMOS work function cap layer over the NMOS work function layer; removing at least a portion of the PMOS work function layer or at least a portion of the NMOS work function layer; and depositing a fill layer. Depositing a high-k dielectric cap layer, depositing a PMOS work function layer or depositing a NMOS work function cap layer may comprise atomic layer deposition of TiN, TiSiN, or TiAlN. Either PMOS or NMOS may be deposited first. | 11-07-2013 |
20140017408 | Deposition Of N-Metal Films Comprising Aluminum Alloys - Provided are methods of depositing films comprising alloys of aluminum, which may be suitable as N-metal films. Certain methods comprise exposing a substrate surface to a metal halide precursor comprising a metal halide selected from TiCl | 01-16-2014 |
20140112824 | Deposition Of Films Comprising Aluminum Alloys With High Aluminum Content - Provided are films comprising aluminum, carbon and a metal, wherein the aluminum is present in an amount greater than about 16% by elemental content and less than about 50% carbon. Also provided are methods of depositing the same. | 04-24-2014 |
Patent application number | Description | Published |
20120153377 | EDGE ROUNDED FIELD EFFECT TRANSISTORS AND METHODS OF MANUFACTURING - Embodiments of the present technology are directed toward gate sidewall engineering of field effect transistors. The techniques include formation of a blocking dielectric region and nitridation of a surface thereof. After nitridation of the blocking dielectric region, a gate region is formed thereon and the sidewalls of the gate region are oxidized to round off gate sharp corners and reduce the electrical field at the gate corners. | 06-21-2012 |
20120156856 | PROCESS MARGIN ENGINEERING IN CHARGE TRAPPING FIELD EFFECT TRANSISTORS - Embodiments of the present technology are directed toward charge trapping region process margin engineering for charge trapping field effect transistor. The techniques include forming a plurality of shallow trench isolation regions on a substrate, wherein the tops of the shallow trench isolation regions extend above the substrate by a given amount. A portion of the substrate is oxidized to form a tunneling dielectric region. A first set of one or more nitride layers are deposited on the tunneling dielectric region and shallow trench isolation regions, wherein a thickness of the first set of nitride layers is approximately half of the given amount that the tops of the shallow trench isolation regions extend above the substrate. A portion of the first set of nitride layers is etched back to the tops of the trench isolation regions. A second set of one or more nitride layers is deposited on the etched back first set of nitride layers. The second set of nitride layers is oxidized to form a charge trapping region on the tunneling dielectric region and a blocking dielectric region on the charge trapping region. A gate region is then deposited on the blocking dielectric region. | 06-21-2012 |
20120156876 | SELF-ALIGNED NAND FLASH SELECT-GATE WORDLINES FOR SPACER DOUBLE PATTERNING - A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed. The photoresist pattern is stripped away leaving the spacer pattern. A trim mask is placed over a portion of the spacer pattern. Portions of the spacer pattern are etched away that are not covered by the trim mask. The trim mask is removed, wherein first remaining portions of the spacer pattern define a plurality of core wordlines. A pad mask is placed such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines. Finally at least one pattern transfer layer is etched through using the mad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicon layer. | 06-21-2012 |
20120168847 | MEMORY WITH EXTENDED CHARGE TRAPPING LAYER - A memory array includes a plurality of bit lines and a plurality of word lines, a gate region, and a charge trapping layer. The charge trapping layer is wider than a word line; the charge trapping layer is extended beyond the edge of the gate region to facilitate capturing and removing charges. | 07-05-2012 |
20130316537 | SELF-ALIGNED NAND FLASH SELECT-GATE WORDLINES FOR SPACER DOUBLE PATTERNING - A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed. The photoresist pattern is stripped away leaving the spacer pattern. A trim mask is placed over a portion of the spacer pattern. Portions of the spacer pattern are etched away that are not covered by the trim mask. The trim mask is removed, wherein first remaining portions of the spacer pattern define a plurality of core wordlines. A pad mask is placed such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines. Finally at least one pattern transfer layer is etched through using the mad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicon layer. | 11-28-2013 |
20140001534 | APPARATUS AND METHOD FOR ROUNDED ONO FORMATION IN A FLASH MEMORY DEVICE | 01-02-2014 |
20140141591 | Method to Improve Charge Trap Flash Memory Core Cell Performance and Reliability - A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride. | 05-22-2014 |
20140148009 | Forming a Substantially Uniform Wing Height Among Elements in a Charge Trap Semiconductor Device - During formation of a charge trap separation in a semiconductor device, an organic material is formed over a plurality of cells. This organic material is selectively removed in order to create a flat upper surface. An etching process is performed to remove the organic material as well as a charge trap layer formed over the plurality of cells, thereby exposing underlying first oxide layers in each of the cells and forming charge trap separation. Further, because of the selective removal step, the etch results in substantially uniform wing heights among the separated cells. | 05-29-2014 |
20150035044 | Method to Improve Charge Trap Flash Memory Core Cell Performance and Reliability - A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride. | 02-05-2015 |
Patent application number | Description | Published |
20130061024 | Bitstream Buffer Manipulation With A SIMD Merge Instruction - Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block. | 03-07-2013 |
20130061025 | Bitstream Buffer Manipulation With A SIMD Merge Instruction - Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block. | 03-07-2013 |
20130124824 | Bitstream Buffer Manipulation With A SIMD Merge Instruction - Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block. | 05-16-2013 |
20130138917 | Bitstream Buffer Manipulation With A SIMD Merge Instruction - Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block. | 05-30-2013 |
20130145120 | Bitstream Buffer Manipulation With A SIMD Merge Instruction - Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block. | 06-06-2013 |
20130145125 | Bitstream Buffer Manipulation With A SIMD Merge Instruction - Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block. | 06-06-2013 |
20130159672 | Bitstream Buffer Manipulation With A SIMD Merge Instruction - Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block. | 06-20-2013 |
Patent application number | Description | Published |
20100085794 | SET AND RESET DETECTION CIRCUITS FOR REVERSIBLE RESISTANCE SWITCHING MEMORY MATERIAL - Circuitry for performing a set or reset process for a reversible resistance-switching memory element in a memory device. A ramped voltage is applied to the memory cell and its state is constantly monitored so that the voltage can be discharged as soon as the set or reset process is completed, avoiding possible disturbs to the memory cell. One set circuit ramps the voltage using a current source, while detecting a current peak using an op-amp loop. One reset circuit ramps the voltage using an op-amp loop, while detecting a current peak by continuing to draw current at the peak current to maintain the output signal stable. Another set circuit ramps the voltage using an op-amp loop and a source-follower configuration. Another reset circuit ramps the voltage using an op-amp loop and a source-follower configuration with level shifting to reduce power consumption. Faster detection and shutoff, and stable operation, are achieved. | 04-08-2010 |
20140233327 | COMPENSATION SCHEME FOR NON-VOLATILE MEMORY - Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell. | 08-21-2014 |
20140233329 | COMPENSATION SCHEME FOR NON-VOLATILE MEMORY - Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell. | 08-21-2014 |
20140241090 | SMART READ SCHEME FOR MEMORY ARRAY SENSING - Methods for reducing variability in bias voltages applied to a plurality of memory cells during a sensing operation caused by IR drops along a word line shared by the plurality of memory cells are described. In some embodiments, IR drops along a shared word line may be reduced by reducing sensing currents associated with memory cells whose state has already been determined during a sensing operation. In one example, once a sense amplifier detects that a memory cell being sensed is in a particular state, then the sense amplifier may disable sensing of the memory cell and discharge a corresponding bit line associated with the memory cell. In some cases, a bit line voltage associated with a memory cell whose state has not already been determined during a first phase of a sensing operation may be increased during a second phase of the sensing operation. | 08-28-2014 |
20140347912 | SENSE AMPLIFIER LOCAL FEEDBACK TO CONTROL BIT LINE VOLTAGE - Methods for precharging bit lines using closed-loop feedback are described. In one embodiment, a sense amplifier may include a bit line precharge circuit for setting a bit line to a read voltage prior to sensing a memory cell connected to the bit line. The bit line precharge circuit may include a first transistor in a source-follower configuration with a first gate and a first source node electrically coupled to the bit line. By applying local feedback from the first source node to the first gate, the bit line settling time may be reduced. In some cases, a first voltage applied to the first gate may be determined based on a first current drawn from the first bit line. Thus, the first voltage applied to the first gate may vary over time depending on the conductivity of a selected memory cell connected to the bit line. | 11-27-2014 |
20150023113 | COMPENSATION SCHEME FOR NON-VOLATILE MEMORY - Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell. | 01-22-2015 |
20150023115 | COMPENSATION SCHEME FOR NON-VOLATILE MEMORY - Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell. | 01-22-2015 |
Patent application number | Description | Published |
20100130013 | SLURRY COMPOSITION FOR GST PHASE CHANGE MEMORY MATERIALS POLISHING - A CMP method for polishing a phase change alloy on a substrate surface including positioning the substrate comprising a phase change alloy material on a platen containing a polishing pad and delivering a polishing slurry to the polishing pad. The polishing slurry includes colloidal particles with a particle size less than 60 nm, in an amount between 0.2% to about 10% by weight of slurry, a pH adjustor, a chelating agent, an oxidizing agent in an amount less than 1% by weight of slurry, and polyacrylic acid. The substrate on the platen is polished to remove a portion of the phase change alloy. A rinsing solution for rinsing the substrate on the platen includes deionized water and at least one component in the deionized water where the component selected from the group consisting of polyethylene imine, polyethylene glycol, polyacrylic amide, alcohol ethoxylates, polyacrylic acid, an azole containing compound, benzo-triazole, and combinations thereof. | 05-27-2010 |
20110265816 | DISK-BRUSH CLEANER MODULE WITH FLUID JET - Embodiments of the present invention relates to an apparatus and method for cleaning a substrate using a disk brush. One embodiment provides a substrate cleaner comprising a substrate chuck disposed in the processing volume, and a brush assembly disposed in the processing volume, wherein the brush assembly comprises a disk brush movably disposed opposing the substrate chuck, and a processing surface of the disk brush contacts a surface of the substrate on the substrate chuck. | 11-03-2011 |
20130186850 | SLURRY FOR COBALT APPLICATIONS - A slurry for chemical mechanical of a cobalt layer or a conductive layer over a cobalt layer includes abrasive particles, an organic complexing compound for Cu or Co ion complexion, a Co corrosion inhibitor that is 0.01-1.0 wt % of the slurry, an oxidizer, and a solvent. The slurry has a pH of 7-12. | 07-25-2013 |
20130189843 | SLURRY FOR PLANARIZING PHOTORESIST - A slurry for planarization of a photoresist includes abrasive particles, an oxidizer, a surface activation chemical, and a solvent. | 07-25-2013 |
Patent application number | Description | Published |
20090175907 | Multi Plasmid System For The Production Of Influenza Virus - Vectors and methods for the production of influenza viruses suitable as recombinant influenza vaccines in cell culture are provided. Bi-directional expression vectors for use in a multi-plasmid influenza virus expression system are provided. Additionally, the invention provides methods of producing influenza viruses with enhanced ability to replicate in embryonated chicken eggs and/or cells (e.g., Vero and/or MDCK) and further provides influenza viruses with enhanced replication characteristics. A method of producing a cold adapted (ca) influenza virus that replicates efficiently at, e.g., 25° C. (and immunogenic compositions comprising the same) is also provided. | 07-09-2009 |
20090246225 | Methods of Producing Influenza Vaccine Compositions - Methods and compositions for the optimization of production of influenza viruses suitable as influenza vaccines are provided. | 10-01-2009 |
20100322969 | INFLUENZA B VIRUSES HAVING ALTERATIONS IN THE HEMAGLUTININ POLYPEPTIDE - The present invention encompasses methods of producing influenza B viruses in cell culture. The influenza B viruses may have desirable characteristics, such as enhanced replication in eggs and may be used, for example, in vaccines and in methods of treatment to protect against influenza B virus infection. | 12-23-2010 |
20120288521 | MULTI PLASMID SYSTEM FOR THE PRODUCTION OF INFLUENZA VIRUS - Vectors and methods for the production of influenza viruses suitable as recombinant influenza vaccines in cell culture are provided. Bi-directional expression vectors for use in a multi-plasmid influenza virus expression system are provided. Additionally, the invention provides methods of producing influenza viruses with enhanced ability to replicate in embryonated chicken eggs and/or cells (e.g., Vero and/or MDCK) and further provides influenza viruses with enhanced replication characteristics. A method of producing a cold adapted (ca) influenza virus that replicates efficiently at, e.g., 25° C. (and immunogenic compositions comprising the same) is also provided. | 11-15-2012 |
20130115235 | SWINE INFLUENZA HEMAGGLUTININ VARIANTS - The technology relates in part to modified influenza viruses useful for vaccine development. Polypeptides, polynucleotides, methods, compositions, and vaccines comprising influenza hemagglutinin and neuraminidase variants are provided. | 05-09-2013 |
20140134208 | MULTI PLASMID SYSTEM FOR THE PRODUCTION OF INFLUENZA VIRUS - Vectors and methods for the production of influenza viruses suitable as recombinant influenza vaccines in cell culture are provided. Bi-directional expression vectors for use in a multi-plasmid influenza virus expression system are provided. Additionally, the invention provides methods of producing influenza viruses with enhanced ability to replicate in embryonated chicken eggs and/or cells (e.g., Vero and/or MDCK) and further provides influenza viruses with enhanced replication characteristics. A method of producing a cold adapted (ca) influenza virus that replicates efficiently at, e.g., 25° C. (and immunogenic compositions comprising the same) is also provided. | 05-15-2014 |
20140199683 | INFLUENZA B VIRUSES HAVING ALTERATIONS IN THE HEMAGLUTININ POLYPEPTIDE - The present invention encompasses methods of producing influenza B viruses in cell culture. The influenza B viruses may have desirable characteristics, such as enhanced replication in eggs and may be used, for example, in vaccines and in methods of treatment to protect against influenza B virus infection. | 07-17-2014 |