Patent application number | Description | Published |
20090219776 | NON-VOLATILE MEMORY DEVICE WITH PLURAL REFERENCE CELLS, AND METHOD OF SETTING THE REFERENCE CELLS - A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells. | 09-03-2009 |
20120257465 | Non-volatile Memory Device With Plural Reference Cells, And Method Of Setting The Reference Cells - A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells. | 10-11-2012 |
20120324276 | INTELLIGENT BIT RECOVERY FOR FLASH MEMORY - A method and system intelligent bit recovery is provided. The intelligent bit recovery determines which bits are toggling, and examines a subset of the potential bit patterns to determine which in the subset of potential bit patterns is valid. The subset is a fraction of the potential bit patterns, and is based on an understanding of the flash memory and the problems that may cause the toggling bits. The intelligent bit recovery may analyze at least one aspect of the flash memory to identify which problem is potentially causing the toggling bits, and to select the subset of potential bit patterns as solutions for the determined problem. Or, the intelligent bit recovery selects potential bit patterns for multiple potential problems. In either way, the subset of potential bit patterns examined by the intelligent bit recovery is a small fraction of the entire set of potential bit patterns. | 12-20-2012 |
20130132804 | Systems, Methods and Devices for Decoding Codewords Having Multiple Parity Segments - An error control decoding system decodes a codeword that includes a data word and two or more parity segments. The system includes a first decoder to decode the codeword by utilizing one or more first parity segments and the data word included in the codeword, and a second decoder to decode the codeword by utilizing one or more second parity segments and the data word included in the codeword, wherein the one or more first parity segments are different from the one or more second parity segments. An error estimation module estimates the number of errors in the codeword, and a controller selects which of the first decoder and second decoder to start decoding the codeword, wherein the selection is based on the estimate of the number of errors in the codeword provided by the error estimation module. | 05-23-2013 |
20130145229 | Systems, Methods and Devices for Multi-Tiered Error Correction - An error control encoding system produces a codeword from a data word, where the resulting codeword includes the data word and three or more parity segments produced using the data word. The system includes a first encoder to encode the data word in two or more first data segments in order to produce two or more first parity segments, where each of the two or more first data segments includes a respective sequential portion of the data word. The system includes a second encoder to encode the data word in one or more second data segments in order to produce a corresponding one or more second parity segments, where each of the one or more second data segments includes a respective sequential portion of the data word, and each of the one or more second data segments also includes a sequential portion of the data included in a plurality of the two or more first data segments. Further, the system includes a controller configured to provide the two or more first data segments of the data word to the first encoder for encoding and to provide the one or more second data segments of the data word to the second encoder for encoding. | 06-06-2013 |
20130145231 | Data Encoder and Decoder Using Memory-Specific Parity-Check Matrix - An error control system uses an error control code that corresponds to an error density location profile of a storage medium. The system includes an encoder configured to produce one or more codewords from data using an error control code generator matrix corresponding to the error density location profile of the storage medium. The system also includes a decoder configured to produce decoded data from one or more codewords using an error control code parity-check matrix corresponding to the error density location profile of the storage medium, where columns of the parity-check matrix are associated with corresponding data bits of the storage medium, rows of the parity-check matrix are associated with check bits, and each matrix element of the parity-check matrix having a predefined value indicates a connection between a particular data bit and a particular check bit. | 06-06-2013 |
20140104961 | Non-volatile Memory Device With Plural Reference Cells, And Method Of Setting The Reference Cells - A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells. | 04-17-2014 |
20140281044 | Performance Optimization of Data Transfer for Soft Information Generation - A single command initiates a first read operation and sequence of one or more additional read operations from the same portion of memory. The one or more additional read operations are terminable after the first read operation provides a first plurality of data values that is made available to a requesting device and/or module. In some implementations, the first plurality of data values includes hard information values. Subsequent pluralities of data values are generated from the same portion of memory until a terminating event occurs. In some implementations, until a terminating event occurs, a respective hybrid plurality of data values is generated by combining the latest read plurality of data values with one of a previously generated hybrid plurality of data values and the first plurality of data values. Each hybrid plurality of data values is representative of a corresponding plurality of soft information values. | 09-18-2014 |
20150364215 | Low-Test Memory Stack for Non-Volatile Storage - The various embodiments described herein include systems, methods and/or devices used to package non-volatile memory. In one aspect, the method includes: (1) selecting, from a set of non-volatile memory die, a plurality of non-volatile memory die on which one or more tests have been deferred until after packaging, the selecting in accordance with wafer positions of the plurality of non-volatile memory die and statistical die performance information corresponding to the wafer positions; and (2) packaging the selected plurality of non-volatile memory die. In some embodiments, after said packaging, the method further includes performing a set of tests on the plurality of non-volatile memory die to identify respective units of memory within the plurality of non-volatile memory die that meet predefined validity criteria, wherein the set of tests performed include at least one of the deferred one or more tests. | 12-17-2015 |
20150364218 | Non-Volatile Memory Module with Physical-To-Physical Address Remapping - The various embodiments described herein include systems, methods and/or devices used to enable physical-to-physical address remapping in a storage module. In one aspect, the method includes, for each of a sequence of two or more units of non-volatile memory, determining a validity state of a respective unit of memory. In accordance with a determination that the validity state of the respective unit of memory is an invalid state, the method includes storing, in a table, a second address assigned to the respective unit of memory. At least a portion of the second address is a physical address portion corresponding to a physical location of a second unit of memory. In accordance with a determination that the validity state of the respective unit of memory is a valid state, the method includes forgoing assignment of the second address corresponding to the unit of memory. | 12-17-2015 |