Hsieh, Tainan
Cheng-Chieh Hsieh, Tainan TW
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20150348877 | Contact Pad for Semiconductor Device - A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound. | 12-03-2015 |
Cheng-Yu Hsieh, Tainan TW
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20100134683 | SIGNAL PROCESSING DEVICE AND METHOD - A signal processing device with high efficiency of teletext information processing is provided. The signal processing device is configured to receive and encode a transport stream for display, wherein the transport stream provides teletext information associated with a plurality of teletext lines and video information associated with a plurality of video lines. The video signal processing device includes a memory configured to store line enable signals and line data associated with the teletext lines and the video lines, a VBI controller coupled to the memory, configured to read the memory to obtain the line data associated with enabled teletext lines of the teletext lines, and an TV encoder coupled to the VBI controller, configured to receive and encode the line data associated with the enabled teletext lines for display. | 06-03-2010 |
20100232511 | MOTION COMPENSATOR, MOTION COMPENSATING METHOD, AND MOTION-COMPENSATED VIDEO DECODER IMPLEMENTING THE SAME - A motion compensating method for a motion-compensated video decoder, the motion compensated video decoder having an entropy decoder for generation of MV information and MB modes, the motion compensating method includes selectively combining adjacent partitions within a macroblock in response to the MV information, and update the MV information and MB modes in response to the combination, and creating a predicted macroblock in response to the most updated MV information and MB modes. | 09-16-2010 |
Chen-Han Hsieh, Tainan TW
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20100309672 | Clamping member for connecting light cover to light housing - A light assembly includes a housing including two frames and two covers are respectively connected to the frames by multiple clamping members. Each of the frames includes at least one first wall which has at least one notch defined therein and each of the covers includes at least one second wall which includes at least one slot. Multiple clamping members connect the covers to the frames and each clamping member includes a first plate, two second plates and a connection portion connected between the first and second plates. A positioning plate extends from the connection portion and includes a ridge extending therefrom. The at least one first wall of each frame is located between the first and second plates and the positioning plate is located within the at least one notch and the ridge is engaged with the at least one slot of the at least one cover. | 12-09-2010 |
Chia-Ta Hsieh, Tainan TW
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20090035902 | INTEGRATED METHOD OF FABRICATING A MEMORY DEVICE WITH REDUCED PITCH - Provided is a method of fabricating a memory device. A substrate including an array region and a peripheral region is provided. A first feature and a second feature are formed in the array region. The first feature and the second feature have a first pitch. A plurality of spacers abutting each of the first feature and the second feature are formed. The plurality of spacers have a second pitch. A third feature in the peripheral region and a fourth and fifth feature in the array region are formed concurrently. The forth and fifth feature have the second pitch. | 02-05-2009 |
20100006974 | STORAGE NITRIDE ENCAPSULATION FOR NON-PLANAR SONOS NAND FLASH CHARGE RETENTION - The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features; forming a tunnel dielectric feature within the semiconductor region; forming a nitride layer on the recessed STI features and the tunnel dielectric feature; etching the nitride layer to form nitride openings within the recessed STI features; partially removing the recessed STI features through the nitride openings, resulting in gaps between the nitride layer and the recessed STI features; and forming a first dielectric material on surfaces of the nitride layer, sealing the nitride openings. | 01-14-2010 |
20100277986 | NON-VOLATILE FIELD PROGRAMMABLE GATE ARRAY - A non-volatile memory device includes a first metal-oxide-semiconductor (CMOS) device coupled to a bit line and a word line and a second CMOS device coupled to the first CMOS device. The second CMOS device is also coupled to a complementary bit line and a complementary word line. The first and second CMOS devices are complementary to one another. An output node is coupled between the first CMOS device and the second CMOS device. A method of programming a non-volatile field programmable gate array (NV-FPGA) includes coupling an information handling system to the FPGA, performing a block erase of a plurality of memory cells in the FPGA, verifying that the block erase is successful, programming an upper page of the FPGA, verifying that the upper page programming is successful, programming a lower page of the FPGA and verifying that the lower page programming is successful. | 11-04-2010 |
20120025869 | NON-VOLATILE FIELD PROGRAMMABLE GATE ARRAY - A non-volatile memory device includes a first metal-oxide-semiconductor (CMOS) device coupled to a bit line and a word line and a second CMOS device coupled to the first CMOS device. The second CMOS device is also coupled to a complementary bit line and a complementary word line. The first and second CMOS devices are complementary to one another. An output node is coupled between the first CMOS device and the second CMOS device. A method of programming a non-volatile field programmable gate array (NV-FPGA) includes coupling an information handling system to the FPGA, performing a block erase of a plurality of memory cells in the FPGA, verifying that the block erase is successful, programming an upper page of the FPGA, verifying that the upper page programming is successful, programming a lower page of the FPGA and verifying that the lower page programming is successful. | 02-02-2012 |
20120087188 | STRUCTURE AND INHIBITED OPERATION OF FLASH MEMORY WITH SPLIT GATE - A method of performing a reading operation to a memory device including a plurality of flash memory cells. The method includes applying a first voltage bias to a control gate of a selected memory cell in the flash memory array and applying a second voltage bias to a word line of the selected memory cell. A control gate of an unselected memory cell in the flash memory array is grounded and a third voltage bias is applied to a word line of the unselected cell to turn off a word line channel of the unselected memory cell. The selected memory cell and unselected memory cell are configured in the memory device and are connected to different word lines. The first voltage bias and the second voltage bias have a same polarity. The third voltage bias and the second voltage bias have opposite polarities. | 04-12-2012 |
20150214237 | LOGIC COMPATIBLE FLASH MEMORY AND METHODS OF FORMING THE SAME - A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate, forming a dielectric protection layer overlapping the first pad oxide layer, removing the second pad oxide layer, and forming a floating gate dielectric over the second active region. A floating gate layer is then formed to include a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric. A planarization is performed on the first portion and the second portion of the floating gate layer. A blocking layer, a control gate layer, and a hard mask layer are formed over the second portion of the floating gate layer. The hard mask layer, the control gate layer, and the blocking layer are patterned to form a gate stack for a flash memory cell. | 07-30-2015 |
Chih-Ming Hsieh, Tainan TW
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20080229526 | System for cleaning a wafer - A system for cleaning a wafer. At least one first chuck roller is connected to a first roller base and includes a first annular groove. A second roller base opposes the first roller base. At least one second chuck roller is connected to the second roller base and includes a second annular groove. A sensing chuck roller is connected to the second roller base and includes a third annular groove corresponding to the first and second annular grooves. A cleaning member covers the third annular groove. A circumferential edge of the wafer is positioned in the first and second annular grooves and abuts the cleaning member. The first and second chuck rollers rotate the wafer, enabling the circumferential edge thereof to rub against the cleaning member. | 09-25-2008 |
Chu Yang Hsieh, Tainan TW
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20110262372 | Lactobacillus Fermentum SG-A95 for Improving Oral Bacterial Groups and Health Care Compositions Thereof - The present invention provides a strain of | 10-27-2011 |
20110318281 | Lactobacillus Salivarius SG-M6 for Improving Oral Bacterial Groups and Health Care Compositions Thereof - This invention provides to a strain of | 12-29-2011 |
Hung-Ting Hsieh, Tainan TW
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20140324898 | SYSTEM AND METHOD FOR SEARCHING ALIASES ASSOCIATED WITH AN ENTITY - A search system for collecting aliases associated with an entity name, includes a storage module configured to store at least one first lexical pattern, a search module coupled to the storage module and configured to obtain a plurality of first snippets from a database according to the entity name, and an alias extracting module coupled to the storage module and the search module separately and configured to, according to the entity name and the first lexical pattern, determine whether any first alias exists in the first snippets. If a first alias exists, the alias extracting module extracts it out and stores it in the storage module. | 10-30-2014 |
Min-Fu Hsieh, Tainan TW
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20140159512 | STATOR STRUCTURE - A stator structure includes a main body having multiple frames each having an arc panel, a main tooth, at least one secondary tooth, at least one main coil and at least one secondary coil. The main tooth and the secondary tooth are disposed at one face of the arc panel. The main coil is installed at the main tooth, and the secondary coil is installed at the secondary coil. A rotor is penetrated through the stator structure. The frames are in a multi-layer circular arrangement at the rotor, and a dislocation angle exists between the frame at any layer and the frame at the neighboring layer. | 06-12-2014 |
Ping Hsieh, Tainan TW
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20110198894 | Chair with electrically adjustable components - An adjustable chair ( | 08-18-2011 |
Tsung-Jung Hsieh, Tainan TW
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20150051866 | METHOD FOR OPTIMIZING PHASOR MEASUREMENT UNIT PLACEMENT - A method for optimizing phasor measurement unit placement includes two phase, calculating a degree of each node of a power system; selecting a node with maximum degree as a center and propagate to the entire power system so as to form a spanning tree; selecting a feasible power dominating set (PDS) of minimum cardinality for the spanning tree in the Phase I. In phase II, use the Artificial Bees Colony Algorithm. According to the minimum PDS, calculating a fitness functions by the equation | 02-19-2015 |
Wei-Hsin Hsieh, Tainan TW
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20090169045 | Display Device with Hidden Speaker Assemblies - A display device includes a display panel, a frame, and a speaker unit. The frame encloses a periphery of the display panel. The speaker unit includes a speaker housing and a speaker assembly. The speaker housing includes first and second housing parts. The first housing part is connected to the frame, has a front opening, and is formed with a hole. The second housing part is mounted on a rear side of the display panel, defines a chamber, and has an open end. The open end of the second housing part is connected to the first housing part such that the chamber in the second housing part is in spatial communication with the front opening in the first housing part through the hole. The speaker assembly is disposed in the chamber in the second housing part and is coupled electrically to the display panel. | 07-02-2009 |
Yi-Hsun Hsieh, Tainan TW
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20150180325 | ELECTROLYTIC CAPACITOR-LESS AC/DC CONVERTER AND CONTROLLING METHOD THEREOF - An AC/DC converter is disclosed. The proposed AC/DC converter generates an output voltage and includes a current ripple eliminator having an input terminal, an energy storage capacitor and an output terminal, wherein the input terminal has an input voltage, the output terminal generates a pure AC component of a voltage feedback signal based on the output voltage, when the input voltage is larger than a first reference voltage, the energy storage capacitor stores a difference between the input voltage and the first reference voltage as an electric energy, otherwise, the energy storage capacitor releases the electric energy to the input voltage, and an operational amplifier operating the AC component and a second reference voltage to determine when the storage capacitor should store or release the electric energy to minimize a ripple of an output power thereof. | 06-25-2015 |
Yun Che Hsieh, Tainan TW
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20100107934 | Intensive pallet - An intensive pallet and a unit direction plank for the same are provided, and the pallet comprises a plurality of first direction planks spaced from each other and a plurality of second direction planks spaced from each other. The second direction plank and the first direction plank stack and cross. Two frame holes are formed in each unit of first direction plank. One frame hole communicates with a next spaced frame hole of the unit first direction plank. A plurality of first ribs are formed at the top side of each frame hole. The frame holes may be inserted by the insertion levers of a forklift. The first ribs are provided to enhance the top sides of frame holes into which the levers are inserted. | 05-06-2010 |