Patent application number | Description | Published |
20080280413 | METHODS FOR FORMING A TRANSISTOR - Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon carbide material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon carbide material to form a source/drain region having a second conductivity. | 11-13-2008 |
20080290470 | Integrated Circuit On Corrugated Substrate - By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance. | 11-27-2008 |
20080296698 | METHOD FOR SUPPRESSING LAYOUT SENSITIVITY OF THRESHOLD VOLTAGE IN A TRANSISTOR ARRAY - A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout. Such recombination surfaces are treated to affect the recombination of interstitial atoms adjacent such surfaces, thus minimizing variations in threshold voltage of transistors within the layout | 12-04-2008 |
20080297237 | METHOD FOR COMPENSATION OF PROCESS-INDUCED PERFORMANCE VARIATION IN A MOSFET INTEGRATED CIRCUIT - An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing. | 12-04-2008 |
20080299735 | METHODS FOR FORMING A TRANSISTOR - Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon-germanium material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon-germanium material to form a source/drain region having a second conductivity. | 12-04-2008 |
20080301599 | METHOD FOR RAPID ESTIMATION OF LAYOUT-DEPENDENT THRESHOLD VOLTAGE VARIATION IN A MOSFET ARRAY - An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations. | 12-04-2008 |
20090007043 | Managing Integrated Circuit Stress Using Dummy Diffusion Regions - Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors. | 01-01-2009 |
20090064072 | METHOD AND APPARATUS FOR PLACING AN INTEGRATED CIRCUIT DEVICE WITHIN AN INTEGRATED CIRCUIT LAYOUT - A system that places an integrated circuit (IC) device within an IC chip layout is presented. During operation, the system receives the IC device to be placed within the IC chip layout, wherein the IC chip layout includes one or more continuous rows of diffusion. Next, the system places the IC device within a continuous row of diffusion. The system then determines whether the IC device is to be electrically isolated from other IC devices. If so, the system inserts one or more isolation devices within the continuous row of diffusion so that the IC device can be electrically isolated from other IC devices. The system then biases the one or more isolation device so that the IC device is electrically isolated from other IC devices within the continuous row of diffusion. | 03-05-2009 |
20090083688 | METHOD AND APPARATUS FOR GENERATING A LAYOUT FOR A TRANSISTOR - A system that generates a layout for a transistor is presented. During operation, the system receives a transistor library which includes operating characteristics of fabricated transistors correlated to transistor gate shapes. The system also receives one or more desired operating characteristics for the transistor. Next, the system determines a transistor gate shape for the transistor based on the transistor library so that a fabricated transistor with the transistor gate shape substantially achieves the one or more desired operating characteristics. The system then generates the layout for the transistor which includes the transistor gate shape. | 03-26-2009 |
20090108293 | Method for Suppressing Lattice Defects in a Semiconductor Substrate - A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer. | 04-30-2009 |
20090108408 | Method for Trapping Implant Damage in a Semiconductor Substrate - A method for minimizing the effects of defects produced in a implantated area of a crystal lattice during dopant implantation in the lattice. The method begins with the step of implanting a trap layer of trap atoms, the trap atoms having a size less than that of the lattice member atoms. After implantation, the lattice is annealed for a time sufficient for interstitial defect atoms to be emitted from the defect area. In that manner, energetically stable pairs are formed between trap atoms and emitted interstitial atoms. | 04-30-2009 |
20090217217 | METHOD OF CORRELATING SILICON STRESS TO DEVICE INSTANCE PARAMETERS FOR CIRCUIT SIMULATION - Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard, stress-sensitive, transistor model is used to develop a mathematical relationship between the first transistor performance measure and one or more instance parameters that are available as inputs to a second, stress-insensitive, transistor model. The second transistor model may for example be the same as the first model, with its stress sensitivity disabled. Thereafter, a substitute stress analyzer can be used to determine a stress-adjusted value for the first performance measure, and the mathematical relationship can be used to convert that value into specific values for the one or more instance parameters. These values are then provided to the second transistor model for use in simulating the characteristics of the particular transistor during circuit simulation. | 08-27-2009 |
20090236673 | METHOD FOR SUPPRESSING LAYOUT SENSITIVITY OF THRESHOLD VOLTAGE IN A TRANSISTOR ARRAY - A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout. Such recombination surfaces are treated to affect the recombination of interstitial atoms adjacent such surfaces, thus minimizing variations in threshold voltage of transistors within the layout | 09-24-2009 |
20090288048 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 11-19-2009 |
20090288049 | Method for Rapid Estimation of Layout-Dependent Threshold Voltage Variation in a MOSFET Array - An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations. | 11-19-2009 |
20090313595 | STRESS-MANAGED REVISION OF INTEGRATED CIRCUIT LAYOUTS - Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors. | 12-17-2009 |
20100019317 | Managing Integrated Circuit Stress Using Stress Adjustment Trenches - Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors. | 01-28-2010 |
20100023899 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 01-28-2010 |
20100023900 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 01-28-2010 |
20100023901 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 01-28-2010 |
20100023902 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 01-28-2010 |
20100024978 | STRESS ENGINEERING FOR CAP LAYER INDUCED STRESS - Improved layouts take better advantage of desirable cap-layer induced transverse and vertical stress. In one aspect, roughly described, a tensile strained cap material overlies the transistor channels in the N-channel diffusion regions but not the P-channel diffusion regions. The material terminates at an edge that is located as far as practical from the N-channel diffusion, toward the P-channel diffusion. In another aspect, roughly described, a gate conductor crosses a P-channel diffusion region and terminates as far as practical beyond the edge without making undesirable electrical contact with any other features of the integrated circuit design, and without overlying any other diffusion regions. A compressively strained cap layer overlies the P-channel diffusion. In yet another aspect, roughly described, a gate conductor crosses an N-channel diffusion and extends by as short a distance as practical before terminating or turning. A tensile strained cap material overlies the N-channel diffusion. | 02-04-2010 |
20100025777 | METHOD FOR SUPPRESSING LATTICE DEFECTS IN A SEMICONDUCTOR SUBSTRATE - A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer. | 02-04-2010 |
20100029050 | STRESS ENGINEERING FOR CAP LAYER INDUCED STRESS - Improved layouts take better advantage of desirable cap-layer induced transverse and vertical stress. In one aspect, roughly described, a tensile strained cap material overlies the transistor channels in the N-channel diffusion regions but not the P-channel diffusion regions. The material terminates at an edge that is located as far as practical from the N-channel diffusion, toward the P-channel diffusion. In another aspect, roughly described, a gate conductor crosses a P-channel diffusion region and terminates as far as practical beyond the edge without making undesirable electrical contact with any other features of the integrated circuit design, and without overlying any other diffusion regions. A compressively strained cap layer overlies the P-channel diffusion. In yet another aspect, roughly described, a gate conductor crosses an N-channel diffusion and extends by as short a distance as practical before terminating or turning. A tensile strained cap material overlies the N-channel diffusion. | 02-04-2010 |
20100042958 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 02-18-2010 |
20100187609 | BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS - Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate. | 07-29-2010 |
20100270597 | METHOD AND APPARATUS FOR PLACING TRANSISTORS IN PROXIMITY TO THROUGH-SILICON VIAS - Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone. | 10-28-2010 |
20100274376 | Method and Apparatus for Performing Stress Modeling of Integrated Circuit Material Undergoing Material Conversion - A method, a computer medium storing computer instructions performing a method, and a computer with processor and memory perform stress modeling as follows. The stress model transforms a representation of a material conversion of a first material in the integrated circuit to a second material in the integrated circuit. Prior to the material conversion the first material occupies a first space having a first boundary. After the material conversion the first material and the second material together occupy a second space having a second boundary. The first space and the second space are different. The stress model performed by the computer system transforms the representation of the material conversion of the first material to the second material into: i) the first material occupying the first space having the first boundary, and ii) a strain displacement condition of the first material. The strain displacement condition is determined by a spatial change from the first boundary to the second boundary. | 10-28-2010 |
20110169140 | RECLAIMING USABLE INTEGRATED CIRCUIT CHIP AREA NEAR THROUGH-SILICON VIAS - Roughly described, an integrated circuit device includes a substrate including a via passing therethrough, a strained electrically conductive first material in the via, the first material tending to introduce first stresses into the substrate, and a strained second material in the via, the second material tending to introduce second stresses into the substrate which at least partially cancel the first stresses. In an embodiment, SiGe is grown epitaxially on the inside sidewall of the via in the silicon wafer. SiO2 is then formed on the inside surface of the SiGe, and metal is formed down the center. The stresses introduce by the SiGe tend to counteract the stresses introduced by the metal, thereby reducing or eliminating undesirable stress in the silicon and permitting the placement of transistors in close proximity to the TSV. | 07-14-2011 |
20110219351 | Method for Compensation of Process-Induced Performance Variation in a Mosfet Integrated Circuit - An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing. | 09-08-2011 |
20110309453 | ELEVATION OF TRANSISTOR CHANNELS TO REDUCE IMPACT OF SHALLOW TRENCH ISOLATION ON TRANSISTOR PERFORMANCE - Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions. | 12-22-2011 |
20120011479 | BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS - Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate. | 01-12-2012 |
20120280354 | METHODS FOR FABRICATING HIGH-DENSITY INTEGRATED CIRCUIT DEVICES - An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process. | 11-08-2012 |
20130026571 | N-CHANNEL AND P-CHANNEL FINFET CELL ARCHITECTURE WITH INTER-BLOCK INSULATOR - A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks. | 01-31-2013 |
20130026572 | N-CHANNEL AND P-CHANNEL FINFET CELL ARCHITECTURE - A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions. | 01-31-2013 |
20130026575 | THRESHOLD ADJUSTMENT OF TRANSISTORS BY CONTROLLED S/D UNDERLAP - Roughly described, an integrated circuit device has formed on a substrate a plurality of transistors including a first subset of at least one transistor and a second subset of at least one transistor, wherein all of the transistors in the first subset have one underlap distance and all of the transistors in the second subset have a different underlap distance. The transistors in the first and second subsets preferably have different threshold voltages, and preferably realize different points on the high performance/low power tradeoff. | 01-31-2013 |
20130026607 | INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE AND METHODS FOR MANUFACTURING THE SAME - A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material. | 01-31-2013 |
20130065380 | METHODS FOR MANUFACTURING INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE - A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall surface does not carry the sidewall surface variations introduced by photolithographic processes, or other patterning processes, involved in forming the mask element and etching the line. | 03-14-2013 |
20130113547 | Method and apparatus for floating or applying voltage to a well of an integrated circuit - In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well. | 05-09-2013 |
20130125075 | METHOD FOR RAPID ESTIMATION OF LAYOUT-DEPENDENT THRESHOLD VOLTAGE VARIATION IN A MOSFET ARRAY - An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations. | 05-16-2013 |
20130132914 | Method and Apparatus for Placing Transistors In Proximity to Through-Silicon Vias - Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone. | 05-23-2013 |
20130334610 | N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE WITH RELAXED GATE PITCH - A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements. | 12-19-2013 |
20130334613 | N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE - A finFET block architecture uses end-to-end finFET blocks. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. An inter-block isolation structure separates the semiconductor fins in the first and second sets. The ends of the fins in the first set are proximal to a first side of the inter-block isolation structure and ends of the fins in the second set are proximal to a second side of the inter-block isolation structure. A patterned gate conductor layer includes a first gate conductor extending across at least one fin in the first set of semiconductor fins, and a second gate conductor extending across at least one fin in the second set of semiconductor fins. The first and second gate conductors are connected by an inter-block conductor. | 12-19-2013 |
20140003133 | SRAM LAYOUTS | 01-02-2014 |
20140015135 | SELF-ALIGNED VIA INTERCONNECT USING RELAXED PATTERNING EXPOSURE - Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for second metal traces on a second metal layer, vertically adjacent to the first metal layer and accessing a precise pattern of intended interconnections between the first and second metal traces. The precise pattern of intended interconnections is operated on to form an imprecise via pattern that indicates a plurality of general areas in which vias are allowed. The imprecise via pattern is for use in an integrated circuit manufacturing process to form, in conjunction with operations to form the first and second metal layers, a plurality of self-aligned vias for interconnecting the intended interconnections. | 01-16-2014 |
20140035053 | FINFET CELL ARCHITECTURE WITH INSULATOR STRUCTURE - A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks. | 02-06-2014 |
20140054722 | FINFET CELL ARCHITECTURE WITH POWER TRACES - A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions. | 02-27-2014 |
20140061936 | LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS - Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described. | 03-06-2014 |
20140065821 | LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS - Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described. | 03-06-2014 |
20140115556 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 04-24-2014 |
20140154855 | METHOD AND APPARATUS WITH CHANNEL STOP DOPED DEVICES - Methods and apparatuses relate to implanting a surface of a semiconductor substrate with dopants, making undoped semiconductor material directly on the surface implanted with the dopants, and making a transistor with a transistor channel in the undoped semiconductor material, such that the transistor channel of the transistor remains undoped throughout manufacture of the integrated circuit. | 06-05-2014 |
20140167174 | INCREASING ION/IOFF RATIO IN FINFETS AND NANO-WIRES - Roughly described, an integrated circuit transistor structure has a body of semiconductor material, the body having two longitudinally spaced doped source/drain volumes with a channel between, a gate stack disposed outside the body and facing at least one of the surfaces of the body along the channel. The body contains an adjustment volume, longitudinally within the channel volume and spaced behind the first surface by a first distance and spaced longitudinally from both the source/drain volumes. The adjustment volume comprises an adjustment volume material having, at each longitudinal position, an electrical conductivity which differs from that of the adjacent body material at the same longitudinal position, at least while the transistor is in an off-state. In one embodiment the adjustment volume material is a dielectric. In another embodiment the adjustment volume material is an electrical conductor. | 06-19-2014 |
20140173545 | PLACING TRANSISTORS IN PROXIMITY TO THROUGH-SILICON VIAS - Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone. | 06-19-2014 |
20140217514 | N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE WITH RELAXED GATE PITCH - A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements. | 08-07-2014 |
20140223394 | METHODS FOR MANUFACTURING INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE - A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall surface does not carry the sidewall surface variations introduced by photolithographic processes, or other patterning processes, involved in forming the mask element and etching the line. | 08-07-2014 |
20140223395 | BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS - Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate. | 08-07-2014 |
20140284727 | Integrated Circuit On Corrugated Substrate - By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance. | 09-25-2014 |
20140367855 | Self-Aligned Via Interconnect Using Relaxed Patterning Exposure - Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for second metal traces on a second metal layer, vertically adjacent to the first metal layer and accessing a precise pattern of intended interconnections between the first and second metal traces. The precise pattern of intended interconnections is operated on to form an imprecise via pattern that indicates a plurality of general areas in which vias are allowed. The imprecise via pattern is for use in an integrated circuit manufacturing process to form, in conjunction with operations to form the first and second metal layers, a plurality of self-aligned vias for interconnecting the intended interconnections. | 12-18-2014 |
20150041921 | INCREASING ION/IOFF RATIO IN FINFETS AND NANO-WIRES - Roughly described, an integrated circuit transistor structure has a body of semiconductor material, the body having two longitudinally spaced doped source/drain volumes with a channel between, a gate stack disposed outside the body and facing at least one of the surfaces of the body along the channel. The body contains an adjustment volume, longitudinally within the channel volume and spaced behind the first surface by a first distance and spaced longitudinally from both the source/drain volumes. The adjustment volume comprises an adjustment volume material having, at each longitudinal position, an electrical conductivity which differs from that of the adjacent body material at the same longitudinal position, at least while the transistor is in an off-state. In one embodiment the adjustment volume material is a dielectric. In another embodiment the adjustment volume material is an electrical conductor. | 02-12-2015 |
20150041924 | N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE - A finFET block architecture uses end-to-end finFET blocks. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. An inter-block isolation structure separates the semiconductor fins in the first and second sets. The ends of the fins in the first set are proximal to a first side of the inter-block isolation structure and ends of the fins in the second set are proximal to a second side of the inter-block isolation structure. A patterned gate conductor layer includes a first gate conductor extending across at least one fin in the first set of semiconductor fins, and a second gate conductor extending across at least one fin in the second set of semiconductor fins. The first and second gate conductors are connected by an inter-block conductor. | 02-12-2015 |
20150088473 | SIMULATION SCALING WITH DFT AND NON-DFT - Electronic design automation modules for simulate the behavior of structures and materials at multiple simulation scales with different simulation modules. | 03-26-2015 |
20150088481 | ITERATIVE SIMULATION WITH DFT AND NON-DFT - Electronic design automation modules for simulate the behavior of structures and materials at multiple simulation scales with different simulation modules. | 03-26-2015 |
20150088803 | CHARACTERIZING TARGET MATERIAL PROPERTIES BASED ON PROPERTIES OF SIMILAR MATERIALS - Roughly described, a technique for approximating a target property of a target material is provided. For each material in a plurality of anchor materials, a correspondence is provided between the value for a predetermined index property of the material and a value for the target property of the material, the values of all the index properties being different. A predictor function is identified in dependence upon the correspondence. A computer system determines a value for the target property for the target material in dependence upon the predictor function and a value for the index property for the target material. The determined value for the target property for the target material is reported to a user. The correspondence can be provided in a database on a non-transitory computer readable medium. The correspondence can be determined experimentally or analytically for each material in a plurality of anchor materials. | 03-26-2015 |
20150089511 | ADAPTIVE PARALLELIZATION FOR MULTI-SCALE SIMULATION - Roughly described, a task control system for managing multi-scale simulations receives a case/task list which identifies cases to be evaluated, at least one task for each of the cases, and dependencies among the tasks. A module allocates available processor cores to at least some of the tasks, constrained by the dependencies, and initiates execution of the tasks on allocated cores. A module, in response to completion of a particular one of the tasks, determines whether or not the result of the task warrants stopping or pruning tasks, and if so, then terminates or prunes one or more of the uncompleted tasks in the case/task list. A module also re-allocates available processor cores to pending not-yet-executing tasks in accordance with time required to complete the tasks and constrained by the dependencies, and initiates execution of the tasks on allocated cores. | 03-26-2015 |