Patent application number | Description | Published |
20080320066 | Cryptographic random number generator using finite field operations - An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations to the signals to generate an output, and to provide an output signal based on the output via an output channel, in this illustrative embodiment. | 12-25-2008 |
20110067982 | MEMS-BASED SWITCHING - A MEMS-based switching device may be used to implement an interconnect switch in a programmable integrated circuit device. Such a MEMS-based device may include a deformable cantilever that may form a closed or open circuit to thereby implement switching functionality. | 03-24-2011 |
20110099454 | Low Complexity LDPC Encoding Algorithm - A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B′x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B′ is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form | 04-28-2011 |
20110173510 | Parallel LDPC Decoder - An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations. | 07-14-2011 |
20120161093 | Via-Configurable High-Performance Logic Block Architecture - A via-configurable circuit block may contain chains of p-type and n-type transistors that may or may not be interconnected by means of configurable vias. Configurable vias may also be used to connect various transistor terminals to a ground line, a power line and/or to various terminals that may provide connections outside of the circuit block. | 06-28-2012 |
20120278372 | Cryptographic Random Number Generator Using Finite Field Operations - An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations to the signals to generate an output, and to provide an output signal based on the output via an output channel, in this illustrative embodiment. | 11-01-2012 |
20140028348 | Via-Configurable High-Performance Logic Block Involving Transistor Chains - A via-configurable logic block architecture for a Structured ASIC has a plurality of MOSFET transistor chains connected to one another through vias. In one embodiment there are three chains and the first transistor chain is a NFET transistor chain, the second transistor chain is a PFET transistor chain, and the third transistor chain is a NFET transistor chain. The first, second and third transistor chains are formed into devices made of transistors that are selected from a voltage threshold group consisting of LVT, SVT and HVT devices, where the first and third transistor chains are formed into devices from a voltage threshold group that is different from one another. In another embodiment transistor drive strength may be varied in the transistor chains of the logic block. In yet another embodiment both voltage threshold and drive strength may be varied together in a symmetrical manner. | 01-30-2014 |
20140103985 | Digitally Controlled Delay Line for a Structured ASIC Having a Via Configurable Fabric for High-Speed Interface - A Digitally Controlled Delay Line (DCDL) for a Structured ASIC chip is used to delaying input or output signals into or out of core logic in a Structured ASIC. The DCDL has a multi-stage configuration that in a preferred embodiment comprises two fine delay stages for fine tuning the delay using sub-gate delay through an inverter whose delay can be adjusted with parallel CMOS transistors whose gates are biased with a voltage control signal that is thermometer coded. The fine-tune stages are followed by coarse delay stages that use gate-level delay. A DCDL controller outputs control signals that are Grey coded and converted to thermometer coded control signals by a Binary-to-Thermometer Decoder. The DCDL circuit block and accompanying Structured ASIC are manufactured on a 28 nm CMOS process lithographic node or smaller. A high speed routing fabric using a balanced binary tree is employed with the DCDL. | 04-17-2014 |
Patent application number | Description | Published |
20090287980 | Computational Architecture for Soft Decoding - A device for soft decoding contains a set of operational elements, each being capable of performing one of several different functions. The operational elements may be dynamically configured with input and output connections to registers, memory locations, and other operational elements to perform various steps in a soft decoding scheme. In many cases, the operational elements may be configured to operate in a pipeline mode where many sequences of operations may be performed in parallel. Some embodiments may be reconfigured at each clock cycle to perform different steps during a decoding operation. The device may be used to perform several different soft decoding schemes with the flexibility of a programmable processor but the throughput of a hardware implementation. | 11-19-2009 |
20090303093 | SYSTEMS AND METHODS FOR PIPELINED ANALOG TO DIGITAL CONVERSION - Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a pipelined analog to digital converter is disclosed that includes two or more comparators. A first of the comparators is operable to compare an analog input to a first voltage reference upon assertion of the first clock, and a second of the comparators is operable to compare the analog input to a second voltage reference upon assertion of the second clock. The pipelined analog to digital converters further include a multiplexer tree with at least a first tier multiplexer and a second tier multiplexer. The first tier multiplexer receives an output of the first comparator and an output of the second comparator, and the second tier multiplexer receives an output derived from the first tier multiplexer. The second tier multiplexer provides an output bit. A bit enable set is used as a selector input to the first tier multiplexer and the second tier multiplexer, and the bit enable set includes one or more output bits from preceding bit periods. | 12-10-2009 |
20090309770 | METHODS AND APPARATUS FOR PROGRAMMABLE DECODING OF A PLURALITY OF CODE TYPES - Methods and apparatus are provided for programmable decoding of a plurality of code types. A method is provided for decoding data encoded using one of a plurality of code types, where each of the code types correspond to a communication standard. The code type associated with the data is identified and the data is allocated to a plurality of programmable parallel decoders. The programmable parallel decoders can be reconfigured to decode data encoded using each of the plurality of code types. A method is also provided for interleaving data among M parallel decoders using a communications network. An interleaver table is employed, wherein each entry in the interleaver table identifies one of the M parallel decoders as a target decoder and a target address of a communications network for interleaved data. Data is interleaved by writing the data to the target address of the communications network. The communications network can comprise, for example, a cross-bar switch and/or one or more first-in-first-out buffers. | 12-17-2009 |
20100030835 | Variable Node Processing Unit - A variable node processing unit with N+1 inputs, having at least a first bank of two-input adders and a separate last bank of two-input adders, where the banks of adders are disposed in series. | 02-04-2010 |
20130254252 | Variable Node Processing Unit - A low-density parity check min-sum decoder including a variable node processing unit having N+1 inputs. A first bank of N+1 two-input adders each have an associated output, and at least one of the N+1 inputs go to more than two of the adders of the first bank. A second bank of N two-input adders has no adders in common with the first bank. At least one of the adders of the first bank provides its associated output to more than one adder of the second bank. The banks of adders are disposed in series. A sign module outputs a sign value produced from one of the inputs and an output from one of the adders of the second bank. N+1 outputs are provided, where one of the outputs is the sign value. | 09-26-2013 |