Patent application number | Description | Published |
20100198690 | Event information tracking and communication tool - A central server system is provided which communicates with a plurality of communication devices known as RTLS tags which are usually worn by participants of an event, the event being normally contained to a facility. The RTLS tags communicate with a network located in the vicinity of the facility to determine the position of the RTLS tags in real time. The network communicates with and transfers information to and from a RTIMS server. Information about identities of the participants, the location of the participants and geographical maps of display booths and exhibitor signage at the event are stored on the RTIMS server in a datastore connected thereto. The datastore may be queried to provide participants information relevant for navigation, lead capture, participant surveys and participant traffic flow. Participant locations may be correlated to entity locations or other participants by the RTIMS system to provide location oriented services. | 08-05-2010 |
20100228602 | Event information tracking and communication tool - A central server system communicates with a plurality of communication devices known as RTLS tags worn by participants of an event in a facility. The RTLS tags communicate with a network located in the vicinity of the facility to determine the position of the RTLS tags in real time. The network transfers information to and from a RTIMS server. Information about identities of the participants, the location of the participants and geographical maps of display booths and exhibitor signage at the event are stored on the RTIMS server in a data store. Reciprocity between participants and exhibitors may be established. The data store may be queried to provide participants information relevant for navigation, lead capture, participant surveys and participant traffic flow. Participant locations may be correlated to entity locations or other participants by the RTIMS system to provide location oriented services. There is a data generation plan for the event design. | 09-09-2010 |
20110071843 | Occurrence marketing tool - A occurrence marketing server communicates with a database to store and retrieve information related to solution seekers, solution providers, surveys, survey responses and social networking data. A universal solution code (USC) is assigned to a set of solution assets configurable into a webpage describing the solution. The occurrence marketing server communicates with mobile devices via an SMS gateway to send and receive text messages. A dashboard is made available to solution seekers and providers. A mobile lead retrieval application uses a badge code to correlate and provide surveys to solution seekers. An information request application accepts and responds to USC codes via SMS text messaging. | 03-24-2011 |
20150302362 | TIME TRACKING DEVICE AND METHOD - A system and method to manage employee time at a set of job sites. A time management system comprises a server in communications with a database in which a set of job site data is stored. An employee device application is installed on a set of employee devices. The set of employee devices are in communication with the server through, the employee device application. The set of employee devices collect a set of time punch data and a set of photos from the set of employees at check-in events and check-out events. The set of time punch data and the set of photos are sent to the server and stored in the database with the set of job site data. A supervisor management application is installed on a set of supervisor devices to monitor the set of job site data, validate photos and activate employee devices. | 10-22-2015 |
Patent application number | Description | Published |
20090294970 | HIGH FREQUENCY INTERCONNECT PAD STRUCTURE - An integrated circuit includes a high speed circuit, an interconnect pad, a passivation layer under the interconnect pad, a first patterned metal layer, and a first via. The high speed circuit is for a high speed signal at a terminal of the high speed circuit. The interconnect pad is on a top surface of the integrated circuit structure. The first patterned metal layer is under the passivation layer having a first portion and a second portion. The first portion of the first patterned metal layer is connected to the terminal of the high speed circuit. The second portion of the first patterned metal layer is under the interconnect pad and is electrically floating when the high frequency signal is present on the interconnect pad portion. The result is reduced capacitive loading on the high speed signal which improves performance. | 12-03-2009 |
20100052106 | PACKAGE DEVICE HAVING CRACK ARREST FEATURE AND METHOD OF FORMING - A package device has a package substrate, a semiconductor die on the package substrate, and a molding compound on the package substrate and over the semiconductor die. The semiconductor die has a last passivation layer, an active circuit region in an internal portion of the die, an edge seal region along a periphery of the die, and a structure over the edge seal region extending above the last passivation layer, covered by the molding compound, and comprising a polymer material. The structure may extend at least five microns above the last passivation layer. The structure stops cracks in the molding compound from reaching the active circuit region. The cracks, if not stopped, can reach wire bonds in the active region and cause them to fail. | 03-04-2010 |
20110101517 | MOLDED SEMICONDUCTOR PACKAGE HAVING A FILLER MATERIAL - An integrated circuit is attached to a package substrate. The integrated circuit is electrically connected to the package substrate using a plurality of bond wires connected between a plurality of bond posts and a plurality of bond pads. A first plurality of the bond pads are along a first side of the integrated circuit and coupled to a first plurality of the bond posts with a first plurality of the bond wires. A second plurality of the bond pads are along a second side of the integrated circuit and coupled to a second plurality of the bond posts with a second plurality of the bond wires. Mold compound is injected through a plurality of openings in the package substrate. A first opening is between the first plurality of bond posts and the first side. A second opening is between the second plurality of bond posts and the second side. | 05-05-2011 |
20110108965 | SEMICONDUCTOR DEVICE PACKAGE - A method for forming a semiconductor device package includes providing a lead frame array having a plurality of leads. Each of the plurality of leads includes an opening extending through the lead from a first surface of the lead to a second surface of the lead, opposite the first surface, and each of the openings is at least partially filled with a solder wettable material. A plurality of semiconductor devices are attached to the lead frame array. The plurality of semiconductor devices are encapsulated, and, after encapsulating, the plurality of semiconductor devices are separated along separation lines which intersect the openings | 05-12-2011 |
20120025401 | INTEGRATED CIRCUIT PACKAGE WITH VOLTAGE DISTRIBUTOR - An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor. | 02-02-2012 |
20140308779 | INTEGRATED CIRCUIT PACKAGE WITH VOLTAGE DISTRIBUTOR - An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor. | 10-16-2014 |
Patent application number | Description | Published |
20120153464 | LOCALIZED ALLOYING FOR IMPROVED BOND RELIABILITY - Methods of forming gold-aluminum electrical interconnects are described. The method may include interposing a diffusion retardant layer between the gold and the aluminum, the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material; bringing into contact the diffusion retardant layer, the gold, and the aluminum; forming alloys of gold and the diffusion retardant material in regions containing the material and forming gold-aluminum intermetallic compounds in regions substantially devoid of the material; and forming a continuous electrically conducting path between the aluminum and the gold. A structure for gold-aluminum interconnect is provided. The structure may include an aluminum alloy bond pad and a diffusion retardant layer in contact with the bond pad, the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material. The structure may include a gold free air ball in contact with the diffusion retardant layer. | 06-21-2012 |
20130020674 | FUSED BUSS FOR PLATING FEATURES ON A SEMICONDUCTOR DIE - A semiconductor structure includes a semiconductor substrate; a semiconductor device formed in and over the substrate; a plurality of interconnect layers over the semiconductor device; an interconnect pad over a top surface of the plurality of interconnect layers, wherein the interconnect pad is coupled to the semiconductor device through the plurality of interconnect layers; a contiguous seal ring surrounding the semiconductor device and extending vertically from the substrate to the top surface of the plurality of interconnect layers; and a fuse coupled between the interconnect pad and the seal ring, wherein the fuse is in a non-conductive state. | 01-24-2013 |
20130023091 | FUSED BUSS FOR PLATING FEATURES ON A SEMICONDUCTOR DIE - A method for forming a semiconductor structure includes forming a plurality of fuses over a semiconductor substrate; forming a plurality of interconnect layers over the semiconductor substrate and a plurality of interconnect pads at a top surface of the plurality of interconnect layers; and forming a seal ring, wherein the seal ring surrounds active circuitry formed in and on the semiconductor substrate, the plurality of interconnect pads, and the plurality of fuses, wherein each fuse of the plurality of fuses is electrically connected to a corresponding interconnect pad of the plurality of interconnect pads and the seal ring, and wherein when each fuse of the plurality of fuses is in a conductive state, the fuse electrically connects the corresponding interconnect pad to the seal ring. | 01-24-2013 |
20130087926 | STACKED SEMICONDUCTOR DEVICES - A stacked semiconductor device includes a first, a second, a third, and a fourth semiconductor device. A first major surface of each of the first and second semiconductor devices which includes the active circuitry directly face each other, and a first major surface of each of the third and fourth semiconductor devices which includes the active circuitry directly face each other. A second major surface of the second semiconductor device directly faces a second major surface of the third semiconductor device. The stacked semiconductor device includes a plurality of continuous conductive vias, wherein each continuous conductive via extends from the second major surface of the first device, through the first device, second device, third device, and fourth device to the second major surface of the fourth device. Each of the semiconductor devices may include a beveled edge at the first major surface on at least one edge of the device. | 04-11-2013 |
20130088255 | STACKED SEMICONDUCTOR DEVICES - A stacked semiconductor device includes a first and a second semiconductor device. A first major surface of each of the first and second devices which includes the active circuitry directly face each other. The first major surface of each of the devices includes a beveled edge on at least one edge, and a probe pad which extends onto the beveled edge. A first opening is located between the beveled edges of the first and second devices on a vertical side of the stacked semiconductor device. | 04-11-2013 |
20130193589 | PACKAGED INTEGRATED CIRCUIT USING WIRE BONDS - A semiconductor device includes an integrated circuit die on a substrate. A first subset of wire bonds is between the substrate and the die. A second subset of wire bonds is between the substrate and the die. A dielectric material coats the first subset of the wire bonds along a majority of length of the first subset of the wire bonds. A medium is in contact with the second subset of the wire bonds along a majority of length of the second subset of the wire bonds. | 08-01-2013 |
20130320480 | METHODS AND STRUCTURES FOR REDUCING HEAT EXPOSURE OF THERMALLY SENSITIVE SEMICONDUCTOR DEVICES - A semiconductor device comprises an integrated circuit (IC) die having a top side and a back side. The circuit substrate includes a heat source circuit, a heat sensitive circuit, a package substrate coupled to the top side of the circuit substrate, and a plurality of thermally conductive through-silicon vias (TSVs) formed from the back side of the circuit substrate to near but not through the top side of the circuit substrate. | 12-05-2013 |
20140001641 | METHODS AND STRUCTURES FOR REDUCING HEAT EXPOSURE OF THERMALLY SENSITIVE SEMICONDUCTOR DEVICES | 01-02-2014 |
20140071652 | TECHNIQUES FOR REDUCING INDUCTANCE IN THROUGH-DIE VIAS OF AN ELECTRONIC ASSEMBLY - An electronic assembly includes a processor die assembly, a first die assembly, and a second die assembly. The first die assembly is positioned on a first side of the processor die assembly. The second die assembly is positioned on a second side of the processor die assembly opposite the first side of the processor die assembly. Through-die vias couple the first and second die assemblies to the processor die assembly. | 03-13-2014 |
20150115463 | STACKED SEMICONDUCTOR DEVICES - A stacked semiconductor device includes a first and second semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the first and second semiconductor devices include active circuitry. The first and second semiconductor devices are stacked so that the first major surface of the first semiconductor device faces the first major surface of the second semiconductor device. At least one continuous conductive via extends from the second major surface of the first semiconductor device to the first major surface of the second semiconductor device. Conductive material fills a cavity adjacent to the contact pad and is in contact with one side of the contact pad. Another side of the contact pad of the first semiconductor device faces and is in contact with another side of the contact pad of the second semiconductor device. | 04-30-2015 |
Patent application number | Description | Published |
20100298984 | USB HVAC SERVICE VERIFICATION - An HVAC system includes an enclosure for containing components of the HVAC system. Associated with the enclosure is an HVAC system control unit including a microcontroller for controlling an operation of the HVAC system. The HVAC system control unit further includes a memory associated with the microcontroller and configured to store data associated with operation of the HVAC system. The microcontroller is configurable to directly transfer the data between the memory and a portable flash memory device. The HVAC system control unit further includes a portable flash memory device interface for coupling the portable flash memory device directly thereto. | 11-25-2010 |
20100298985 | CUSTOMER EQUIPMENT PROFILE SYSTEM FOR HVAC CONTROLS - Disclosed herein is a heating, ventilating, and air conditioning (HVAC) unit and controller with memory provisions for storing, receiving, and transmitting customer equipment profiles. The controller may include a plurality of profiles that allows a selection thereof for restoration. A method for configuring HVAC equipment, including a customer profile database and efficiently transmitting unique customer and factory profiles, is also disclosed. | 11-25-2010 |
20100298987 | CONSTANT AIR VOLUME HVAC SYSTEM WITH A DEHUMIDIFICATION FUNCTION AND DISCHARGE AIR TEMPERATURE CONTROL, AN HVAC CONTROLLER THEREFOR AND A METHOD OF OPERATION THEREOF - An HVAC controller, a method of operating a constant air volume (CAV) HVAC unit and a CAV HVAC system are disclosed herein. In one embodiment, the HVAC controller includes: (1) an interface configured to receive both a latent cooling demand and a sensible cooling demand and (2) a processor configured to direct both a dehumidification function and a discharge air temperature control function for a CAV HVAC system employing the latent cooling demand and the sensible cooling demand. | 11-25-2010 |
20100298989 | HVAC SYSTEM WITH AUTOMATED BLOWER CAPACITY DEHUMIDIFICATION, A HVAC CONTROLLER THEREFOR AND A METHOD OF OPERATION THEREOF - An HVAC controller, a method of operating a HVAC unit and a HVAC system are disclosed herein. In one embodiment, the HVAC controller includes: (1) an interface configured to receive both a latent cooling demand and a sensible cooling demand and (2) a processor configured to direct both a dehumidification function and a cooling function when simultaneously processing both the latent cooling demand and the sensible cooling demand, the dehumidification function based on an operating capacity of an indoor air blower system. | 11-25-2010 |
20100298993 | AIRFLOW MANAGING SYSTEM, A METHOD OF MONITORING THE AIRFLOW IN AN HVAC SYSTEM AND A HVAC SYSTEM - An airflow managing system for monitoring airflow of a HVAC system, a HVAC system and a method of monitoring the airflow in a HVAC system is provided. In one embodiment, the airflow managing system includes: (1) an air pressure sensor configured to obtain an air pressure measurement directly from a scroll of an air blower of the HVAC system and (2) a HVAC controller configured to determine an airflow rate for the HVAC system based on the air pressure measurement and corresponding parameters associated with the air blower. | 11-25-2010 |
Patent application number | Description | Published |
20080306289 | CATALYST COMPOSITION, A PROCESS FOR PREPARING THE CATALYST COMPOSITION AND A USE OF THE CATALYST COMPOSITION - A catalyst composition comprising a support having a surface area of at least 500 m | 12-11-2008 |
20090286998 | PROCESS FOR THE PREPARATION OF ALKYLENE CARBONATE AND/OR ALKYLENE GLYCOL - The invention provides a reaction system for the production of an alkylene carbonate and/or an alkylene glycol comprising: an epoxidation zone containing an epoxidation catalyst located within an epoxidation reactor; a carboxylation zone containing an iodide-containing carboxylation catalyst located within an alkylene oxide absorber; and one or more purification zones containing a purification absorbent capable of reducing the quantity of iodide-containing impurities in a feed comprising a recycle gas, which purification zones are located upstream from the epoxidation zone; and a process for the production of an alkylene carbonate and/or an alkylene glycol. | 11-19-2009 |
20090287011 | PROCESS FOR THE PREPARATION OF AN ALKYLENE CARBONATE AND AN ALKYLENE GLYCOL - The invention provides a reaction system for the production of an alkylene carbonate comprising: an epoxidation zone containing an epoxidation catalyst located within an epoxidation reactor; a carboxylation zone containing an bromide-containing carboxylation catalyst located within an alkylene oxide absorber; and one or more purification zones containing a purification absorbent capable of reducing the quantity of bromide-containing impurities in a feed comprising a recycle gas, which purification zones are located upstream from the epoxidation zone; and a process for the production of an alkylene carbonate and an alkylene glycol. | 11-19-2009 |
20120213679 | PROCESS FOR THE PREPARATION OF ALKYLENE CARBONATE AND/OR ALKYLENE GLYCOL - The invention provides a reaction system for the production of an alkylene carbonate and/or an alkylene glycol comprising: an epoxidation zone containing an epoxidation catalyst located within an epoxidation reactor; a carboxylation zone containing an iodide-containing carboxylation catalyst located within an alkylene oxide absorber; and one or more purification zones containing a purification absorbent capable of reducing the quantity of iodide-containing impurities in a feed comprising a recycle gas, which purification zones are located upstream from the epoxidation zone; and a process for the production of an alkylene carbonate and/or an alkylene glycol. | 08-23-2012 |
20120309992 | PROCESS FOR IMPROVING THE SELECTIVITY OF AN EO CATALYST - The present invention relates to a process for improving the overall selectivity of an EO process for converting ethylene to ethylene oxide utilizing a highly selective EO silver catalyst containing a rhenium promoter wherein following normal operation a hard strip of the chloride on the surface of the catalyst is conducted in order to remove a portion of the chlorides on the surface of the catalyst. Following the hard strip, the catalyst is optionally re-optimized. Surprisingly, it has been found that the selectivity of the catalyst following the hard strip may be substantially higher than the selectivity prior to the hard strip. | 12-06-2012 |
20120315198 | PROCESS FOR THE PREPARATION OF AN ALKYLENE CARBONATE AND AN ALKYLENE GLYCOL - The invention provides a reaction system for the production of an alkylene carbonate comprising: an epoxidation zone containing an epoxidation catalyst located within an epoxidation reactor; a carboxylation zone containing an bromide-containing carboxylation catalyst located within an alkylene oxide absorber; and one or more purification zones containing a purification absorbent capable of reducing the quantity of bromide-containing impurities in a feed comprising a recycle gas, which purification zones are located upstream from the epoxidation zone; and a process for the production of an alkylene carbonate and an alkylene glycol. | 12-13-2012 |