Patent application number | Description | Published |
20080229259 | Design flow for shrinking circuits having non-shrinkable IP layout - A method for processing an integrated circuit is provided. The method includes providing a first integrated circuit having a first scale, wherein the first integrated circuit comprises a shrinkable circuit comprising a first intellectual property (IP) layout, and a non-shrinkable circuit comprising a second IP layout; and generating a second integrated circuit having a second scale smaller than the first scale. The step of generating the second integrated circuit includes shrinking the shrinkable integrated circuit to the second scale. The method further includes merging the second IP layout with the non-shrinkable circuit to generate a final integrated circuit. | 09-18-2008 |
20080270813 | Mother/daughter switch design with self power-up control - System and method for providing power to integrated circuitry with good power-on responsive time and reduced power-on transient glitches. A preferred embodiment comprises a daughter switch coupled to a circuit block, a first control circuit coupled to the daughter circuit, a second control circuit coupled to the first control circuit, and a mother circuit coupled to the circuit block and to the second control circuit. After the daughter switch is turned on by a control signal, the mother switch is not turned on until the daughter switch has discharged (charged) the voltage potential across power rails of the mother circuit to a point where glitches are minimized. The second control circuit turns on the mother circuit when the reduced voltage potential is reached, with a signal produced by the first control circuit reflects the voltage potential. Furthermore, a bypass circuit can be used to reduce leakage current. | 10-30-2008 |
20090282374 | Dummy Pattern Design for Reducing Device Performance Drift - A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip. | 11-12-2009 |
20090315079 | Layout Architecture for Improving Circuit Performance - An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight. | 12-24-2009 |
20090326873 | INTEGRATED CIRCUIT DESIGN IN OPTICAL SHRINK TECHNOLOGY NODE - Disclosed is a system, method, and computer-readable medium for designing a circuit and/or IC chip to be provided using an optical shrink technology node. Initial design data may be provided in a first technology node and through the use of embedding scaling factors in one or more EDA tools of the design flow, a design (e.g., mask data) can be generated for the circuit in an optical shrink technology node. Examples of EDA tools in which embedded scaling factors may be provided are simulation models and extraction tools including LPE decks and RC extraction technology files. | 12-31-2009 |
20100058267 | PLACE-AND-ROUTE LAYOUT METHOD WITH SAME FOOTPRINT CELLS - This invention discloses a method for automatically generating an integrated circuit (IC) layout, the method comprises determining a first cell height, creating a plurality of standard cells all having the first cell height, and generating the IC layout from the plurality of standard cells by placing and routing thereof. | 03-04-2010 |
20100065913 | Performance-Aware Logic Operations for Generating Masks - A method for forming masks for manufacturing a circuit includes providing a design of the circuit, wherein the circuit comprises a device; performing a first logic operation to determine a first region for forming a first feature of the device; and performing a second logic operation to expand the first feature to a second region greater than the first region. The pattern of the second region may be used to form the masks. | 03-18-2010 |
20100078725 | Standard Cell without OD Space Effect in Y-Direction - An integrated circuit structure includes a semiconductor substrate; a first active region in the semiconductor substrate; and a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region. A gate electrode strip is over the first and the second active regions and forms a first MOS device and a second MOS device with the first active region and the second active region, respectively. A first spacer bar is in the semiconductor substrate and connected to the first active region. At least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region. A second spacer bar is in the semiconductor substrate and connected to the second active region. At least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region. | 04-01-2010 |
20100127333 | NOVEL LAYOUT ARCHITECTURE FOR PERFORMANCE ENHANCEMENT - The present disclosure provides an integrated circuit. The integrated circuit includes an active region in a semiconductor substrate; a first field effect transistor (FET) disposed in the active region; and an isolation structure disposed in the active region. The FET includes a first gate; a first source formed in the active region and disposed on a first region adjacent the first gate from a first side; and a first drain formed in the active region and disposed on a second region adjacent the first gate from a second side. The isolation structure includes an isolation gate disposed adjacent the first drain; and an isolation source formed in the active region and disposed adjacent the isolation gate such that the isolation source and the first drain are on different sides of the isolation gate. | 05-27-2010 |
20100164614 | Structure and System of Mixing Poly Pitch Cell Design under Default Poly Pitch Design Rules - An integrated circuit including type-1 cells and a type-2 cell is presented. The type-1 cells have poly lines with a default poly pitch. The type-2 cell has poly lines with a non-default poly pitch. A first boundary region has at least one isolation area that lies between the type-1 cells and the type-2 cell in the X-direction. The first boundary region includes at least one merged dummy poly line, wherein the at least one merged dummy poly line has a first portion that complies with the default poly pitch of the type-1 cells and a second portion that complies with the non-default poly pitch of the type-2 cell. | 07-01-2010 |
20100174933 | System and Method for Reducing Processor Power Consumption - A system and method for reducing active power in processors is disclosed. A method embodiment comprises the steps of determining when a particular logic block is inactive, determining the powered state of the particular logic block, isolating the particular logic block from a main processor core, and powering off the particular logic block. When the system needs the particular logic block, the method further comprises reactivating the block. A system embodiment comprises software and a processor coupled to a clock control module, an isolation control module and a header/footer module, operable to isolate a particular logic block and power off a particular logic block, thereby reducing power. Another embodiment comprises a logic module coupled to a clock by a clock gating module, an isolation module for isolating the logic module, a header/footer module for disabling power to the logic module, and a power and clock gating control module for controlling the clock gating module and the header/footer module. | 07-08-2010 |
20100196803 | Methods for Cell Boundary Isolation in Double Patterning Design - A method of designing a double patterning mask set for a layout of a chip includes designing standard cells. In each of the standard cells, all left-boundary patterns are assigned with one of a first indicator and a second indicator, and all right-boundary patterns are assigned with an additional one of the first indicator and the second indicator. The method further includes placing the standard cells in a row of the layout of the chip. Starting from one of the standard cells in the row, indicator changes to the standard cells are propagated throughout the row. All patterns in the standard cells having the first indicator are transferred to a first mask of the double patterning mask set. All patterns in the standard cells having the second indicator are transferred to a second mask of the double patterning mask set. | 08-05-2010 |
20100199238 | Systematic Method for Variable Layout Shrink - A method for integrated circuit design includes providing a layout of an integrated circuit; determining key parameters of the integrated circuit; determining target values of the key parameters; and performing a first shrinkage of the layout using a first shrink percentage to generate a shrunk layout. The shrunk layout is evaluated by generating values of the key parameters from the shrunk layout. A portion of the values of the key parameters failing to meet respective ones of the target values is found. Guidelines for tuning manufacturing processes of the shrunk layout are provided, so that the portion of the values of the key parameters can meet the respective ones of the target values. | 08-05-2010 |
20100199253 | Routing Method for Double Patterning Design - A method of designing a double patterning mask set includes dividing a chip into a grid comprising grid cells; and laying out a metal layer of the chip. In substantially each of the grid cells, all left-boundary patterns of the metal layer are assigned with a first one of a first indicator and a second indicator, and all right-boundary patterns of the metal layer are assigned with a second one of the first indicator and the second indicator. Starting from one of the grid cells in a row, indicator changes are propagated throughout the row. All patterns in the grid cells are transferred to the double patterning mask set, with all patterns assigned with the first indicator transferred to a first mask of the double patterning mask set, and all patterns assigned with the second indicator transferred to a second mask of the double patterning mask set. | 08-05-2010 |
20100205577 | Design Methods for E-Beam Direct Write Lithography - A method of forming integrated circuits for a wafer includes providing an E-Beam direct write (EBDW) system. A grid is generated for the wafer, wherein the grid includes grid lines. An integrated circuit is laid out for the wafer, wherein substantially no sensitive features in the integrated circuit cross the grid lines of the grid. An EBDW is performed on the wafer using the EBDW system. | 08-12-2010 |
20100269081 | Standard Cells Having Flexible Layout Architecture/Boundaries - An integrated circuit layout includes a standard cell, which includes a first gate strip and a second gate strip parallel to each other and having a gate pitch; a first boundary and a second boundary on opposite ends of the first standard cell; and a third boundary and a fourth boundary on opposite ends of the first standard cell and parallel to the first gate strip and the second gate strip. A cell pitch between the third boundary and the fourth boundary is not equal to integer times the gate pitch. A PMOS transistor is formed of the first gate strip and a first active region. An NMOS transistor is formed of the first gate strip and a second active region. | 10-21-2010 |
20100281446 | Integrated Circuit Design using DFM-Enhanced Architecture - Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell. | 11-04-2010 |
20100293514 | DESIGN-DRIVEN METAL CRITICAL DIMENSION (CD) BIASING - A method of designing an integrated circuit (“IC”) is provided that includes placing an IC design, where the IC design includes a first element, a second element, and a path coupling the first and second elements, and routing the IC design. Further, the method includes obtaining at least one of resistivity data and capacitance data related to the path, and obtaining timing data related to the path. The method also includes using at least one of the resistivity data, the capacitance data, and the timing data to determine a critical dimension (“CD”) bias to be applied to the path, and modifying the IC design, where modifying includes applying the CD bias to the path. | 11-18-2010 |
20110023002 | DOUBLE PATTERNING FRIENDLY LITHOGRAPHY METHOD AND SYSTEM - A method includes receiving an identification of a plurality of cells to be included in an integrated circuit (IC) layout, including a list of pairs of cells within the plurality of cells to be connected to each other. First routing paths are identified, to connect a maximum number of the pairs of cells using one-dimensional (1-D) routing between cells within those pairs of cells. Second routing paths are selected from a predetermined set of two-dimensional (2-D) routing patterns to connect any of the pairs of cells which cannot be connected by 1-D routing. The first and second routing paths are output to a machine readable storage medium to be read by a control system for controlling a semiconductor fabrication process to fabricate the IC. | 01-27-2011 |
20110035715 | SYSTEM AND METHOD FOR ON-CHIP-VARIATION ANALYSIS - Apparatus is provided for performing timing analysis on a circuit. A first storage device portion stores a state dependent stage weight for each of a rising time arc and a falling time arc of each of a plurality of cells in a cell library. An adder is provided for calculating a sum of the state dependent stage weights for each of the cells that are included in a circuit path. A second storage device portion stores a table containing on chip variation (OCV) derating factors. The table is indexed by values of the sum. A total path delay is calculated for the circuit path, based on the OCV derating factor corresponding to the sum of the state dependent stage weights for the cells in the circuit path. | 02-10-2011 |
20110035717 | Design Optimization for Circuit Migration - An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist. | 02-10-2011 |
20110072405 | Chip-Level ECO Shrink - In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed. | 03-24-2011 |
20110119648 | ROUTING SYSTEM AND METHOD FOR DOUBLE PATTERNING TECHNOLOGY - A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology. | 05-19-2011 |
20110193234 | Methods for Double-Patterning-Compliant Standard Cell Design - A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells. | 08-11-2011 |
20110204449 | Dummy Pattern Design for Reducing Device Performance Drift - A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip. | 08-25-2011 |
20110291200 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure. | 12-01-2011 |
20110296360 | METHOD FOR CHECKING AND FIXING DOUBLE-PATTERNING LAYOUT - A method and system checks a double patterning layout and outputs a representation of G0-rule violations and critical G0-spaces. The method includes receiving layout data having patterns, determining whether each distance between adjacent pattern elements is a G0-space, find all G0-space forming a G0-rule violation, finding all G0-space that are critical G0-spaces, and outputting a representation of G0-rule violations and critical G0-spaces to an output device. By resolving G0-rule violations and critical G0-spaces, a design checker can effectively generate a double patterning technology (DPT) compliant layout. | 12-01-2011 |
20120025273 | ELECTROMIGRATION RESISTANT STANDARD CELL DEVICE - A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells. | 02-02-2012 |
20120032268 | Layout and Process of Forming Contact Plugs - A device includes a semiconductor substrate including an active region, a gate electrode directly over the active region, and a gate contact plug over and electrically coupled to the gate electrode. The gate contact plug includes at least a portion directly over, and vertically overlapping, the active region. | 02-09-2012 |
20120043618 | Performance-Aware Logic Operations for Generating Masks - Stress engineering for PMOS and NMOS devices is obtained with a compressive stressor layer over the PMOS device, wherein the compressive stressor layer has the shape of a polygon when viewed from a top down perspective, and wherein the polygon includes a recess defined in its periphery. The NMOS device has a tensile stress layer wherein the tensile stressor layer has the shape of a polygon when viewed from the top down perspective, wherein the polygon includes a protrusion in its periphery, the protrusion extending into the recess of the first stressor layer. Thus, stress performance for both devices can be improved without violating design rules. | 02-23-2012 |
20120091592 | Double Patterning Technology Using Single-Patterning-Spacer-Technique - A method of forming an integrated circuit structure includes forming a first and a second plurality of tracks parallel to a first direction and on a wafer representation. The first and the second plurality of tracks are allocated in an alternating pattern. A first plurality of patterns is laid out on the first plurality of tracks and not on the second plurality of tracks. A second plurality of patterns is laid out on the second plurality of tracks and not on the first plurality of tracks. The first plurality of patterns is extended in the first direction and in a second direction perpendicular to the first direction, so that each of the second plurality of patterns is surrounded by portions of the first plurality of patterns, and substantially none of neighboring ones of the first plurality of patterns on the wafer representation have spacings greater than a pre-determined spacing. | 04-19-2012 |
20120131523 | METHOD OF GENERATING AN INTELLECTUAL PROPERTY BLOCK DESIGN KIT, METHOD OF GENERATING AN INTEGRATED CIRCUIT DESIGN, AND SIMULATION SYSTEM FOR THE INTEGRATED CIRCUIT DESIGN - The present application discloses a method of generating an intellectual property (IP) block design kit including an IP block circuit design and a system-level characteristics table for manufacturing an integrated circuit. According at least one embodiment, the IP block circuit design is generated. The IP block circuit design is simulated based on predetermined configuration sets, and each configuration set has manufacturing options and/or operating conditions. A plurality of system-level models for the predetermined configuration sets are generated based on the simulation of the IP block circuit design. The system-level characteristics table is generated by arranging the predetermined configuration sets and the system-level models in compliance with a system-level characteristics table template of a system-level characteristics modeling device. Then the IP block circuit design and the system-level characteristics table are stored as the IP block design kit. | 05-24-2012 |
20120131528 | METHOD AND APPARATUS FOR ACHIEVING MULTIPLE PATTERNING TECHNOLOGY COMPLIANT DESIGN LAYOUT - A method and apparatus for achieving multiple patterning compliant technology design layouts is provided. An exemplary method includes providing a routing grid having routing tracks; designating each of the routing tracks one of at least two colors; applying a pattern layout having a plurality of features to the routing grid, wherein each of the plurality of features corresponds with at least one routing track; and applying a feature splitting constraint to determine whether the pattern layout is a multiple patterning compliant layout. If the pattern layout is not a multiple patterning compliant layout, the pattern layout may be modified until a multiple patterning compliant layout is achieved. If the pattern layout is a multiple patterning compliant layout, the method includes coloring each of the plurality of features based on the color of each feature's corresponding at least one routing track, thereby forming a colored pattern layout, and generating at least two masks with the features of the colored pattern layout. Each mask includes features of a single color. | 05-24-2012 |
20120167021 | Cell Layout for Multiple Patterning Technology - A system and method for providing a cell layout for multiple patterning technology is provided. An area to be patterned is divided into alternating sites corresponding to the various masks. During a layout process, sites located along a boundary of a cell are limited to having patterns in the mask associated with the boundary site. When placed, the individual cells are arranged such that the adjoining cells alternate the sites allocated to the various masks. In this manner, the designer knows when designing each individual cell that the mask pattern for one cell will be too close to the mask pattern for an adjoining cell. | 06-28-2012 |
20120210279 | DECOMPOSITION AND MARKING OF SEMICONDUCTOR DEVICE DESIGN LAYOUT IN DOUBLE PATTERNING LITHOGRAPHY - Provided is a system and method for assessing a design layout for a semiconductor device level and for determining and designating different features of the design layout to be formed by different photomasks by decomposing the design layout. The features are designated by markings that associate the various device features with the multiple photomasks upon which they will be formed and then produced on a semiconductor device level using double patterning lithography, DPL, techniques. The markings are done at the device level and are included on the electronic file provided by the design house to the photomask foundry. In addition to overlay and critical dimension considerations for the design layout being decomposed, various other device criteria, design criteria processing criteria and their interrelation are taken into account, as well as device environment and the other device layers, when determining and marking the various device features. | 08-16-2012 |
20120313256 | Non-Hierarchical Metal Layers for Integrated Circuits - An integrated circuit structure includes a semiconductor substrate, and a first metal layer over the semiconductor substrate. The first metal layer has a first minimum pitch. A second metal layer is over the first metal layer. The second metal layer has a second minimum pitch smaller than the first minimum pitch. | 12-13-2012 |
20120331426 | CELL ARCHITECTURE AND METHOD - A method includes selecting a cell stored in a non-transient computer readable storage medium, arranging a plurality of the cells on a model of a semiconductor device, and creating a mask for the semiconductor device based on the model of the semiconductor device. The cell is designed according to a design rule in which a first power-supply-connection via satisfies a criterion from the group consisting of: i) the first power-supply-connection via is spaced apart from a second power-supply-connection via by a distance that is greater than a threshold distance such that the cell can be fabricated by a single-photolithography single-etch process, or ii) the first power-supply-connection via is coupled to first and second substantially parallel conductive lines that extend along directly adjacent tracks. | 12-27-2012 |
20130087932 | INTEGRATED CIRCUITS AND METHODS OF DESIGNING THE SAME - A method of designing an integrated circuit includes deploying an active area in a first standard cell. At least one gate electrode is routed, overlapping the active area in the first standard cell. At least one metallic line structure is routed, overlapping the active area in the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. A first power rail is routed substantially orthogonal to the at least one metallic line structure in the first standard cell. The first power rail overlaps the at least one metallic line structure. The first power rail has a flat edge that is adjacent to the at least one metallic line structure. A first connection plug is deployed at a region where the first power rail overlaps the at least one metallic line structure in the first standard cell. | 04-11-2013 |
20130234212 | ELECTROMIGRATION RESISTANT STANDARD CELL DEVICE - A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. | 09-12-2013 |
20130256902 | INTERCONNECT STRUCTURE HAVING SMALLER TRANSITION LAYER VIA - An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via. | 10-03-2013 |
20140001595 | Layout Architecture for Performance Improvement | 01-02-2014 |
20140077270 | INTEGRATED CIRCUIT - An integrated circuit includes a first standard cell over a substrate, a power rail, and a first connection plug. The first standard cell includes an active area, at least one gate electrode overlapping the active area of the first standard cell, and at least one metallic line structure overlapping the active area of the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. The power rail is substantially orthogonal to the at least one metallic line structure of the first standard cell. The power rail overlaps the at least one metallic line structure of the first standard cell, and the power rail has a flat edge extending through the first standard cell. The first connection plug is at a region where the power rail overlaps the at least one metallic line structure of the first standard cell. | 03-20-2014 |
20140183647 | INTEGRATED CIRCUIT LAYOUT DESIGN - An integrated circuit layout that includes a first standard cell having a first transistor region and a second transistor region; a second standard cell having a third transistor region and a fourth transistor region. The first and second standard cells adjoin each other at side boundaries thereof and the first transistor region and the third transistor region are formed in a first continuous active region, and the second transistor region and the fourth transistor region are formed in a second continuous region. | 07-03-2014 |
20140215421 | SELF-ALIGNED MULTIPLE PATTERNING LAYOUT DESIGN - Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. The initial design layout comprises a first pattern, such as a mandrel pattern, and a second pattern, such as a passive fill pattern. An initial cut pattern is generated for the initial design layout. Responsive to identifying a design rule violation associated with the initial cut pattern, the initial design layout is modified to generate a modified initial design layout. An updated cut pattern, not resulting in the design rule violation, is generated based upon the modified initial design layout. The updated cut pattern is applied to the modified initial design layout to generate a final design layout. The final design layout can be verified as self-aligned multiple patterning (SAMP) compliant. | 07-31-2014 |
20140245251 | Design Optimization for Circuit Migration - An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist. | 08-28-2014 |
20140282306 | Layout Optimization for Integrated Design - A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern. | 09-18-2014 |
20140298284 | STANDARD CELL DESIGN LAYOUT - Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant. | 10-02-2014 |
20150062761 | Electrostatic Discharge Protection for Level-Shifter Circuit - A circuit, a multiple power domain circuit, and a method are disclosed. An embodiment is a circuit including an input circuit having a first output and a second output, the input circuit being coupled to a first power supply voltage, and a level-shifting circuit having a first input coupled to the first output of the input circuit and a second input coupled to the second output of the input circuit, the level-shifting circuit being coupled to a second power supply voltage. The circuit further includes a first transistor coupled between a first node of the level-shifting circuit and the second power supply voltage, and a control circuit having an output coupled to a gate of the first transistor, the control circuit being coupled to the second power supply voltage. | 03-05-2015 |
20150082259 | LAYOUT OPTIMIZATION FOR INTEGRATED CIRCUIT DESIGN - A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern. | 03-19-2015 |