Patent application number | Description | Published |
20090089468 | COHERENT INPUT OUTPUT DEVICE - According to some embodiments, data to be exchanged via a system input output interface may be determined at a processor. It may then be arranged to exchange the data via a coherent input output device coupled to a coherent system interconnect. Other embodiments are described. | 04-02-2009 |
20110161748 | Systems, methods, and apparatuses for hybrid memory - Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer. | 06-30-2011 |
20120284436 | SYSTEMS, METHODS, AND APPARATUSES FOR HYBRID MEMORY - Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer. | 11-08-2012 |
Patent application number | Description | Published |
20120011276 | Dynamically Modulating Link Width - Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability. | 01-12-2012 |
20150081921 | DYNAMICALLY MODULATING LINK WIDTH - Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability. | 03-19-2015 |
20150161005 | SYSTEMS, METHODS, AND APPARATUSES FOR STACKED MEMORY - Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer. | 06-11-2015 |
Patent application number | Description | Published |
20100027564 | Method, Apparatus, And System For Idle State Definition For Power Management - A predetermined network packet is utilized for power reduction in either or both of a transmitter and receiver when information is not needed. Upon detection of the predetermined network packet type, various portions of the transmitter and/or receiver may be clock gated or powered down. | 02-04-2010 |
20100098101 | PACKET FORMAT FOR A DISTRIBUTED SYSTEM - A method is provided for transmitting a packet including information describing a bus transaction to be executed at a remote device. A bus transaction is detected on a first bus and a network packet is generated for transmission over a network. The network packet includes an opcode describing the type of bus transaction. One or more control signals of the bus transaction map directly to one or more bits of the opcode to simplify decoding or converting of the bus transaction to the opcode. The packet is transmitted to a remote device and the bus transaction is then replayed at a second bus. In addition, the packet includes a data field having a size that is a multiple of a cache line size. The packet includes separate CRCs for the data and header. The packet also includes a transaction ID to support split transactions over the network. Also, fields in the packet header are provided in a particular order to improve switching efficiency. | 04-22-2010 |
20110176431 | PHYSICAL LAYER LOOPBACK - In some embodiments, a chip comprises control circuitry to provide inband signals, inband output ports, and transmitters to transmit the inband signals to the inband output ports. The control circuitry selectively includes loopback initiating commands in the inband signals. Other embodiments are described and claimed. | 07-21-2011 |
20120047305 | PACKET FORMAT FOR A DISTRIBUTED SYSTEM - A method is provided for transmitting a packet including information describing a bus transaction to be executed at a remote device. A bus transaction is detected on a first bus and a network packet is generated for transmission over a network. The network packet includes an opcode describing the type of bus transaction. One or more control signals of the bus transaction map directly to one or more bits of the opcode to simplify decoding or converting of the bus transaction to the opcode. The packet is transmitted to a remote device and the bus transaction is then replayed at a second bus. In addition, the packet includes a data field having a size that is a multiple of a cache line size. The packet includes separate CRCs for the data and header. The packet also includes a transaction ID to support split transactions over the network. Also, fields in the packet header are provided in a particular order to improve switching efficiency. | 02-23-2012 |
20130114420 | PHYSICAL LAYER LOOPBACK - In some embodiments, a chip comprises control circuitry to provide inband signals, inband output ports, and transmitters to transmit the inband signals to the inband output ports. The control circuitry selectively includes loopback initiating commands in the inband signals. Other embodiments are described and claimed. | 05-09-2013 |
20140156892 | METHOD, SYSTEM, AND APPARATUS FOR LINK LATENCY MANAGEMENT - A link latency management for a high-speed point-to-point network (pTp) is described The link latency management facilitates calculating latency of a serial interface by tracking a round trip delay of a header that contains latency information. Therefore, the link latency management facilitates testers, logic analyzers, or test devices to accurately measure link latency for a point-to-point architecture utilizing a serial interface. | 06-05-2014 |
20150074440 | LINK POWER SAVINGS WITH STATE RETENTION - Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed. | 03-12-2015 |
20150178092 | HIERARCHICAL AND PARALLEL PARTITION NETWORKS - In accordance with the present description, provided are hierarchical and parallel partition networks which include a plurality of parallel partition packet networks for interconnecting components on one or more integrated circuit dies. In one embodiment, each parallel partition packet network is independent of the other parallel partition packet networks and has a unit level switch at a unit hierarchical level. In another aspect, each parallel partition packet network has a unit-to-unit level switch at a unit-to-unit hierarchical level. Other aspects are described herein. | 06-25-2015 |
Patent application number | Description | Published |
20120123961 | PERFORMANCE REPORTING FOR PRODUCTS AND SERVICES USING WEB-BASED PORTALS - A method includes obtaining performance information from sources, where the performance information relates to products and/or services, enabling the performance information to be reviewed to thereby produce vetted and categorized performance information, receiving the vetted and categorized performance information, where the vetted and categorized performance information includes the performance information that has been vetted for reliability and that has been categorized according to reliability, and using the vetted and categorized performance information to generate reports, where the reports indicate a performance impact of the products and/or services. | 05-17-2012 |
20130124269 | PERFORMANCE REPORTING FOR PRODUCTS AND SERVICES USING WEB-BASED PORTALS - A method includes obtaining performance information from sources, where the performance information relates to products and/or services, enabling the performance information to be reviewed to thereby produce vetted and categorized performance information, receiving the vetted and categorized performance information, where the vetted and categorized performance information includes the performance information that has been vetted for reliability and that has been categorized according to reliability, and using the vetted and categorized performance information to generate reports, where the reports indicate a performance impact of the products and/or services. | 05-16-2013 |
20160104086 | SYSTEM FOR SELECTING ENVIRONMENTALLY-SUSTAINABLE BUILDING PRODUCTS - An enhanced system is provided to assist a building professional in selecting products for building projects which minimize environmental impact. Accurate data on many different building products that has previously been collected, categorized and subcategorized by product type is provided to the system. This information has previously been separated into ranks (spheres) based upon how well the data has been collected according to ISO Product Standard data requirements. A user may then interactively select values for the environmental impact parameters. Products matching the selected environmental impact parameter values are displayed, while those not matching the values are not displayed. The user may select various products. The amount of each selected product to be used on a project is acquired and used to weight the environmental impact. Costs and financial benefits are determined from the products used and a payback period is determined. | 04-14-2016 |
Patent application number | Description | Published |
20090150301 | FINANCIAL PRODUCT RISK MITIGATION SYSTEM AND METHOD - Automated methods for managing risk associated with investment products is disclosed. A logic engine executes portfolio realignment and contract benefit calculations according to timing rules or event-based triggers. The investment product may provide a guaranteed withdrawal benefit option that allows for a variety of investment, payment, withdrawal, fee and termination options. | 06-11-2009 |
20120036087 | AUTOMATIC INCOME ADJUSTMENT - A method includes receiving market data associated with an investment product that specifies a first guaranteed annual withdrawal amount and a second guaranteed annual withdrawal amount, where the first guaranteed annual withdrawal amount is greater than the second guaranteed annual withdrawal amount. The method includes automatically selecting a guaranteed annual withdrawal amount from the first guaranteed annual withdrawal amount and the second guaranteed annual withdrawal amount based on at least an evaluation of the market data. | 02-09-2012 |
20130096959 | Automatic Income Adjustment - A method includes receiving market data associated with an investment product that specifies a first guaranteed annual withdrawal amount and a second guaranteed annual withdrawal amount, where the first guaranteed annual withdrawal amount is greater than the second guaranteed annual withdrawal amount. The method also includes automatically selecting a guaranteed annual withdrawal amount from the first guaranteed annual withdrawal amount and the second guaranteed annual withdrawal amount based on at least an evaluation of the market data. | 04-18-2013 |
20150339781 | Financial Product Risk Mitigation System and Method - Automated methods for managing risk associated with investment products is disclosed. A logic engine executes portfolio realignment and contract benefit calculations according to timing rules or event-based triggers. The investment product may provide a guaranteed withdrawal benefit option that allows for a variety of investment, payment, withdrawal, fee and termination options. | 11-26-2015 |
Patent application number | Description | Published |
20100331928 | VISIBLE LIGHT MODULATION OF MITOCHONDRIAL FUNCTION IN HYPOXIA AND DISEASE - The present invention provides methods of using electromagnetic radiation in the visible portion of the spectrum to modulate mitochondrial function in the treatment of various conditions, including Alzheimer's disease, other dementias, hypoxia and diabetic peripheral neuropathy, and sensory disorders of the extremities. | 12-30-2010 |
20120065709 | METHODS AND DEVICES FOR VISIBLE LIGHT MODULATION OF MITOCHONDRIAL FUNCTION IN HYPOXIA AND DISEASE - The present invention provides methods of using electromagnetic radiation in the visible portion of the spectrum to modulate mitochondrial function in the treatment of various conditions, including Alzheimer's disease, other demential, hypoxia and diabetic peripheral neuropathy, and sensory disorders of the extremities. | 03-15-2012 |
20130288328 | VISIBLE LIGHT MODULATION OF MITOCHONDRIAL FUNCTION IN HYPOXIA AND DISEASE - The present invention provides methods of using electromagnetic radiation in the visible portion of the spectrum to modulate mitochondrial function in the treatment of various conditions, including Alzheimer's disease, other dementias, hypoxia and diabetic peripheral neuropathy, and sensory disorders of the extremities. | 10-31-2013 |
Patent application number | Description | Published |
20090053476 | MULTILAYERED CELLULAR METALLIC GLASS STRUCTURES AND METHODS OF PREPARING THE SAME - Multi-layered cellular metallic glass structures and methods of preparing the same are provided. In one embodiment, the cellular metallic glass structure includes at least one patterned metallic glass sheet and at least one additional sheet. The at least one patterned metallic glass sheet may include multiple sheets connected together to form a group of sheets, and the structure may include a group of sheets sandwiched between two outer sheets. The patterned metallic glass sheets may be patterned by thermoplastically forming two- and/or three-dimensional patterns in the metallic glass sheets. The metallic glass cellular structures are useful in a wide variety of applications, including but not limited to blast protection applications, energy absorption applications, structural support applications, biomedical implant applications, heat exchanger applications, thermal management applications, electrical shielding applications, magnetic shielding applications, and debris and radiation shielding for aerospace and outer space applications. | 02-26-2009 |
20130074313 | Multilayered Cellular Metallic Glass Structures and Methods of Preparing the Same - Multi-layered cellular metallic glass structures and methods of preparing the same are provided. In one embodiment, the cellular metallic glass structure includes at least one patterned metallic glass sheet and at least one additional sheet. The at least one patterned metallic glass sheet may include multiple sheets connected together to form a group of sheets, and the structure may include a group of sheets sandwiched between two outer sheets. The patterned metallic glass sheets may be patterned by thermoplastically forming two- and/or three-dimensional patterns in the metallic glass sheets. The metallic glass cellular structures are useful in a wide variety of applications, including but not limited to blast protection applications, energy absorption applications, structural support applications, biomedical implant applications, heat exchanger applications, thermal management applications, electrical shielding applications, magnetic shielding applications, and debris and radiation shielding for aerospace and outer space applications. | 03-28-2013 |
Patent application number | Description | Published |
20140122829 | EFFICIENT MEMORY VIRTUALIZATION IN MULTI-THREADED PROCESSING UNITS - A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches. | 05-01-2014 |
20140123145 | EFFICIENT MEMORY VIRTUALIZATION IN MULTI-THREADED PROCESSING UNITS - A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches. | 05-01-2014 |
20140123146 | EFFICIENT MEMORY VIRTUALIZATION IN MULTI-THREADED PROCESSING UNITS - A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches. | 05-01-2014 |
20140281255 | PAGE STATE DIRECTORY FOR MANAGING UNIFIED VIRTUAL MEMORY - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20140281256 | FAULT BUFFER FOR RESOLVING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20140281263 | REPLAYING MEMORY TRANSACTIONS WHILE RESOLVING MEMORY ACCESS FAULTS - One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a replay unit per SM. Upon detecting a page fault associated with a memory transaction issued by a particular SM, the corresponding replay unit causes the SM, but not any unaffected SMs, to cease issuing new memory transactions. The replay unit then stores the faulting memory transaction and any faulting in-flight memory transaction in a replay buffer. As page faults are resolved, the replay unit replays the memory transactions in the replay buffer—removing successful memory transactions from the replay buffer—until all of the stored memory transactions have successfully executed. Advantageously, the overall performance of the PPU is improved compared to conventional PPUs that, upon detecting a page fault, stop performing memory transactions across all SMs included in the PPU until the fault is resolved. | 09-18-2014 |
20140281296 | FAULT BUFFER FOR TRACKING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20140281297 | MIGRATION OF PEER-MAPPED MEMORY PAGES - Techniques are provided by which memory pages may be migrated among PPU memories in a multi-PPU system. According to the techniques, a UVM driver determines that a particular memory page should change ownership state and/or be migrated between one PPU memory and another PPU memory. In response to this determination, the UVM driver initiates a peer transition sequence to cause the ownership state and/or location of the memory page to change. Various peer transition sequences involve modifying mappings for one or more PPU, and copying a memory page from one PPU memory to another PPU memory. Several steps in peer transition sequences may be performed in parallel for increased processing speed. | 09-18-2014 |
20140281299 | OPPORTUNISTIC MIGRATION OF MEMORY PAGES IN A UNIFIED VIRTUAL MEMORY SYSTEM - Techniques are disclosed for transitioning a memory page between memories in a virtual memory subsystem. A unified virtual memory (UVM) driver detects a page fault in response to a memory access request associated with a first memory page, where a local page table does not include an entry corresponding to a virtual memory address included in the memory access request. The UVM driver, in response to the page fault, executes a page fault sequence. The page fault sequence includes modifying the ownership state associated with the first memory page to be central-processing-unit-shared. The page fault sequence further includes scheduling the first memory page for migration from a system memory associated with a central processing unit (CPU) to a local memory associated with a parallel processing unit (PPU). One advantage of the disclosed approach is that the PPU accesses memory pages with greater efficiency. | 09-18-2014 |
20140281324 | MIGRATING PAGES OF DIFFERENT SIZES BETWEEN HETEROGENEOUS PROCESSORS - One embodiment of the present invention sets forth a computer-implemented method for migrating a memory page from a first memory to a second memory. The method includes determining a first page size supported by the first memory. The method also includes determining a second page size supported by the second memory. The method further includes determining a use history of the memory page based on an entry in a page state directory associated with the memory page. The method also includes migrating the memory page between the first memory and the second memory based on the first page size, the second page size, and the use history. | 09-18-2014 |
20140281357 | COMMON POINTERS IN UNIFIED VIRTUAL MEMORY SYSTEM - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20140281358 | MIGRATION SCHEME FOR UNIFIED VIRTUAL MEMORY SYSTEM - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
Patent application number | Description | Published |
20090284325 | Phased-Array Antenna Filter and Diplexer for a Super Economical Broadcast System - A phased-array antenna filter and diplexer for a super economical broadcast system are provided. The filter and diplexer includes a signal divider tee diplexer, a receive filter and a transmit filter. The diplexer includes a tee branch point, an antenna port, a transmit port and a receive port. The receive filter includes a flat, multi-pole bandpass filter, an input port and an output port, where the input port is coupled to the diplexer receive port to define a receive signal path, from the tee branch point to the receive input port, that has a length of approximately one quarter receive wavelength. The transmit filter includes a folded, multi-pole bandpass filter, an input port and an output port, where the output port is coupled to the diplexer transmit port to define a transmit signal path, from the tee branch point to the transmit output port, that has a length of approximately one quarter transmit wavelength. | 11-19-2009 |
20110001583 | FILTER APPARATUS AND METHOD - A filter includes a cross-coupling link which includes a crossbar, a first vertical support attached to one end of the crossbar, a second vertical support attached to another end of the crossbar, a first coupling arm attached to the first vertical support, a second coupling arm attached to the second vertical support, a first adjustable support attached to the first coupling arm at one end and grounded at another end, and a second adjustable support attached to the second coupling arm at one end and grounded at another end. | 01-06-2011 |
Patent application number | Description | Published |
20100004768 | CONTROLLABLE TRACK-SKIPPING - A method, system, and computer program product allow users to skip and/or to fast-forward through media items such as songs, while limiting the extent to which skipping is allowed in order to maintain conformance with sound performance complement restrictions such as those specified by the Digital Millennium Copyright Act. If the user requests a skip that may result in a DMCA violation, the skip is disallowed and the request is denied. Playlists are constructed so that the sound recording performance complement limitations are applied to a longer time period than the period specified in the DMCA, the longer time period being defined by adding an “excess time” to the normal DMCA period. If the user attempts to skip a song or song portion that would cause the aggregated skipped amount to exceed the excess time, the skip is disallowed. | 01-07-2010 |
20120011138 | ASSOCIATING AND LINKING COMPACT DISC METADATA - Improved techniques for enhancing, associating, and linking various sources of metadata for music files, to allow integration of commercially generated metadata with user-entered metadata, and to ensure that metadata provided to the user is of the highest quality and accuracy available, even when the metadata comes from disparate sources having different levels of credibility. The invention further provides improved techniques for identifying approximate matches when querying metadata databases, and also provides improved techniques for accepting user submissions of metadata, for categorizing user submissions according to relative credibility, and for integrating user submissions with existing metadata. | 01-12-2012 |
20130317937 | RELATIONSHIP DISCOVERY ENGINE - A system, method, and computer program product discover relationships among items and recommend items based on the discovered relationships. The recommendations provided by the present invention are based on user profiles that take into account actual preferences of users, without requiring users to complete questionnaires. An improved binomial log likelihood ratio analysis technique is applied, to reduce adverse effects of overstatement of coincidence and predominance of best sellers. The invention may be used, for example, to generate track lists for a personalized radio station. | 11-28-2013 |