Patent application number | Description | Published |
20090016126 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided that is capable of detecting a short circuit defect to be detected in a memory array without causing an error due to off-current of a sense amplifier circuit. Sense amplifier circuits amplify a potential between a pair of bit lines, which occurs based on potential of memory cells selected by driving word lines and bit lines. Selection transistors are provided between the bit lines and the sense amplifier circuits. A word-SE interval control circuit included in an X timing generating circuit turns off the selection transistors and disconnects the bit lines from the sense amplifier circuits based on a signal representing a test state for expanded time when a test to expand an interval between word line driving and activation of the sense amplifier circuits and detect defect sites of the bit lines is performed. | 01-15-2009 |
20090016139 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device is provided which enables use of an overdrive method at low voltage and for a small device area. The semiconductor device includes: memory cells; sense amplifiers, each having P-channel and N-channel MOS transistors and amplifying a signal read from a memory cell; a first power supply line connected to a source terminal of the P-channel MOS transistor provided in each of the sense amplifiers; a second power supply line which supplies an overdrive voltage to the sense amplifiers at a potential higher than a write potential of the memory cell; a third power supply line connected to an external power supply, a connection element which connects and disconnects the first power supply line and the second power supply line; a capacitance element connected to the second power supply line; and a resistance element inserted between the second power supply line and the third power supply line. | 01-15-2009 |
20090284291 | COMPLEMENTARY SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE COMPRISING SAME - A complementary signal generation circuit includes a first transmission path including a first number N of inverters and a second transmission path including a second number (N−1) of inverters. A delay circuit composed of a first resistance element and a capacity element is arranged in series between two inverters in the second transmission path so as to correspond to any one of the inverters in the first transmission path. The capacity element is formed by a capacitive inverter having the same input capacity ratio as the any one of the inverters. The complementary signal generation circuit generates output signals having the logic levels which are complementary to each other through the first and second transmission paths. | 11-19-2009 |
20100008129 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device includes first and second bit lines complementary to each other, sense amplifiers, memory cells, first and second switches, an equalizer circuit, and a potential generation unit. The potential generation unit supplies a first potential to at least a selected one of the plurality of first and second bit lines through the plurality of first and second switches. The equalizer circuit sets the first and second bit lines at the second potential. When an access to the memory cell connected to the first and second bit lines, the potential generation unit gives the first potential to the second bit line. | 01-14-2010 |
20100182862 | Semiconductor memory device and method of controlling auto-refresh - Auto-refresh of a semiconductor device may be controlled by setting the number of auto-refresh to be performed in a period of time, based on temperature, when an auto-refresh command is detected. | 07-22-2010 |
20100302833 | Semiconductor device having nonvolatile memory element and manufacturing method thereof - To provide a semiconductor device including a pair of antifuse elements at either a high level or a low level, an OR circuit that outputs different logic information for a case that at least one of the antifuse elements is at a high level and a case that both of the antifuse elements are at a low level, and an exclusive OR circuit that outputs different logic information for a case that the logic states are different from each other and a case that they are same as each other. | 12-02-2010 |
20110032780 | Semiconductor device - The semiconductor device includes a first pair of data lines, a second pair of data lines, a third pair of data lines, a first amplifier (SA) connected to the first pair of data lines, a first switch that controls connection between the first pair of data lines and the second pair of data lines, a second switch that controls connection between the second pair of data lines and the third pair of data lines, a second amplifier that amplifies data on the second pair of data lines, for output to the third pair of data lines, a third amplifier connected to the third pair of data lines, and a control circuit that controls the second switch forming a pair of switches. When two data lines constituting the third pair of data lines both assume a first state, the control circuit controls the second switch to be turned off, thereby controlling the second pair of data lines and the third pair of data lines to be disconnected. Output data of the first amplifier is then output to the second pair of data lines via the first switch. When the two data lines constituting the third pair of data lines assume a second state different from the first state according to data output from the third amplifier, the second switch is controlled to be turned on, thereby controlling the second pair of data lines and the third pair of data lines to be connected. Then, the first amplifier receives the data output from the first amplifier. | 02-10-2011 |
20110096613 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of first output terminals | 04-28-2011 |