Patent application number | Description | Published |
20080229154 | Self-referencing redundancy scheme for a content addressable memory - A self-referencing redundancy scheme in a content addressable memory may use a faulty bit table, populated during manufacturing, to indicate, not only the address of all the defective memory locations, but also the data which they should hold. Then, during read out, a read out state machine may access the faulty bit table, determine the data the faulty location should have held, and write that faulty data onto latches associated with the faulty memory elements. | 09-18-2008 |
20080232171 | Phase change memory with program/verify function - A phase change memory includes a plurality of cells for storing data in the form of respective resistance levels, addressing circuits for addressing cells to be programmed, and the resistance levels are determined from comparison of cell currents of addressed cells with a reference current. A reference generator provides the sense amplifier with the reference current. The reference generator is provided with a reference select circuit to select the reference current from a plurality of verify currents based on program data to be stored in the cell. | 09-25-2008 |
20080291719 | Streaming mode programming in phase change memories - A streaming programming mode may be implemented on user command in a phase change memory. In the streaming programming mode, accelerated programming may be achieved by ramping up to a voltage that it used for both reading and programming. Repeated programming operations may be streamed after one ramp up without ramping down the voltage on the memory cells between programming operations. This may save time. In addition, the memory may be read in between programming operations, again, without necessarily ramping down. | 11-27-2008 |
20080298122 | Biasing a phase change memory device - A phase change memory device includes a plurality of cells connected to bitlines and including respective phase change memory elements and cell select devices and an addressing circuit for selectively addressing at least one bitline and one cell connected thereto. A reading column bias circuit supplies a bitline voltage to the addressed bitline and cell. The bitline voltage includes the sum of a safe voltage and a reference select device voltage, wherein the reference voltage is equal to a select device voltage on the select device when a cell current flowing through the phase change memory element and the cell select device is equal to a safe current. The safe voltage and the safe current are such that phase transition of the phase change memory element is prevented in any bias condition including a cell voltage lower than the safe voltage and in any bias condition including the cell current lower than the safe current. | 12-04-2008 |
20090073751 | Interleaved array architecture - A partition may be made up of two planes of memory cells in a phase change memory. These planes may be configured so that they are not adjacent to one another. In some embodiments, this may mean that the adjacent planes may share sensing circuits, reducing the overall size of the memory array. In addition, by using non-adjacent planes to make up a partition, the planes may be spaced in a way which reduces resistance of power conveying lines. This may mean that smaller sized lines may be used, further reducing the size of the overall array. | 03-19-2009 |
20090073752 | Adaptive wordline programming bias of a phase change memory - The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell. | 03-19-2009 |
20090256133 | Multiple layer resistive memory - A resistive memory cell may be composed of four stacked layers. Each layer may be sandwiched by electrodes. Connections may be formed from each of four directions around the stack, for example, aligned with each of four edges where the resistive layers are rectangular. | 10-15-2009 |
20110080777 | Adaptive Wordline Programming Bias of a Phase Change Memory - The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell. | 04-07-2011 |
20110292721 | Adaptive Wordline Programming Bias of a Phase Change Memory - The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell. | 12-01-2011 |
20120268984 | Adaptive Wordline Programming Bias of a Phase Change Memory - The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell. | 10-25-2012 |
20140063897 | NON-VOLATILE MEMORY INCLUDING REFERENCE SIGNAL PATH - Some embodiments include apparatuses and methods having a first memory element and a first select component coupled to the first memory element, a second memory element and a second select component coupled to the second memory element, and an access line shared by the first and second select components. At least one of the embodiments can include a circuit to generate a signal indicating a state of the second memory element based on a first signal developed from a first signal path through the first memory element and a second signal developed from a second signal path through the second memory element. | 03-06-2014 |
20140245107 | REARRANGING WRITE DATA TO AVOID HARD ERRORS - This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error. | 08-28-2014 |