Patent application number | Description | Published |
20080228950 | MEMORY POWER DOWN MODE EXIT METHOD AND SYSTEM - A memory includes a circuit having a set terminal for receiving an input signal indicating a request to exit a power-down mode. The circuit is configured to provide an output signal to enable exiting the power-down mode in response to the input signal before the input signal is latched. | 09-18-2008 |
20080267258 | System and method for monitoring temperature in a multiple die package - A temperature control circuit, comprising: a plurality of temperature sensors each configured to measure a temperature of a corresponding memory chip chosen from a plurality of memory chips, and to generate a sensor output signal that is set to a first voltage if the measured temperature of the corresponding memory chip meets a temperature requirement, and is set to a floating voltage if the measured temperature of the corresponding memory chip does not meet the temperature requirement, the sensor output signal being connected to an intermediate node; a current source connected to the intermediate node; and a control circuit configured to provide chip control signals to the plurality of memory chips. | 10-30-2008 |
20090237972 | MEMORY INCLUDING PERIPHERY CIRCUITRY TO SUPPORT A PORTION OR ALL OF THE MULTIPLE BANKS OF MEMORY CELLS - A memory including periphery circuitry configured to support multiple banks of memory cells. The periphery circuitry includes switches that are set to put the periphery circuitry into a first mode to support a portion of the multiple banks of memory cells and a second mode to support all of the multiple banks of memory cells. | 09-24-2009 |
20130314984 | Processors and Systems Using Phase-Change Memory with and without Bitline-sharing - Methods and systems for phase change memory having high RESET currents. In some sample embodiments, PCM elements share access devices in parallel between bit lines, permitting higher RESET currents to be shared between several access devices without overdriving. Lower individual current densities permit smaller access devices and smaller memories having greater reliability and longer retention. In some sample embodiments, hybrid arrays connect bit lines on only a few word lines, using the shared bits e.g. only for critical information. In some sample embodiments, several PCM elements share a single larger access device which can pass higher currents while still reducing the total memory size. | 11-28-2013 |
20130336047 | Cell Refresh in Phase Change Memory - A memory in which a comparison of PCM memory elements storing logical values to a trigger resistance or to each other can be used to determine the extent of resistance drift since the PCM memory elements were last written. If the comparison determines that the resistance drift has passed a sense margin threshold or a trigger resistance, a memory refresh is triggered and pre-drift resistances corresponding to the stored logical values are written to the PCM memory elements. | 12-19-2013 |
20130336048 | Processors and Systems Using Cell-Refreshed Phase-Change Memory - Systems in which PCM is used, including memory systems, as well as methods for operating such systems. A comparison of PCM memory elements storing logical values to a trigger resistance or to each other can be used to determine the extent of resistance drift since the PCM memory elements were last written. If the comparison determines that the resistance drift has passed a sense margin threshold or a trigger resistance, a memory refresh is triggered and pre-drift resistances corresponding to the stored logical values are written to the PCM memory elements. | 12-19-2013 |
20130336053 | Paralleled Drive Devices Per Bitline in Phase-Change Memory Array - Methods and systems for phase change memory having high RESET currents. In some sample embodiments, PCM elements share access devices in parallel between bit lines, permitting higher RESET currents to be shared between several access devices without overdriving. Lower individual current densities permit smaller access devices and smaller memories having greater reliability and longer retention. In some sample embodiments, hybrid arrays connect bit lines on only a few word lines, using the shared bits e.g. only for critical information. In some sample embodiments, several PCM elements share a single larger access device which can pass higher currents while still reducing the total memory size. | 12-19-2013 |